MAAIL/VI CMOS P-Compatible 12-Bit DAC __tsCGG@nt@ al Deer Features The MX7542 1s a CMOS 12-Bit digitai-to-analog con- @ 12-Bit Resolution and a-Gi rcroprocessors Input data leaded ae V2.LSB Linearly Over Temperature Fae aon ytes. and is then transferred to an internal @ +1 LSB Gain Accuracy (MX7542G) timing is similar to that of a static RAM write cycle. Sppm/C Max. Gain Drift A clear input is also provided which resets the DAC Microprocessor Compatible register to all zeros. This can be used to initialize the @ 40mW Max. Power Dissipation fevice on power up or during software calibration @ 45V Operation Low power consumption, +5V operation, and multi- Ordering information eons, cs high Precision processor conttolied DAG applications. The MX7542 is supplied in 16-lead DIP PART TEMP. RANGE PACKAGE ERROR and Small Outline packages. MX7542JN 0C to +70C ~~Plastic DIP +1 LSB MX7542KN 0C to +70C ~- Plastic DIP + LSB MX7542GKN 0C to +70C ~ Plastic: DIP +% LSB MX7S542SCWE 0C to +70C Smait Outhne +1 LSB Applications MX7542KCWE C to +70C_~ Small Outline + LSB MX7542GKCWE 00C to +70C Small Outline +% LSB Programmable Power Sources - MX7542JC/D 0C to +70G ~sDice +1 LSB Portable Test Equipment MX7542AD -25C to +85C Ceramic +1 LSB Digitally Controlled Filters MX7542BD -25C to +B5C Ceramic + LSB Auto-Calibration Circuitry MX7542GBD s_ -25C. to +85C Ceramic +'4 LSB Motion Control Systems MX7542AQ 28C to +85C == CERDIP** +1 LSB MX75428Q -25C to +B5C = CERDIP** + LSB MX7542GBQ_ s -26C. to +85C_~s CERDIP** +% LSB MX7542SD -55C to +125C =Ceramic +1 LSB . . MX7542TD -6C to +125C ~=Ceramic +' LSB __-__________ Functional Diagram MX7542GTD s- -55C to #125C- Ceramic +' LSB MX7542SQ -55C to #125C +~CERDIP** +1 LSB MX7542TQ -55C to +125C }~=CERDIP** +1: LSB MX7542GTQ ~--55C to +125C = CERDIP"* + LSB MAXIM MX7542 12-BIT MULTIPLYING DAC _ 12-BIT DAG AEGISTER clr Yoo QGNa wa H-BYTE M-BYTE L-BYTE _ OATA DATA OATA cs ADDAESS AEGISTER REGISTER AEGISTER OECOOE Logic al (LS) [SB] * All davices 16 lead packages "* Maxim reserves the right to ship Ceramic packages in tieu of CERDIP packages Pin Configuration Top View MAXIM MX7542 MAXI MAXI vi IS a registered trademark of Maxtm Integrated Products Maxim integrated Products 2-81 < cpsSlXWCMOS P-Compatible 12-Bit DAC ABSOLUTE MAXIMUM RATINGS Vpo tO AGND 0.0... eee ce cece cece nena eens -03V, +7V Vop tO OGND occ ee cee cee nent eee eee eee -0.3V, +7V AGND to DGND 0.0.0... eco c cece cen e eee eee ees Vop DGND to AGND 2.0.0... ec ceeece cece tert ee en eee nes bb Digital Input Voltage to DGND (Pins 4-11, 13) Power Dissipation (derate 6mMW/C above +70C) Operating Temperature Range Commercial MX7542.1, K, GK MX7542 Vent: Vping to AGND Veer t0 AGND Vara to AGND Storage Temperature +25V Industrial MX7542A, B, GB............. Military Mx7542S, T, GT.............. Lead Temperature (Soldering 10 sec) 0C to +70C -25C to +85C ~5C to +125C -65C to +150C +300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not pled. Exposure to absolute maximum ratings conditions for extended periods may affect device rehability ELECTRICAL CHARACTERISTICS (Ta = Twin tO Tax: Yoo = *5Y. Vace = *10V. Vout: = Vout2 = GND, unless otherwise specified) PARAMETER |symBou| CONDITIONS MIN TYP MAX | UNITS DC ACCURACY Resolution 12 Bits MX7542J/A/S +1 Non-Linearity MX 7542K/B/T +0.5 LSB MX7542GK/GB/GT 0.5 MX7542J/A/S (Note 1) +2 Differential Non-Linearity MX7542K/B/T (Note 2) +1 LSB MX7542GK/GB/GT (Note 2) +1 MX7542U/K/A/B/S/T T, = 25C +123 MX7542J/K/A/B Tan tO Trax +135 MX7542S/T T to T, +145 Gain Error MIN MAX LSB MX7542GK/GB/GT T, = 25C +1 MX7542GK/GB Twin tO Tax +1 MX7542GT Twin tO Trax +2 Gain Temperature Coefficient AGain/ATemperature (Note 4) 2 5 pem/ec Power Supply Rejection PSRR | Vop = +4.75V to +5.25V ya = 25C aos 1M min tO Tax 0.01 Ty = 25C 1 Output Leakage Current MX7542J/K/GK Tin to Twax 10 nA lout lours (Note 3) MX7542A/B/GB Tan tO Twrax 10 MX75428/T/GT Twn tO Trax 200 DYNAMIC PERFORMANCE (Note 4) Output Current Settling Time To 1/2 LSB, Outt Load = 1002 2 Ss Feedthrough Error Vaer = +10V 10kHz sine wave 25 mVpp REFERENCE INPUT input Resistance (pin 15) | Rarer | 8 18.25 kQ ANALOG OUTPUT (Note 4) Cour, | DAC Register 6000 0000 0000 75 DAC Register 1111 1111 1111 260 OUT1 Output Capacitance gure | DAC Register 1111 1111 1111 75 pF ours | DAC Register 0000 0000 0000 260 2-82 MAAXAIL/VICMOS P-Compatible 12-Bit DAC ELECTRICAL CHARACTERISTICS (Continued) (Ta = Twin tO Tax: Von = +5. Vaer = +10V, Vout: = Youre = GND, unless otherwise specified) PARAMETER |symBOL | CONDITIONS MIN TYP MAX | untts | LOGIC INPUTS Logic HIGH Voltage Vine +3.0 V Logic LOW Voltage Vint +0.8 Logic Input Current tin OV oF Vop 1 uA Input Capacitance (Note 4) Cin 8 pF SWITCHING CHARACTERISTICS (see Figure 6) (Note 5) : . T, = 26C 120 Write Pulse Width t A me Fulse WR | Th tO Trax 220 . : T, = 26C 50 Address-to-Write Hold Time t A AWH Tun tO Trax 65 ns . T, = 25C 50 hip Select-to-Write Hold t A Chip Select-to-Write Ho! WH Trans tO Traax 100 . : Ta = 25C 200 M CLEAR Pulse Width | t A inimum u i CLR Tray 10 Trrax 300 BYTE LOADING T, = 25C 60 Chip Setect-to-WRITE Setu t A p P OWS Thin to Trax 130 : . T, = 25C 80 Address Valid-to-Write Setu t A P ANS | Thay tO Tax 180 na : T, = 25C 50 Data Setup Time t, A up PS | Tan tO Tax 65 : T, = 26C 50 Hold T t A Data Hold Time DH Teun 10 Trax 65 DAC LOADING T, = 25C 60 Chip Select-to-WRITE Setu t A p P CWS | Thin tO Trax 150 ns . T, = 25C 120 Add lnd-to-Write Set t A ddress valid-to-Write Setup AWS Tran 10 Trax 240 POWER SUPPLY Supply Voltage Voo 5V + 5% 4.75 5.25 Vv Supply Current lop 2.5 mA Note 1: Monotonic to 11 bits from Ty tO Tyax Note 2: Monotonic to 12 bits from Tyyy tO Tyyax Note 3: Io.7, tested with DAC register loaded to all 0's. lgut2 tested with DAC register loaded to all 1's Note 4: Guaranteed by design but not tested Note 5: Sample tested at +25C to ensure compliance. MAAIMNMI 2-83 cpslXWMX7542 CMOS uP-Compatible 12-Bit DAC Detailed Description The basic MX7542 DAC circuit consists of a laser- trimmed, thin-film R-2R resistor array with NMOS current switches as shown in Figure 1. Binarily weighted currents are switched to either OUT1 or OUT2 depending on the status of each input bit. Although the current at OUT1 or OUT2 will depend on the digital input code, the sum of the two output currents is always equal to the input current at Veer minus the termination resistor current (Ry). Either current output can be converted into a voltage externally by adding an output amplifier (Figure 4). The Veer input accepts a wide range of signals in- cluding fixed and time varying voltage or current inputs. If a current source is used for the reference input, then a low temperature coefficient external resistor should be used for Reg to minimize gain variation with temperature. Equivalent Circuit Analysis Figures 2 and 3 show the equivalent circuits for the R-2R ladder when all digital inputs are LOW and HIGH respectively. The input resistance at Vper is nominally 15kQ and does not change with digital input code. The Ipe-/4096 current source, which is actually the ladder termination resistor (Ry, Figure 1), results in an intentional 1-bit current loss to GND. The lLeaxaGe Current sources represent junction and surface leakage currents. Capacitors Coyt, and Coyte represent the switches ON and OFF. capacitances respectively. When all inputs are switched from LOW to HIGH, the capaci- tance at OUT1 changes from approximately 75pF to 260pF. This capacitance is code-dependent and is a function of the number of ON switches that are con- nected to a specific output. Vrer Switches Shown For Inputs High Figure 1 MX7542 Functional Diagram Circuit Configurations Unipolar Operation The most common configuration for the MX7542 is shown in Figure 4. The circuit is used for unipolar binary operation and/or 2-quadrant multiplication. The code table is given in Table 1. Note that the polarity of the output is the inverse of the reference input. In many applications, gain adjustment of the MX7542 will not be necessary. In those cases, and also when gain is trimmed but only at the reference source, resistors Rt and R2 in Figure 4 can be omitted. However, if the trims are desired and the DAC is to operate over a wide temperature range, then low tempco (<300ppm/C) resistors should be used at R1 and R2. Ara OuTt A = 15K VREF OUT2 IREF h IReF anoR LEAKAGE Rre = 15K VRer eae t OUT1 ince 6 x 18: LEAKAGE I 260pF OUT2 g LEAKAGE t 75pF Figure 2. MX7542 DAC Equivalent Circuit. All Digital inputs LOW 2-84 Figure 3: MX7542 DAC Equivalent Circuit, All Digital inputs HIGH MAALWICMOS /P-Compatible 12-Bit DAC Table 1. Code Table Unipolar Binary . DIGITAL INPUT +5v Re MSB LSB ANALOG OUTPUT C1 TOPF-33PF 144datddd414d -Vper ( 2% | out1\! Vin Lis VREF MAXIM > Vout 2048 Vv MX7542 OUT2/3 MAXIM 1000 0000 0000 - aoe: | = - ee DGND _AGND MAX400 REF | 4096. 2 fx2 3 1 = 0000 0000 0001 Veer | a5 TRIM J Ks resistor | A/S er 0000 0000 0000 ov RI 1oon | 100 R2 470 33n Figure 4. Unipolar Binary Operation Table 2. Code Table a Bipolar (Offset Binary) Operation 20k +5V R2* VREF MAXIM MX7542 OUT2/2 , DGND _AGND = = 5kO 10% TRIM resistor | 4S | KOT RI room | 1000 Re 47a_| 330 Figure 5 Bipolar Operation (4-Quadrant Multiplication) Bipolar Operation With the circuit configuration in Figure 5, the Mx7542 operates in the bipolar, or 4-quadrant multiplying mode. A second amplifier and three matched resistors are required. Matching to 0.01% is recommended for 12 bit performance. The code table for the output, which is offset binary, is listed in Table 2. In multi- plying applications, the MSB determines output po- larity while the other 11 bits control amplitude. MAXI/VI DIGITAL INPUT MSB LSB ANALOG OUTPUT 1111 11114114 aoa | *Vaer 2048 10000000 0001 Veer | 5aa5 | 1000 0000 0000 ov 01111111 1111 1 Veer | 2048 2048 Veer | 3548 0000 0000 0000 To adjust the circuit, load the DAC with a code of 1000 0000 0000 and trim R1 for a OV output. With R1 and R2 omitted, an alternative zero trim is to adjust the ratio of R3 and R4 for OV out. Full scale can be trimmed by loading the DAC with all zeros or all ones and adjusting the amplitude of Vac or varying R5 until the desired positive or negative output is obtained. (If gain and offset trims are not required, R1 and R2 in Figure 5 can be omitted. 2-85 cpSlZXWMX7542 CMOS uP-Compatible 12-Bit DAC Interface Logic interface Logic Information The MX7542 Truth Table is shown in Table 3. The high, middie and low byte, 4 bit data registers are loaded separately. The 12-bit DAC register is then loaded with the contents of the 3 data registers. The interface timing (Figure 6) is the same as writing to static RAM. The CLR input asynchronously resets the 12-Bit DAC Register to Code 0000 0000 0000. In a unipolar mode the DAC output will be set to 0 volts. In the bipolar mode a CLR input resets the DAC output to Vper. Notes: 1. 1 indicates logic HIGH 2. 0 indicates togic LOW 3. X indicates don't care 4. indicates LOW to HIGH transition 5. MSB ~ = XXXX XXXX XXXX - LSB high middle low byte byte byte 6 These control signals are level triggered Table 3. MX7542 Truth Table MX7542 Control Inputs = MX7542 Operation A,| A, | CS | WR CLR X |X| xX x 0 | Resets DAC 12-Bit Register to Code 0000 0000 0000 xX |X 1 x 1 |No Operation Device Not Selected o|/o}0 - 1 |Load LOW Byte Data Register On Edge As Shown Load o[1]o | f | 1 [Load MIDDLE Byte ppplicable . ata Data Register On Edge As Shown Register With Data 1} 0} 0 | F} 1 [Load HIGH Byte | At 0,-D, Data Register On Edge As Shown 1/1 0 |LSJ} 1 | Load 12-Bit DAC Register With Data In LOW Byte, MIDDLE Byte & HIGH Byte Data Registers |~___ ADDRESS BUS vatip__-_| \ cs (PIN 8) A0-A1 View (PINS 10. 11) ViL | | { _ tews >| wR t (PIN 9) AWS X jean} tawer | | fo | }~ own twr a 10s >< {pH D3-D0 (PINS 4-7) Ka__K | DATA BUS VALIO NOTE TIMING MEASUREMENT REFERENCE LEVEL IS Vin * Vit 2 Figure 6 MX7542 Timing Diagram MAAI/VICMOS uP-Compatible 12-Bit DAC _ Application information Output Amplifier Offset For best linearity, OUT1 and OUT2 should be termi- nated exactly OV. In most applications OUT1 is con- nected to the summing junction of an inverting op- amp. The amplifiers input offset voltage can degrade the linearity of the DAC by causing OUT1 to be terminated to a non-zero voltage. The resulting error IS: Error Voltage = Vos(1 + Rep/Ro), where Vos is the op-amp's offset voltage and Ro is the output resistance of the DAC. Ro is a function of the digital input code, and varies from approximately 15k to 45k. The error voltage range is then typically 4/3V ag to 2Vog, a change of 2/3Vog. An amplifier with 3mvV of offset will therefore degrade the linearity by 2mvV, almost a full LSB with a 10V reference voltage. For best linearity, a low-offset amplifier such as the MAX400 should be used, or the amplifier offset must be trimmed to zero. A good rule of thumb ts that Vos should be no more than 1/10 of an LSB's value. The output amplifier input bias current (Ip) can also limit performance since lg x Reg generates an offset error. tg should therefore be much less than the DAC output current for 1 LSB, typically 250nA with Vpee = 10V. One tenth of this value, 25nA, is recommended. Offset and linearity can also be impaired if the output amplifiers noninverting input is grounded through a bias current compensation resistor. This resistor adds to offset at this pin and should not be used. Best performance is obtained when the noninverting input is directly connected to ground. Dynamic Considerations In static or DC applications, the AC characteristics of the output amplifier are not critical. In higher speed applications, where either the reference input is an AC signal or the DAC output must quickly settle to a new programmed value, the AC parameters of the output op-amp must be considered. Another error source in dynamic applications is para- sitic coupling of signal from the Vper terminal to OUT1 or OUT2. This is normally a function of board layout and package lead-to-lead capacitance. Signals can also be injected into the DAC outputs when the digital inputs are switched. This digital feedthrough is usually dependent on circuit board layout and on- chip capacitive coupling. Layout induced feedthrough can he minimized with guard traces between digital inputs, Vag, and the DAC outputs. Compensations A compensation capacitor, C1, may be needed when the DAC is used with a high speed output amplifier. The purpose of the capacitor is to cancel the pole formed by the DACs output capacitance and internal feedback resistance. Its value depends on the type of op-amp used but typical values range from 10 to 33pF. Too small a value causes output ringing while excess capacitance overdamps the output. The size of C1 can be minimized, and output settling perform- ance improved, by keeping the PC board trace and stray capacitance at OUT1 as small as possible. Grounding and Bypassing Since OUT1, OUT2 and the output amps noninverting inputs are sensitive to offset voltages, nodes that are to be grounded should be connected directly to single point ground through a separate, very low resistance (less than 0.2Q) path. The current at OUT1 and OUT2 varies with input code, creating a code dependent error if these terminals are connected to ground (or a virtual ground) through a resistive path. A 1pF bypass capacitor, in parallel with a 0.01yuF ceramic cap, should be connected as close to the DAC's Vpp and GND pins as possible. The MX7542 has high-impedance digital inputs. To minimize noise pick-up. they should be tied to either Vop or GND when not used. It is also good practice to connect active inputs to Vpp or GND through high valued resistors (1MQ) to prevent static charge accumulation if these pins are left floating, such as when a circuit card is left unconnected. Chip Topography 4 13 12 Vpp CLR DGND Maw carder assume respansibiity for use of any Curcuttry ofner than curcurtry entrety embodred in a Maxim proguct No circu patent tcenses are .mpted Max reserves the ght [co change the cucurtry and specications wiihou!l notice af any hme MAXALSVI 2-87 cpSZXW