300 MHz to 1100 MHz Balanced Mixer, LO Buffer, and RF Balun ADL5369 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM RF frequency range of 300 MHz to 1100 MHz IF frequency range of 30 MHz to 450 MHz Power conversion loss: 6.2 dB SSB noise figure of 7.2 dB Input IP3 of 28 dBm Typical LO interface return loss of 0 dBm Single-ended, 50 RF and LO input ports High isolation SPDT LO input switch Typical single-supply operation: 3.3 V to 5 V Exposed pad, 5 mm x 5 mm, 20-lead LFCSP VCMI IFOP IFON PWDN COMM 20 19 18 17 16 ADL5369 VPMX 1 15 LOI2 RFIN 2 14 VPSW RFCT 3 13 VGS1 APPLICATIONS Cellular base station receivers Transmit observation receivers Radio link downconverters COMM 4 12 VGS0 COMM 5 11 LOI1 6 7 8 9 10 VLO3 LGM3 VLO2 LOSW NIC NIC = NOT INTERNALLY CONNECTED. 13361-001 BIAS GENERATOR Figure 1. GENERAL DESCRIPTION The ADL5369 uses a highly linear, doubly balanced passive mixer core along with integrated radio frequency (RF) and local oscillator (LO) balancing circuitry to allow single-ended operation. The ADL5369 incorporates an RF balun, allowing optimal performance over a 300 MHz to 1100 MHz RF input frequency range. The balanced passive mixer arrangement provides good LO to RF leakage, typically better than -25 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. The passive mixer core yields a typical power conversion loss of 6.2 dB. The ADL5369 provides two switched LO paths that can be used in time division duplex (TDD) applications where it is desirable to rapidly switch between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5369 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (<200 A) the circuit when desired. The ADL5369 is fabricated using a BiCMOS high performance IC process. The device is available in a 5 mm x 5 mm, 20-lead LFCSP and operates over a -40C to +85C temperature range. An evaluation board is also available. Table 1. Passive Mixers RF Frequency (MHz) 300 to 1100 500 to 1700 1200 to 2500 2200 to 2700 2300 to 2900 Rev. A Single Mixer ADL5369 ADL5367 ADL5365 Not applicable ADL5363 Single Mixer and IF Amp Not applicable ADL5357 ADL5355 ADL5353 Dual Mixer and IF Amp Not applicable ADL5358 ADL5356 ADL5354 Not applicable Not applicable Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5369* PRODUCT PAGE QUICK LINKS Last Content Update: 11/29/2017 COMPARABLE PARTS DESIGN RESOURCES View a parametric search of comparable parts. * ADL5369 Material Declaration * PCN-PDN Information EVALUATION KITS * Quality And Reliability * ADL5369 Evaluation Board * Symbols and Footprints DOCUMENTATION DISCUSSIONS Data Sheet View all ADL5369 EngineerZone Discussions. * ADL5369: 300 MHz to 1100 MHz Balanced Mixer, LO Buffer, and RF Balun Data Sheet SAMPLE AND BUY REFERENCE MATERIALS Visit the product page to see pricing options. Product Selection Guide TECHNICAL SUPPORT * RF, Microwave, and Millimeter Wave IC Selection Guide 2017 Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. 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ADL5369 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 3.3 V Performance Characteristics .......................................... 14 Applications ....................................................................................... 1 Upconversion Characteristics ................................................... 15 Functional Block Diagram .............................................................. 1 Spurious Performance ............................................................... 16 General Description ......................................................................... 1 Circuit Description......................................................................... 17 Revision History ............................................................................... 2 RF Subsystem .............................................................................. 17 Specifications..................................................................................... 3 LO Subsystem ............................................................................. 17 5 V Performance ........................................................................... 4 Applications Information .............................................................. 19 3.3 V Performance ........................................................................ 4 Basic Connections ...................................................................... 19 Absolute Maximum Ratings............................................................ 5 IF Port .......................................................................................... 19 Thermal Resistance ...................................................................... 5 Mixer VGS Control DAC .......................................................... 19 ESD Caution .................................................................................. 5 Evaluation Board ............................................................................ 20 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 23 5 V Performance Characteristics ................................................ 7 REVISION HISTORY 5/16--Rev. 0 to Rev. A Changes to Specifications Section ....................................................... 3 Changes to 5 V Performance Section and 3.3 V Performance Section ......................................................................................................... 4 Changes to Table 5 ..................................................................................... 5 Added Thermal Resistance Section, Table 6, and Junction to Board Thermal Impedance Section; Renumbered Sequentially .................. 5 Changes to RF Frequency Section .................................................. 7 Changes to Temperature Section .................................................... 8 Changes to IF Frequency Section ................................................... 9 Changes to LO Power and Spurious Performance Section ....... 10 Changes to Conversion Loss Distribution, Input IP3 Distribution, and Return Loss Section .................................................................. 11 Changes to Isolation, Leakage, Power Conversion Loss, Input IP3, and SSB Noise Figure Section ............................................... 12 Changes to 3.3 V Performance Characteristics Section ............ 14 Changes to Upconversion Characteristics Section .................... 15 Changes to 5 V Performance Section .......................................... 16 Change to Figure 45 ....................................................................... 19 Change to Figure 46 ....................................................................... 20 Changes to Table 8.......................................................................... 21 1/16--Revision 0: Initial Version Rev. A | Page 2 of 23 Data Sheet ADL5369 SPECIFICATIONS Supply voltage (VS) = 5 V, supply current (IS) = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, ZO = 50 , R9 = 1.7 k, unless otherwise noted. Table 2. Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER-DOWN (PWDN) INTERFACE2 PWDN Threshold Logic 0 Level Logic 1 Level PWDN Response Time PWDN Input Bias Current 1 2 Test Conditions/Comments Min Tunable to >20 dB over a limited bandwidth Typ Unit 1100 dB MHz 450 5.5 ||pF MHz V 10 50 300 Differential impedance, f = 93 MHz Externally generated Max 35.2||11.9 30 3.3 -6 5.0 0 16.5 50 330 +10 1550 1.0 0.4 1.4 Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled Apply the supply voltage from the external circuit through the choke inductors. PWDN function is intended for use with VS 3.6 V only. Rev. A | Page 3 of 23 160 220 0.0 70 dBm dB MHz V V V ns ns A A ADL5369 Data Sheet 5 V PERFORMANCE VS = 5 V, IS = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , R9 = 1.7 k, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Power Conversion Loss Voltage Conversion Loss Single Sideband (SSB) Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB)1 LO to IF Leakage LO to RF Leakage RF to IF Isolation IF/2 Spurious IF/3 Spurious POWER SUPPLY Positive Supply Voltage Total Quiescent Current 1 Test Conditions/Comments Min Typ Including 1:1 IF port transformer and printed circuit board (PCB) loss ZSOURCE = 50 , differential ZLOAD = 50 differential fRF1 = 449.5 MHz, fRF2 = 451.5 MHz, fLO = 543 MHz, each RF tone at 0 dBm fRF1 = 500 MHz, fRF2 = 450 MHz, fLO = 543 MHz, each RF tone at -10 dBm Exceeding 20 dBm RF power results in damage to the device Unfiltered IF output Max 6.2 1.4 7.2 28 dB dB dB dBm 56 dBm 20 dBm dBm dBm dBc dBc dBc 5.5 V mA -16 -27 -42 -57 -60 0 dBm input power 0 dBm input power 4.5 5 84 VS = 5 V Unit Exceeding 20 dBm RF power results in damage to the device. 3.3 V PERFORMANCE VS = 3.3 V, IS = 55 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, R9 = 226 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE Power Conversion Loss SSB Noise Figure IIP3 IIP2 POWER INTERFACE Supply Voltage Quiescent Current Power-Down Current Test Conditions/Comments Min Including 1:1 IF port transformer and PCB loss fRF1 = 449.5 MHz, fRF2 = 451.5 MHz, fLO = 543 MHz, each RF tone at -10 dBm fRF1 = 500 MHz, fRF2 = 450 MHz, fLO = 543 MHz, each RF tone at -10 dBm 3.0 Resistor programmable Device disabled Rev. A | Page 4 of 23 Typ Max Unit 6.5 7.4 24 dB dB dBm 53 dBm 3.3 55 150 3.6 V mA A Data Sheet ADL5369 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter VS RF Input Level LO Input Level IFOP, IFON Bias Voltage VGS0, VGS1, LOSW, PWDN Internal Power Dissipation Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 20 dBm 13 dBm 6.0 V 5.5 V 0.6 W 150C -40C to +85C -65C to +150C 260C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. JA is the junction to ambient thermal resistance (C/W), JB is the junction to board thermal resistance (C/W), and JC is the junction to case thermal resistance (C/W). JC is determined by the mechanical design of the ADL5369 and is optimized to the lowest possible value. JA and JB are functions of the design of the PCB, and are under the control of the user. The data shown in Table 6 is based on a JEDEC standard design and is provided for comparison purposes. Table 6. Thermal Resistance Package Type 20-Lead LFCSP 1 JA1 25 JB1 14.74 JC1 1.08 Unit C/W See JEDEC Standard JESD51-2 for information on optimizing thermal impedance (PCB with 3 x 3 vias). Junction to Board Thermal Impedance The junction to board thermal impedance (JB) is the thermal impedance from the die to or near the component lead of the ADL5369. For the ADL5369, JB was determined experimentally to be 14.74C/W with the device mounted on a 4-layer circuit board (two of the layers being ground planes) in a configuration similar to that of the ADL5369-EVALZ evaluation board. Board size and complexity (number of layers) affect JB; more layers tend to reduce the thermal impedance slightly. If the board temperature is known, use the junction to board thermal impedance to calculate die temperature (also known as junction temperature) to ensure that it does not exceed the specified limit of 150C. For example, if the board temperature is 85C, the die temperature is given by the equation TJ = TB + (PDISS x JB) where: TJ is the junction temperature. TB is the board temperature measured at or near the component lead. PDISS is the power dissipated from the device. The typical worst case power dissipation for the ADL5369 is 522 mW (5.5 V x 95 mA). Therefore, TJ is TJ = 85C + (0.522 W x 14.74C/W) = 92.70C ESD CAUTION Rev. A | Page 5 of 23 ADL5369 Data Sheet 20 19 18 17 16 VCMI IFOP IFON PWDN COMM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 ADL5369 TOP VIEW (Not to Scale) 15 14 13 12 11 LOI2 VPSW VGS1 VGS0 LOI1 NOTES 1. NIC = NOT INTERNALLY CONNECTED. 2. EXPOSED PAD MUST BE SOLDERED TO GROUND. 13361-002 VLO3 LGM3 VLO2 LOSW NIC 6 7 8 9 10 VPMX RFIN RFCT COMM COMM Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4, 5, 16 6, 8 7 9 10 11, 15 12, 13 14 17 18, 19 20 Mnemonic VPMX RFIN RFCT COMM VLO3, VLO2 LGM3 LOSW NIC LOI1, LOI2 VGS0, VGS1 VPSW PWDN IFON, IFOP VCMI EPAD (EP) Description Positive Supply Voltage for the IF Amplifier. RF Input. This pin must be ac-coupled. RF Balun Center Tap (AC Ground). Device Common (DC Ground). Positive Supply Voltages for LO Amplifier. LO Amplifier Bias Control. LO Switch. LOI1 is selected for 0 V, or LOI2 is selected for 3 V. Not Internally Connected. LO Inputs. These pins must be ac-coupled. Mixer Gate Bias Controls (3 V Logic). Ground these pins for the nominal setting. Positive Supply Voltage for LO Switch. Power-Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode. Differential IF Outputs. No Connect. This pin can be grounded. Exposed Pad. The exposed pad must be soldered to ground. Rev. A | Page 6 of 23 Data Sheet ADL5369 TYPICAL PERFORMANCE CHARACTERISTICS 5 V PERFORMANCE CHARACTERISTICS RF Frequency VS = 5 V, IS = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 , unless otherwise noted. 0.100 SUPPLY CURRENT (A) 0.095 90 -40C +25C +85C 80 -40C +25C +85C 70 INPUT IP2 (dBm) 0.090 0.085 0.080 60 50 40 0.075 500 600 700 800 900 1000 1100 20 300 RF FREQUENCY (MHz) 400 SSB NOISE FIGURE (dB) 4 2 500 600 700 800 900 1000 1100 -40C +25C +85C 12 10 8 6 4 0 300 13361-004 400 30 25 20 600 700 800 900 RF FREQUENCY (MHz) 1000 1100 13361-005 15 500 500 600 700 800 900 1000 Figure 7. SSB Noise Figure vs. RF Frequency -40C +25C +85C 400 400 RF FREQUENCY (MHz) Figure 4. Power Conversion Loss vs. RF Frequency INPUT IP3 (dBm) 1100 2 RF FREQUENCY (MHz) 10 300 1000 Figure 5. Input IP3 vs. RF Frequency Rev. A | Page 7 of 23 1100 13361-007 CONVERSION LOSS (dB) 6 35 900 14 8 40 800 16 10 0 300 700 Figure 6. Input IP2 vs. RF Frequency -40C +25C +85C 12 600 RF FREQUENCY (MHz) Figure 3. Supply Current vs. RF Frequency 14 500 13361-006 400 13361-003 0.070 300 30 ADL5369 Data Sheet Temperature VS = 5 V, IS = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 , unless otherwise noted. 0.100 4.75V 5V 5.25V 4.75V 5V 5.25V 57 0.085 0.080 55 53 51 0.075 49 0.070 47 0.065 -40 -20 0 20 40 60 80 45 -45 TEMPERATURE (C) -25 10 4.75V 5V 5.25V 9 6.5 6.0 5.5 5.0 20 40 60 80 6 4.75V 5V 5.25V 30 29 28 27 26 0 20 40 TEMPERATURE (C) 60 80 13361-010 25 -20 -20 0 20 40 60 Figure 12. SSB Noise Figure vs. Temperature 31 IPNUT IP3 (dBm) 7 TEMPERATURE (C) 32 24 -40 4.75V 5V 5.25V 8 4 -40 Figure 9. Power Conversion Loss vs. Temperature 33 75 Figure 10. Input IP3 vs. Temperature Rev. A | Page 8 of 23 80 13361-012 0 13361-009 -20 TEMPERATURE (C) 34 55 5 4.5 4.0 -40 35 Figure 11. Input IP2 vs. Temperature SSB NOISE FIGURE (dB) CONVERSION LOSS (dB) 7.0 15 TEMPERATURE (C) Figure 8. Supply Current vs. Temperature 8.0 -5 13361-011 INPUT IP2 (dBm) 0.090 13361-008 SUPPLY CURRENT (A) 0.095 59 Data Sheet ADL5369 IF Frequency VS = 5 V, IS = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 , unless otherwise noted. 0.100 0.095 60 0.090 INPUT IP2 (dBm) 0.085 0.080 0.075 -40C +25C +85C 55 50 45 80 130 180 230 280 330 380 35 30 13361-013 0.070 30 430 IF FREQUENCY (MHz) 80 330 380 430 380 430 12 SSB NOISE FIGURE (dB) CONVERSION LOSS (dB) 280 14 8 6 4 2 10 8 6 4 2 80 130 180 230 280 330 380 430 IF FREQUENCY (MHz) 0 30 13361-014 0 30 26.0 25.5 -40C +25C +85C 24.5 24.0 23.5 23.0 22.5 22.0 130 180 230 280 330 IF FREQUENCY (MHz) 380 430 13361-015 21.5 80 130 180 230 280 330 Figure 17. SSB Noise Figure vs. IF Frequency 25.0 21.0 30 80 IF FREQUENCY (MHz) Figure 14. Power Conversion Loss vs. IF Frequency INPUT IP3 (dBm) 230 Figure 16. Input IP2 vs. IF Frequency -40C +25C +85C 10 180 IF FREQUENCY (MHz) Figure 13. Supply Current vs. IF Frequency 12 130 13361-016 40 13361-017 SUPPLY CURRENT (A) 65 -40C +25C +85C Figure 15. Input IP3 vs. IF Frequency Rev. A | Page 9 of 23 ADL5369 Data Sheet LO Power and Spurious Performance VS = 5 V, IS = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 , unless otherwise noted. -30 6.0 5.5 -50 -60 -70 5.0 -80 4.5 -90 -4 -2 0 2 4 6 8 10 LO POWER (dBm) -100 300 34 600 700 800 900 1000 1100 1100 Figure 21. IF/2 Spurious vs. RF Frequency -20 -40C +25C +85C -30 33 IF/3 SPURIOUS (dBc) 32 INPUT IP3 (dBm) 500 RF FREQUENCY (MHz) Figure 18. Power Conversion Loss vs. LO Power 35 400 13361-021 IF/2 SPURIOUS (dBc) 6.5 4.0 -6 -40C +25C +85C -40 7.0 13361-018 CONVERSION LOSS (dB) 7.5 -20 -40C +25C +85C 13361-022 8.0 31 30 29 28 -40C +25C +85C -40 -50 -60 -70 27 -80 25 -6 -4 -2 0 2 4 6 8 10 LO POWER (dBm) 13361-019 26 Figure 19. Input IP3 vs. LO Power 60 59 -40C +25C +85C 56 55 54 53 52 51 -2 0 2 4 6 LO POWER (dBm) 8 10 13361-020 INPUT IP2 (dBm) 57 -4 400 500 600 700 800 900 1000 RF FREQUENCY (MHz) Figure 22. IF/3 Spurious vs. RF Frequency 58 50 -6 -90 300 Figure 20. Input IP2 vs. LO Power Rev. A | Page 10 of 23 Data Sheet ADL5369 Conversion Loss Distribution, Input IP3 Distribution, and Return Loss VS = 5 V, IS = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 , unless otherwise noted. 80 -5 RF RETURN LOSS (dB) 0 60 40 20 -10 -15 5.8 6.0 6.2 6.4 -25 300 13361-024 0 6.6 CONVERSION LOSS (dB) 400 500 600 700 800 900 1000 1100 13361-027 -20 1200 13361-028 PERCENTAGE (%) 100 RF FREQUENCY (MHz) Figure 26. RF Port Return Loss, Fixed IF vs. Frequency Figure 23. Conversion Loss Distribution 0 100 -5 LO RETURN LOSS (dB) PERCENTAGE (%) 80 60 40 -10 SELECTED -15 UNSELECTED -20 -25 20 -30 24 25 26 27 28 29 30 31 32 INPUT IP3 (dBm) -35 300 13361-023 0 18 25 16 20 14 15 12 100 150 200 IF FREQUENCY (MHz) 250 10 300 CAPACITANCE (pF) 30 13361-026 RESISTANCE () 35 50 600 700 800 900 1000 1100 Figure 27. LO Return Loss vs. LO Frequency, Selected and Unselected 22 R11 LO1 R11 LO2 C11 (pF )LO1 C11 (pF) LO2 20 10 500 LO FREQUENCY (MHz) Figure 24. Input IP3 Distribution 40 400 Figure 25. IF Port Return Loss Rev. A | Page 11 of 23 ADL5369 Data Sheet Isolation, Leakage, Power Conversion Loss, Input IP3, and SSB Noise Figure VS = 5 V, IS = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 , unless otherwise noted. 70 65 -25 LO TO RF LEAKAGE (dBm) 60 55 50 -35 500 600 700 800 900 1000 1100 RF FREQUENCY (MHz) -45 393 13361-029 400 2 LO LEAKAGE (dBm) -55 -60 1193 -30 -35 2LO TO IF -40 -45 2LO TO RF 500 600 700 800 900 1000 1100 -55 393 13361-030 400 RF FREQUENCY (MHz) 493 593 693 793 893 993 1093 1193 1193 LO FREQUENCY (MHz) Figure 29. RF to IF Isolation vs. RF Frequency Figure 32. 2LO Leakage vs. LO Frequency -20 -40C +25C +85C -25 -10 3LO LEAKAGE (dBm) -30 -15 -20 -25 -30 -35 3LO TO RF -40 -45 3LO TO IF -35 -50 -40 -55 493 593 693 793 893 993 1093 LO FREQUENCY (MHz) 1193 13361-031 LO TO IF LEAKAGE (dBm) 1093 -50 -65 -45 393 993 13361-033 RF TO IF ISOLATION (dBc) -50 -5 893 -25 -45 0 793 -20 -40 -70 300 693 Figure 31. LO to RF Leakage vs. LO Frequency -40C +25C +85C -35 593 LO FREQUENCY (MHz) Figure 28. LO Switch Isolation vs. RF Frequency -30 493 13361-032 -40 45 40 300 -30 13361-034 LO SWITCH ISOLATION (dB) -20 -40C +25C +85C Figure 30. LO to IF Leakage vs. LO Frequency -60 393 493 593 693 793 893 993 1093 LO FREQUENCY (MHz) Figure 33. 3LO Leakage vs. LO Frequency Rev. A | Page 12 of 23 Data Sheet ADL5369 40 17 9 6 5 11 4 9 3 NOISE FIGURE 2 VGS = 0, VGS = 0, VGS = 1, VGS = 1, 1 0 300 400 500 600 700 800 900 1000 30 NOISE FIGURE (dB) 13 CONVERSION LOSS SSB NOISE FIGURE (dB) 7 RF FREQUENCY (MHz) Figure 34. Power Conversion Loss and SSB Noise Figure vs. RF Frequency 35 30 0 1 0 1 20 15 10 5 400 500 600 700 800 900 RF FREQUENCY (MHz) 1000 1100 13361-036 INPUT IP3 (dBm) 25 0 300 20 15 5 5 1100 VGS = 0, VGS = 0, VGS = 1, VGS = 1, 25 10 7 0 1 0 1 13361-035 CONVERSION LOSS (dB) 35 15 8 Figure 35. Input IP3 vs. RF Frequency Rev. A | Page 13 of 23 0 -30 -25 -20 -15 -10 -5 0 BLOCKER POWER (dBm) Figure 36. SSB Noise Figure vs.10 MHz Offset Blocker Level 5 13361-037 10 ADL5369 Data Sheet 3.3 V PERFORMANCE CHARACTERISTICS VS = 3.3 V, IS = 56 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, R9 = 226 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted. 0.08 80 -40C +25C +85C 70 -40C +25C +85C 60 INPUT IP2 (dBm) SUPPLY CURRENT (A) 0.07 0.06 0.05 50 40 30 0.04 400 500 600 700 800 900 1000 1100 RF FREQUENCY (MHz) 10 300 13361-038 0.03 300 400 12 600 700 800 900 1000 1100 RF FREQUENCY (MHz) Figure 40. Input IP2 vs. RF Frequency Figure 37. Supply Current vs. RF Frequency 14 500 13361-041 20 18 -40C +25C +85C 16 -40C +25C +85C SSB NOISE FIGURE (dB) CONVERSION LOSS (dB) 14 10 8 6 4 12 10 8 6 4 2 500 600 700 800 900 1000 1100 RF FREQUENCY (MHz) -40C +25C +85C 25 20 15 400 500 600 700 800 RF FREQUENCY (MHz) 900 1000 13361-040 INPUT IP3 (dBm) 30 10 300 400 500 600 700 800 900 1000 RF FREQUENCY (MHz) Figure 41. SSB Noise Figure vs. RF Frequency Figure 38. Power Conversion Loss vs. RF Frequency 35 0 300 Figure 39. Input IP3 vs. RF Frequency Rev. A | Page 14 of 23 1100 13361-042 400 13361-039 0 300 2 Data Sheet ADL5369 UPCONVERSION CHARACTERISTICS TA = 25C, fIF = 93 MHz, fLO = 543 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 , unless otherwise noted. 16 14 25 10 8 6 20 15 10 4 500 600 700 800 RF FREQUENCY (MHz) 900 1000 1100 13361-043 400 Figure 42. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion Rev. A | Page 15 of 23 0 300 400 500 600 700 800 900 1000 1100 RF FREQUENCY (MHz) Figure 43. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion 13361-044 5 2 0 300 -40C +25C +85C 30 12 INPUT IP3 (dBm) CONVERSION LOSS (dB) 35 -40C +25C +85C ADL5369 Data Sheet SPURIOUS PERFORMANCE All spur tables are (N x fRF) - (M x fLO) and were measured using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = -100 dBm. 5 V Performance VS = 5 V, IS = 84 mA, TA = 25C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 , unless otherwise noted. M 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 -41.537 -71.919 -95.982 <-100 <-100 <-100 1 -16.885 0 -50.753 -72.895 -78.49 <-100 <-100 <-100 2 -33.42 -45.535 -58.999 -79.147 -93.128 <-100 <-100 <-100 <-100 <-100 3 -42.57 -17.948 -60.289 -64.17 -81.092 <-100 <-100 <-100 <-100 <-100 <-100 4 -38.358 -54.779 -72.545 -90.573 -99.503 -95.9 <-100 <-100 <-100 <-100 <-100 <-100 <-100 5 -49.375 -32.507 -70.273 -70.476 -87.794 -90.504 <-100 <-100 <-100 <-100 <-100 <-100 <-100 6 -61.446 -47.242 -58.881 -92.162 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 Rev. A | Page 16 of 23 7 -49.819 -42.403 -73.383 -81.353 -99.13 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 8 -51.873 -45.589 -65.824 -87.574 -98.082 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 9 -60.951 -45.324 -78.819 -89.786 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 10 -52.666 -67.094 -68.754 -82.829 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 11 -60.115 -47.641 -97.834 -93.849 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 12 -61.09 -61.494 -72.556 -86.249 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 Data Sheet ADL5369 CIRCUIT DESCRIPTION The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. The ADL5369 consists of two primary components: the RF subsystem and the LO subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size. Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M x N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the IF output. This termination is accomplished by the addition of a sum network between the IF output and the mixer. The RF subsystem consists of an integrated, low loss RF balun, passive metal-oxide semiconductor field-effect transistor (MOSFET) mixer, sum termination network, and IF amplifier. The LO subsystem consists of a single pole, double throw (SPDT)terminated FET switch and a three-stage limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. Additionally, dc current can be saved by reducing the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the device. Note that no performance enhancement is obtained by reducing the value of the resistors; reducing the value of the resistors may result in excessive dc power dissipation. A block diagram of the device is shown in Figure 44. VCMI IFOP IFON PWDN COMM 20 19 18 17 16 LO SUBSYSTEM The LO amplifier provides a large signal level to the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 700 MHz. The best operation is achieved with high-side LO injection for RF signals in the 300 MHz to 1100 MHz range. Operation outside these ranges is permissible, and conversion loss is extremely wideband, easily spanning 300 MHz to 1100 MHz, but intermodulation is optimal over the aforementioned ranges. ADL5369 15 LOI2 VPMX 1 RFIN 2 14 VPSW RFCT 3 13 VGS1 BIAS GENERATOR 12 VGS0 COMM 5 11 LOI1 6 7 8 9 10 VLO3 LGM3 VLO2 LOSW NIC 13361-047 COMM 4 NIC = NOT INTERNALLY CONNECTED. Figure 44. Simplified Schematic RF SUBSYSTEM The single-ended, 50 RF input is internally transformed to a balanced signal using a low loss (<1 dB), unbalanced to balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, using a blocking capacitor is recommended to avoid running excessive dc current through the device. The RF balun can easily support an RF input frequency range of 300 MHz to 1100 MHz. The ADL5369 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses. The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from -6 dBm to +10 dBm, but the circuit continues to function at considerably lower levels of LO input power. Rev. A | Page 17 of 23 ADL5369 Data Sheet The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5369 has a power-down mode that permits the dc current to drop to <200 A. All of the logic inputs work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to 5.5 V, although a small bias current is drawn. Rev. A | Page 18 of 23 Data Sheet ADL5369 APPLICATIONS INFORMATION BASIC CONNECTIONS IF PORT The ADL5369 mixer is designed to upconvert or downconvert between radio frequencies (RF) from 300 MHz to 1100 MHz and intermediate frequencies (IF) from 30 MHz to 450 MHz. Figure 45 depicts the basic connections of the mixer. It is recommended to ac-couple the RF and LO input ports to prevent non-zero dc voltages from damaging the RF balun or LO input circuit. The RFIN capacitor value of 8 pF is recommended to provide the optimized RF input return loss for the desired frequency band. The real part of the output impedance is approximately 50 , as seen in Figure 25, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion loss that is approximately the same as the power conversion loss, as shown in Table 3. MIXER VGS CONTROL DAC The ADL5369 features two logic control pins, Pin 12 (VGS0) and Pin 13 (VGS1), that allow programmability for internal gate to source voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults both VGS0 and VGS1 to ground. Power conversion loss, NF, and IIP3 can be optimized, as shown in Figure 34 and Figure 35. For upconversion, drive the IF inputs, Pin 18 (IFON) and Pin 19 (IFOP), differentially or use a 1:1 ratio transformer for singleended operation. An 8 pF capacitor is recommended for the RF output, Pin 2 (RFIN). IF1_OUT R1 0 T1 910 +5V C24 560pF C25 560pF 20 19 10k 18 17 10pF 4.7F 16 ADL5369 +5V 100pF 1 15 2 14 LO2_IN 100pF RFIN +5V 10pF 3 13 10pF BIAS GENERATOR 4 12 5 11 100pF 6 7 8 9 RBIAS LO 10 10k +5V 10pF LO1_IN 10pF Figure 45. Typical Application Circuit Rev. A | Page 19 of 23 13361-048 0.01F ADL5369 Data Sheet EVALUATION BOARD Table 8 describes the various configuration options of the evaluation board. Evaluation board layout is shown in Figure 47 to Figure 50. An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 46. The evaluation board is fabricated using Rogers(R) RO3003 material. IF1_OUT R1 0 T1 C25 560pF C24 560pF R14 910 C21 10pF VPOS COMM PWDN IFON VGS0 COMM LOI1 C6 10pF C22 1nF VGS1 COMM R22 10k R23 15k VGS1 VGS0 LO1_IN NIC LOSW VLO2 C4 10pF VLO3 C5 0.01F ADL5369 RFCT VPOS C20 10pF VPSW LGM3 C1 100pF LO2_IN LOI2 VPMX RFIN RFIN C12 100pF C10 100pF LOSEL R9 1.7k C8 10pF VPOS NIC = NOT INTERNALLY CONNECTED. Figure 46. Evaluation Board Schematic Rev. A | Page 20 of 23 R4 10k 13361-049 C2 10F IFOP L3 0 VCMI VPOS PWR_UP R21 10k Data Sheet ADL5369 Table 8. Evaluation Board Configuration Components C2, C6, C8, C20, C21 C1, C4, C5 T1, R1, C24, C25 C10, C12, R4 R21 C22, L3, R9, R14, R22, R23, VGS0, VGS1 Description Power supply decoupling. Nominal supply decoupling consists of a 10 F capacitor to ground in parallel with a 10 pF capacitor to ground positioned as close to the device as possible. RF input interface. The input channels are ac-coupled through C1. C4 and C5 provide bypassing for the center taps of the RF input baluns. IF output interface. T1 is a 1:1 impedance transformer used to provide a single-ended IF output interface. Remove R1 for balanced output operation. C24 and C25 are used to block the dc bias at the IF ports. LO interface. C10 and C12 provide ac coupling for the LO1_IN and LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is enabled when the LOSEL test point is logic low. LO2_IN is enabled when LOSEL is pulled to logic high. PWDN interface. R21 pulls the PWDN logic low and enables the device. The PWR_UP test point allows the PWDN interface to be exercised using the an external logic generator. Grounding the PWDN pin for nominal operation is allowed. Using the PWDN pin when supply voltages exceed 3.3 V is not allowed. Bias control. R22 and R23 form a voltage divider to provide 3 V for logic control, bypassed to ground through C22. VGS0 and VGS1 jumpers provide programmability at the VGS0 and VGS1 pins. It is recommended to pull these two pins to ground for nominal operation. R9 sets the bias point for the internal LO buffers. Rev. A | Page 21 of 23 Default Conditions C2 = 10 F (Size 0603), C6, C8, C20, C21 = 10 pF (Size 0402) C1 = 100 pF (Size 0402), C4 = 10 pF (Size 0402), C5 = 0.01 F (Size 0402) T1 = TC1-1-13M+ (Mini-Circuits), R1 = 0 (Size 0402), C24, C25 = 560 pF (Size 0402) C10, C12 = 100 pF (Size 0402), R4 = 10 k (Size 0402) R21 = 10 k (Size 0402) C22 = 1 nF (Size 0402), L3 = 0 (Size 0603), R9 = 1.7 k (Size 0402), R14 = 910 (Size 0402), R22 = 10 k (Size 0402), R23 = 15 k (Size 0402), VGS0 = VGS1 = 3-pin shunt 13361-052 Data Sheet 13361-050 ADL5369 13361-051 13361-053 Figure 49. Evaluation Board Power Plane, Internal Layer 2 Figure 47. Evaluation Board Top Layer Figure 48. Evaluation Board Ground Plane, Internal Layer 1 Figure 50. Evaluation Board Bottom Layer Rev. A | Page 22 of 23 Data Sheet ADL5369 OUTLINE DIMENSIONS PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.35 0.28 0.23 0.65 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 5 3.25 3.10 SQ 2.95 11 0.80 0.75 0.70 0.70 0.60 0.40 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHC. 111908-A TOP VIEW Figure 51. 20-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.75 mm Package Height (CP-20-9) Dimensions shown in millimeters ORDERING GUIDE Model1 ADL5369ACPZ-R7 ADL5369-EVALZ 1 Temperature Range -40C to +85C Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP], 7" Tape and Reel Evaluation Board Z = RoHS Compliant Part. (c)2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13361-0-5/16(A) Rev. A | Page 23 of 23 Package Option CP-20-9 Ordering Quantity 1,500 1