300 MHz to 1100 MHz Balanced Mixer,
LO Buffer, and RF Balun
Data Sheet ADL5369
Rev. A Document Feedback
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Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
RF frequency range of 300 MHz to 1100 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion loss: 6.2 dB
SSB noise figure of 7.2 dB
Input IP3 of 28 dBm
Typical LO interface return loss of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Typical single-supply operation: 3.3 V to 5 V
Exposed pad, 5 mm × 5 mm, 20-lead LFCSP
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
FUNCTIONAL BLOCK DIAGRAM
2
3
1
20 19 18 17 16
678910
4
5
14
13
15
12
BIAS
GENERATOR
VPMX
RFIN
RFCT
COMM
COMM
LOI2
VPSW
VGS1
VGS0
LOI1
V
CMI IFOP IFON PWDN COMM
VLO3 LGM3 VLO2 LOSW NIC
ADL5369
NIC = NOT INTERNALLY CONNECTED.
11
13361-001
Figure 1.
GENERAL DESCRIPTION
The ADL5369 uses a highly linear, doubly balanced passive mixer
core along with integrated radio frequency (RF) and local oscillator
(LO) balancing circuitry to allow single-ended operation. The
ADL5369 incorporates an RF balun, allowing optimal performance
over a 300 MHz to 1100 MHz RF input frequency range. The
balanced passive mixer arrangement provides good LO to RF
leakage, typically better than −25 dBm, and excellent intermod-
ulation performance. The balanced mixer core also provides
extremely high input linearity, allowing the device to be used in
demanding cellular applications where in-band blocking signals
may otherwise result in the degradation of dynamic perform-
ance. The passive mixer core yields a typical power conversion loss
of 6.2 dB.
The ADL5369 provides two switched LO paths that can be
used in time division duplex (TDD) applications where it is
desirable to rapidly switch between two local oscillators. LO
current can be externally set using a resistor to minimize dc
current commensurate with the desired level of performance.
For low voltage applications, the ADL5369 is capable of operation
at voltages down to 3.3 V with substantially reduced current.
Under low voltage operation, an additional logic pin is provided
to power down (<200 µA) the circuit when desired.
The ADL5369 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
Single
Mixer
Single Mixer
and IF Amp
Dual Mixer
and IF Amp
300 to 1100 ADL5369 Not applicable Not applicable
500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500 ADL5365 ADL5355 ADL5356
2200 to 2700 Not
applicable
ADL5353 ADL5354
2300 to 2900 ADL5363 Not applicable Not applicable
ADL5369* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/29/2017
COMPARABLE PARTS
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EVALUATION KITS
•ADL5369 Evaluation Board
DOCUMENTATION
Data Sheet
•ADL5369: 300 MHz to 1100 MHz Balanced Mixer, LO
Buffer, and RF Balun Data Sheet
REFERENCE MATERIALS
Product Selection Guide
•RF, Microwave, and Millimeter Wave IC Selection Guide
2017
DESIGN RESOURCES
•ADL5369 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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ADL5369 Data Sheet
Rev. A | Page 2 of 23
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Performance ........................................................................... 4
3.3 V Performance ........................................................................ 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance Characteristics ................................................ 7
3.3 V Performance Characteristics .......................................... 14
Upconversion Characteristics ................................................... 15
Spurious Performance ............................................................... 16
Circuit Description......................................................................... 17
RF Subsystem .............................................................................. 17
LO Subsystem ............................................................................. 17
Applications Information .............................................................. 19
Basic Connections ...................................................................... 19
IF Port .......................................................................................... 19
Mixer VGS Control DAC .......................................................... 19
Evaluation Board ............................................................................ 20
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
5/16—Rev. 0 to Rev. A
Changes to Specifications Section ....................................................... 3
Changes to 5 V Performance Section and 3.3 V Performance
Section ......................................................................................................... 4
Changes to Table 5 ..................................................................................... 5
Added Thermal Resistance Section, Table 6, and Junction to Board
Thermal Impedance Section; Renumbered Sequentially .................. 5
Changes to RF Frequency Section .................................................. 7
Changes to Temperature Section .................................................... 8
Changes to IF Frequency Section ................................................... 9
Changes to LO Power and Spurious Performance Section ....... 10
Changes to Conversion Loss Distribution, Input IP3 Distribution,
and Return Loss Section .................................................................. 11
Changes to Isolation, Leakage, Power Conversion Loss, Input
IP3, and SSB Noise Figure Section ............................................... 12
Changes to 3.3 V Performance Characteristics Section ............ 14
Changes to Upconversion Characteristics Section .................... 15
Changes to 5 V Performance Section .......................................... 16
Change to Figure 45 ....................................................................... 19
Change to Figure 46 ....................................................................... 20
Changes to Table 8 .......................................................................... 21
1/16—Revision 0: Initial Version
Data Sheet ADL5369
Rev. A | Page 3 of 23
SPECIFICATIONS
Supply voltage (VS) = 5 V, supply current (IS) = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, ZO = 50 Ω,
R9 = 1.7 k, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RF INPUT INTERFACE
Return Loss Tunable to >20 dB over a limited bandwidth 10 dB
Input Impedance 50 Ω
RF Frequency Range 300 1100 MHz
OUTPUT INTERFACE
Output Impedance Differential impedance, f = 93 MHz 35.2||11.9 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V
LO INTERFACE
LO Power −6 0 +10 dBm
Return Loss 16.5 dB
Input Impedance 50 Ω
LO Frequency Range 330 1550 MHz
POWER-DOWN (PWDN) INTERFACE2
PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 220 ns
PWDN Input Bias Current Device enabled 0.0 μA
Device disabled 70 μA
1 Apply the supply voltage from the external circuit through the choke inductors.
2 PWDN function is intended for use with VS ≤ 3.6 V only.
ADL5369 Data Sheet
Rev. A | Page 4 of 23
5 V PERFORMANCE
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, R9 = 1.7 k, unless
otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Loss Including 1:1 IF port transformer and printed circuit board (PCB) loss 6.2 dB
Voltage Conversion Loss ZSOURCE = 50 Ω, differential ZLOAD = 50 Ω differential 1.4 dB
Single Sideband (SSB) Noise Figure 7.2 dB
Input Third-Order Intercept (IIP3) fRF1 = 449.5 MHz, fRF2 = 451.5 MHz, fLO = 543 MHz, each RF tone
at 0 dBm
28 dBm
Input Second-Order Intercept (IIP2) fRF1 = 500 MHz, fRF2 = 450 MHz, fLO = 543 MHz, each RF tone
at −10 dBm
56 dBm
Input 1 dB Compression Point (IP1dB)1 Exceeding 20 dBm RF power results in damage to the device 20 dBm
LO to IF Leakage Unfiltered IF output −16 dBm
LO to RF Leakage −27 dBm
RF to IF Isolation −42 dBc
IF/2 Spurious 0 dBm input power −57 dBc
IF/3 Spurious 0 dBm input power −60 dBc
POWER SUPPLY
Positive Supply Voltage 4.5 5 5.5 V
Total Quiescent Current VS = 5 V 84 mA
1 Exceeding 20 dBm RF power results in damage to the device.
3.3 V PERFORMANCE
VS = 3.3 V, IS = 55 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Loss Including 1:1 IF port transformer and PCB loss 6.5 dB
SSB Noise Figure 7.4 dB
IIP3 fRF1 = 449.5 MHz, fRF2 = 451.5 MHz, fLO = 543 MHz, each RF
tone at −10 dBm
24 dBm
IIP2 fRF1 = 500 MHz, fRF2 = 450 MHz, fLO = 543 MHz, each RF tone
at −10 dBm
53 dBm
POWER INTERFACE
Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 55 mA
Power-Down Current Device disabled 150 μA
Data Sheet ADL5369
Rev. A | Page 5 of 23
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VS 5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
IFOP, IFON Bias Voltage 6.0 V
VGS0, VGS1, LOSW, PWDN 5.5 V
Internal Power Dissipation 0.6 W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is the junction to ambient thermal resistance (°C/W), θJB is
the junction to board thermal resistance (°C/W), and θJC is the
junction to case thermal resistance (°C/W). θJC is determined by
the mechanical design of the ADL5369 and is optimized to the
lowest possible value. θJA and θJB are functions of the design of
the PCB,and are under the control of the user. The data shown
in Table 6 is based on a JEDEC standard design and is provided
for comparison purposes.
Table 6. Thermal Resistance
Package Type θJA1 θ
JB1 θ
JC1 Unit
20-Lead LFCSP 25 14.74 1.08 °C/W
1 See JEDEC Standard JESD51-2 for information on optimizing thermal
impedance (PCB with 3 × 3 vias).
Junction to Board Thermal Impedance
The junction to board thermal impedance (θJB) is the thermal
impedance from the die to or near the component lead of the
ADL5369. For the ADL5369, θJB was determined experimentally to
be 14.74°C/W with the device mounted on a 4-layer circuit board
(two of the layers being ground planes) in a configuration
similar to that of the ADL5369-EVALZ evaluation board. Board
size and complexity (number of layers) affect θJB; more layers tend
to reduce the thermal impedance slightly.
If the board temperature is known, use the junction to board
thermal impedance to calculate die temperature (also known as
junction temperature) to ensure that it does not exceed the speci-
fied limit of 150°C. For example, if the board temperature is
85°C, the die temperature is given by the equation
TJ = TB + (PDISS × θJB)
where:
TJ is the junction temperature.
TB is the board temperature measured at or near the component
lead.
PDISS is the power dissipated from the device.
The typical worst case power dissipation for the ADL5369 is
522 mW (5.5 V × 95 mA). Therefore, TJ is
TJ = 85°C + (0.522 W × 14.74°C/W) = 92.70°C
ESD CAUTION
ADL5369 Data Sheet
Rev. A | Page 6 of 23
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPMX
RFIN
RFCT
COMM
COMM
VGS1
VPSW
LOI2
VGS0
LOI1
VLO3
LGM3
VLO2
NIC
LOSW
IFON
IFOP
VCMI
PWDN
COMM
14
13
12
1
3
4
15
11
2
5
7
6
8
9
10
19
20
18
17
16
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2
. EXPOSED PAD MUST BE SOLDERED TO GROUND.
ADL5369
TOP VIEW
(Not to Scale)
13361-002
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 VPMX Positive Supply Voltage for the IF Amplifier.
2 RFIN RF Input. This pin must be ac-coupled.
3 RFCT RF Balun Center Tap (AC Ground).
4, 5, 16 COMM Device Common (DC Ground).
6, 8 VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
7 LGM3 LO Amplifier Bias Control.
9 LOSW LO Switch. LOI1 is selected for 0 V, or LOI2 is selected for 3 V.
10 NIC Not Internally Connected.
11, 15 LOI1, LOI2 LO Inputs. These pins must be ac-coupled.
12, 13 VGS0, VGS1 Mixer Gate Bias Controls (3 V Logic). Ground these pins for the nominal setting.
14 VPSW Positive Supply Voltage for LO Switch.
17 PWDN Power-Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode.
18, 19 IFON, IFOP Differential IF Outputs.
20 VCMI No Connect. This pin can be grounded.
EPAD (EP) Exposed Pad. The exposed pad must be soldered to ground.
Data Sheet ADL5369
Rev. A | Page 7 of 23
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE CHARACTERISTICS
RF Frequency
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 Ω, unless
otherwise noted.
0.070
0.075
0.080
0.085
0.090
0.095
0.100
300 400 500 600 700 800 900 1000 1100
SUPPLY CURRENT (A)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-003
Figure 3. Supply Current vs. RF Frequency
0
2
4
6
8
10
12
14
300 400 500 600 700 800 900 1000 1100
CONVERSION LOSS (dB)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-004
Figure 4. Power Conversion Loss vs. RF Frequency
10
15
20
25
30
35
40
300 400 500 600 700 800 900 1000 1100
INPUT IP3 (dBm)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-005
Figure 5. Input IP3 vs. RF Frequency
20
30
40
50
60
70
80
90
300 400 500 600 700 800 900 1000 1100
INPUT IP2 (dBm)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-006
Figure 6. Input IP2 vs. RF Frequency
0
2
4
6
8
10
12
14
16
300 400 500 600 700 800 900 1000 1100
SSB NOISE FIGURE (dB)
RF FREQUENCY (MHz)
13361-007
–40°C
+25°C
+85°C
Figure 7. SSB Noise Figure vs. RF Frequency
ADL5369 Data Sheet
Rev. A | Page 8 of 23
Temperature
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 Ω, unless
otherwise noted.
0.065
0.070
0.075
0.080
0.085
0.090
0.095
0.100
–40–200 20406080
SUPPLY CURRENT (A)
TEMPERATURE (°C)
4.75V
5V
5.25V
13361-008
Figure 8. Supply Current vs. Temperature
4.0
4.5
5.0
5.5
6.0
6.5
8.0
7.0
–40 –20 0 20 40 60 80
CONVERSION LOSS (dB)
TEMPERATURE (°C)
13361-009
4.75V
5V
5.25V
Figure 9. Power Conversion Loss vs. Temperature
13361-010
24
25
26
27
28
29
30
31
32
33
34
–40 –20 0 20 40 60 80
IPNUT IP3 (dBm)
TEMPERATURE (°C)
4.75V
5V
5.25V
Figure 10. Input IP3 vs. Temperature
45
47
49
51
53
55
57
59
INPUT IP2 (dBm)
13361-011
–45 –25 –5 15 35 55 75
TEMPERATURE (°C)
4.75V
5V
5.25V
Figure 11. Input IP2 vs. Temperature
4
5
6
7
8
9
10
–40 –20 0 20 40 60 80
SSB NOISE FIGURE (dB)
TEMPERATURE (°C)
4.75V
5V
5.25V
13361-012
Figure 12. SSB Noise Figure vs. Temperature
Data Sheet ADL5369
Rev. A | Page 9 of 23
IF Frequency
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 Ω, unless
otherwise noted.
0.070
0.075
0.080
0.085
0.090
0.095
0.100
30 80 130 180 230 280 330 380 430
SUPPLY CURRENT (A)
IF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-013
Figure 13. Supply Current vs. IF Frequency
0
2
4
6
8
10
12
CONVERSION LOSS (dB)
13361-014
30 80 130 180 230 280 330 380 430
IF FREQUENCY (MHz)
–40°C
+25°C
+85°C
Figure 14. Power Conversion Loss vs. IF Frequency
21.0
21.5
22.0
22.5
23.0
23.5
24.0
24.5
25.0
25.5
26.0
30 80 130 180 230 280 330 380 430
INPUT IP3 (dBm)
IF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-015
Figure 15. Input IP3 vs. IF Frequency
35
40
45
50
55
60
65
30 80 130 180 230 280 330 380 430
INPUT IP2 (dBm)
IF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-016
Figure 16. Input IP2 vs. IF Frequency
0
2
4
6
8
10
12
14
30 80 130 180 230 280 330 380 430
SSB NOISE FIGURE (dB)
IF FREQUENCY (MHz)
13361-017
Figure 17. SSB Noise Figure vs. IF Frequency
ADL5369 Data Sheet
Rev. A | Page 10 of 23
LO Power and Spurious Performance
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 Ω, unless
otherwise noted.
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
–6–4–20246810
CONVERSION LOSS (dB)
LO POWER (dBm)
–40°C
+25°C
+85°C
13361-018
Figure 18. Power Conversion Loss vs. LO Power
25
26
27
28
29
30
31
32
33
34
35
–6 –4 –2 0 2 4 6 8 10
INPUT IP3 (dBm)
LO POWER (dBm)
–40°C
+25°C
+85°C
13361-019
Figure 19. Input IP3 vs. LO Power
50
51
52
53
54
55
56
57
58
59
60
–6 –4 –2 0 2 4 6 8 10
INPUT IP2 (dBm)
LO POWER (dBm)
–40°C
+25°C
+85°C
13361-020
Figure 20. Input IP2 vs. LO Power
–100
–90
–80
–70
–60
–50
–40
–30
–
20
300 400 500 600 700 800 900 1000 1100
IF/2 SPURIOUS (dBc)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-021
Figure 21. IF/2 Spurious vs. RF Frequency
–90
–80
–70
–60
–50
–40
–30
–
20
300 400 500 600 700 800 900 1000 1100
IF/3 SPURIOUS (dBc)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-022
Figure 22. IF/3 Spurious vs. RF Frequency
Data Sheet ADL5369
Rev. A | Page 11 of 23
Conversion Loss Distribution, Input IP3 Distribution, and Return Loss
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 Ω, unless
otherwise noted.
13361-024
100
80
60
40
20
0
PERCENTAGE (%)
CONVERSION LOSS (dB)
5.86.06.26.46.6
Figure 23. Conversion Loss Distribution
13361-023
100
80
60
40
20
0
PERCENTAGE (%)
INPUT IP3 (dBm)
24 25 26 27 28 29 30 31 32
Figure 24. Input IP3 Distribution
30025020015010050
40
35
30
25
20
15
10
22
20
18
16
14
12
10
IF FREQUENCY (MHz)
RESISTANCE ()
CAPACITANCE (pF)
R11 LO1
R11 LO2
C11 (pF )LO1
C11 (pF) LO2
13361-026
Figure 25. IF Port Return Loss
–25
–20
–15
–10
–5
0
300 400 500 600 700 800 900 1000 1100
RF RETURN LOSS (dB)
RF FREQUENCY (MHz)
13361-027
Figure 26. RF Port Return Loss, Fixed IF vs. Frequency
–35
–30
–25
–20
–15
–10
–5
0
300 400 500 600 700 800 900 1000 1100 1200
LO RETURN LOSS (dB)
LO FREQUENCY (MHz)
SELECTED
UNSELECTED
13361-028
Figure 27. LO Return Loss vs. LO Frequency, Selected and Unselected
ADL5369 Data Sheet
Rev. A | Page 12 of 23
Isolation, Leakage, Power Conversion Loss, Input IP3, and SSB Noise Figure
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 Ω, unless
otherwise noted.
40
45
50
55
60
65
70
300 400 500 600 700 800 900 1000 1100
LO SWITCH ISOL
A
TION (dB)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-029
Figure 28. LO Switch Isolation vs. RF Frequency
–70
–65
–60
–55
–50
–45
–40
–35
–
30
300 400 500 600 700 800 900 1000 1100
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
RF TO IF ISOL
A
TION (dBc)
13361-030
Figure 29. RF to IF Isolation vs. RF Frequency
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
393 493 593 693 793 893 993 1093 1193
LO FREQUENCY (MHz)
–40°C
+25°C
+85°C
LO TO IF LEAKAGE (dBm)
13361-031
Figure 30. LO to IF Leakage vs. LO Frequency
–45
–40
–35
–30
–25
–20
393 493 593 693 793 893 993 1093 1193
LO FREQUENCY (MHz)
LO TO RF LEAKAGE (dBm)
13361-032
Figure 31. LO to RF Leakage vs. LO Frequency
–55
–50
–45
–40
–35
–30
–25
–
20
393 493 593 693 793 893 993 1093 1193
2 LO LEAKAGE (dBm)
LO FREQUENCY (MHz)
2LO TO RF
2LO TO IF
13361-033
Figure 32. 2LO Leakage vs. LO Frequency
–60
–55
–50
–45
–40
–35
–30
–25
–
20
393 493 593 693 793 893 993 1093 1193
3LO LEAKAGE (dBm)
LO FREQUENCY (MHz)
3LO TO RF
3LO TO IF
13361-034
Figure 33. 3LO Leakage vs. LO Frequency
Data Sheet ADL5369
Rev. A | Page 13 of 23
5
7
9
11
13
15
17
0
1
2
3
4
5
6
7
8
9
10
300 400 500 600 700 800 900 1000 1100
SSB NOISE FIGURE (dB)
CONVERSION LOSS (dB)
RF FREQUENCY (MHz)
CONVERSION LOSS
NOISE FIGURE
V
GS
= 0, 0
V
GS
= 0, 1
V
GS
= 1, 0
V
GS
= 1, 1
13361-035
Figure 34. Power Conversion Loss and SSB Noise Figure vs. RF Frequency
0
5
10
15
20
25
30
35
300 400 500 600 700 800 900 1000 1100
INPUT IP3 (dBm)
RF FREQUENCY (MHz)
V
GS
= 0, 0
V
GS
= 0, 1
V
GS
= 1, 0
V
GS
= 1, 1
13361-036
Figure 35. Input IP3 vs. RF Frequency
0
5
10
15
20
25
30
35
40
–30 –25 –20 –15 –10 –5 05
NOISE FIGURE (dB)
BLOCKER POWER (dBm)
13361-037
Figure 36. SSB Noise Figure vs.10 MHz Offset Blocker Level
ADL5369 Data Sheet
Rev. A | Page 14 of 23
3.3 V PERFORMANCE CHARACTERISTICS
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
0.03
0.04
0.05
0.06
0.07
0.08
300 400 500 600 700 800 900 1000 1100
SUPPLY CURRENT (A)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-038
Figure 37. Supply Current vs. RF Frequency
0
2
4
6
8
10
12
14
300 400 500 600 700 800 900 1000 1100
CONVERSION LOSS (dB)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-039
Figure 38. Power Conversion Loss vs. RF Frequency
10
15
20
25
30
35
300 400 500 600 700 800 900 1000
INPUT IP3 (dBm)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-040
Figure 39. Input IP3 vs. RF Frequency
10
20
30
40
50
60
70
80
300 400 500 600 700 800 900 1000 1100
INPUT IP2 (dBm)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-041
Figure 40. Input IP2 vs. RF Frequency
13361-042
0
2
4
6
8
10
12
14
16
18
300 400 500 600 700 800 900 1000 1100
SSB NOISE FIGURE (dB)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
Figure 41. SSB Noise Figure vs. RF Frequency
Data Sheet ADL5369
Rev. A | Page 15 of 23
UPCONVERSION CHARACTERISTICS
TA = 25°C, fIF = 93 MHz, fLO = 543 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k, and ZO = 50 Ω, unless
otherwise noted.
0
2
4
6
8
10
12
14
16
300 400 500 600 700 800 900 1000 1100
CONVERSION LOSS (dB)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-043
Figure 42. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion
0
5
10
15
20
25
30
35
300 400 500 600 700 800 900 1000 1100
INPUT IP3 (dBm)
RF FREQUENCY (MHz)
–40°C
+25°C
+85°C
13361-044
Figure 43. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion
ADL5369 Data Sheet
Rev. A | Page 16 of 23
SPURIOUS PERFORMANCE
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 k,
and ZO = 50 Ω, unless otherwise noted.
M
0 1 2 3 4 5 6 7 8 9 10 11 12
N
0 −16.885 −33.42 −42.57 −38.358 −49.375 −61.446 −49.819 −51.873 −60.951 −52.666 −60.115 −61.09
1 −41.537 0 −45.535 −17.948 −54.779 −32.507 −47.242 −42.403 −45.589 −45.324 −67.094 −47.641 −61.494
2 −71.919 −50.753 −58.999 −60.289 −72.545 −70.273 −58.881 −73.383 −65.824 −78.819 −68.754 −97.834 −72.556
3 −95.982 −72.895 −79.147 −64.17 −90.573 −70.476 −92.162 −81.353 −87.574 −89.786 −82.829 −93.849 −86.249
4 <−100 −78.49 −93.128 −81.092 −99.503 −87.794 <−100 −99.13 −98.082 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 −95.9 −90.504 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
Data Sheet ADL5369
Rev. A | Page 17 of 23
CIRCUIT DESCRIPTION
The ADL5369 consists of two primary components: the RF
subsystem and the LO subsystem. The combination of design,
process, and packaging technology allows the functions of these
subsystems to be integrated into a single die, using mature
packaging and interconnection technologies to provide a high
performance, low cost design with excellent electrical,
mechanical, and thermal properties. In addition, the need for
external components is minimized, optimizing cost and size.
The RF subsystem consists of an integrated, low loss RF balun,
passive metal-oxide semiconductor field-effect transistor
(MOSFET) mixer, sum termination network, and IF amplifier.
The LO subsystem consists of a single pole, double throw (SPDT)-
terminated FET switch and a three-stage limiting LO amplifier.
The purpose of the LO subsystem is to provide a large, fixed
amplitude, balanced signal to drive the mixer independent of
the level of the LO input.
A block diagram of the device is shown in Figure 44.
2
3
1
20 19 18 17 16
6 7 8 9 10
4
5
14
13
15
12
BIAS
GENERATOR
VPMX
RFIN
RFCT
COMM
COMM
LOI2
VPSW
VGS1
VGS0
LOI1
CMI IFOP IFON PWDN COMM
VLO3 LGM3 VLO2 LOSW NIC
ADL5369
NIC = NOT INTERNALLY CONNECTED.
11
13361-047
Figure 44. Simplified Schematic
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB), unbalanced to balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, using a blocking capacitor is recommended to
avoid running excessive dc current through the device. The RF
balun can easily support an RF input frequency range of 300 MHz
to 1100 MHz.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the IF
output. This termination is accomplished by the addition of a
sum network between the IF output and the mixer.
Additionally, dc current can be saved by reducing the dc supply
voltage to as low as 3.3 V, further reducing the dissipated power
of the device. Note that no performance enhancement is obtained
by reducing the value of the resistors; reducing the value of the
resistors may result in excessive dc power dissipation.
LO SUBSYSTEM
The LO amplifier provides a large signal level to the mixer to
obtain optimum intermodulation performance. The resulting
amplifier provides extremely high performance centered on an
operating frequency of 700 MHz. The best operation is achieved
with high-side LO injection for RF signals in the 300 MHz to
1100 MHz range. Operation outside these ranges is permissible,
and conversion loss is extremely wideband, easily spanning 300
MHz to 1100 MHz, but intermodulation is optimal over the
aforementioned ranges.
The ADL5369 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
ADL5369 Data Sheet
Rev. A | Page 18 of 23
The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the LO
amplifier by raising the value of the external bias control resistor.
For dc current critical applications, the LO chain can operate
with a supply voltage as low as 3.3 V, resulting in substantial dc
power savings.
In addition, when operating with supply voltages below 3.6 V,
the ADL5369 has a power-down mode that permits the dc
current to drop to <200 µA.
All of the logic inputs work with any logic family that provides a
Logic 0 input level of less than 0.4 V and a Logic 1 input level that
exceeds 1.4 V. All logic inputs are high impedance up to Logic 1
levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry
permits operation up to 5.5 V, although a small bias current
is drawn.
Data Sheet ADL5369
Rev. A | Page 19 of 23
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5369 mixer is designed to upconvert or downconvert
between radio frequencies (RF) from 300 MHz to 1100 MHz and
intermediate frequencies (IF) from 30 MHz to 450 MHz. Figure 45
depicts the basic connections of the mixer. It is recommended
to ac-couple the RF and LO input ports to prevent non-zero dc
voltages from damaging the RF balun or LO input circuit. The
RFIN capacitor value of 8 pF is recommended to provide the
optimized RF input return loss for the desired frequency band.
For upconversion, drive the IF inputs, Pin 18 (IFON) and Pin 19
(IFOP), differentially or use a 1:1 ratio transformer for single-
ended operation. An 8 pF capacitor is recommended for the RF
output, Pin 2 (RFIN).
IF PORT
The real part of the output impedance is approximately 50 Ω,
as seen in Figure 25, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion loss that is approximately the same as the power
conversion loss, as shown in Table 3.
MIXER VGS CONTROL DAC
The ADL5369 features two logic control pins, Pin 12 (VGS0)
and Pin 13 (VGS1), that allow programmability for internal
gate to source voltages for optimizing mixer performance over
desired frequency bands. The evaluation board defaults both
VGS0 and VGS1 to ground. Power conversion loss, NF, and
IIP3 can be optimized, as shown in Figure 34 and Figure 35.
2
3
1
19 18 17 16
6 7 8 9 10
14
15
12
11
BIAS
GENERATOR
LO2_IN
RFIN +5V
+5V
+5V
+5V
LO1_IN
10k
R1
0
910
C24
560pF
10k
10pF10pF
10pF
100pF
10pF
0.01µF
4.7µF
R
BIAS LO
100pF
10pF
100pF
ADL5369
20
13
5
4
T1
IF1_OUT
C25
560pF
13361-048
Figure 45. Typical Application Circuit
ADL5369 Data Sheet
Rev. A | Page 20 of 23
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 46. The evaluation board is fabricated using Rogers®
RO3003 material.
Table 8 describes the various configuration options of the
evaluation board. Evaluation board layout is shown in Figure 47 to
Figure 50.
C22
1nF
C20
10pF
C2
10µF
C21
10pF
C1
100pF
C10
100pF
C12
100pF
VGS1
LO2_IN
LO1_IN
RFIN
R22
10k
VPOS
PWR_UP
R23
15k
VPOS
VPOS
VPOS
LOSEL
VGS0
C5
0.01µF
C4
10pF
C6
10pF
C8
10pF
R9
1.7kR4
10k
R21
10k
R14
910L3
0
VPMX
RFIN
RFCT
COMM
COMM
VGS1
VPSW
LOI2
VGS0
LOI1
IFON
IFOP
VCMI
PWDN
COMM
VLO3
LGM3
VLO2
NIC
LOSW
ADL5369
R1
0
C24
560pF
T1
IF1_OUT
C25
560pF
13361-049
NIC = NOT INTERNALLY CONNECTED.
Figure 46. Evaluation Board Schematic
Data Sheet ADL5369
Rev. A | Page 21 of 23
Table 8. Evaluation Board Configuration
Components Description Default Conditions
C2, C6, C8,
C20, C21
Power supply decoupling. Nominal supply decoupling consists of
a 10 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
C2 = 10 μF (Size 0603),
C6, C8, C20, C21 = 10 pF (Size 0402)
C1, C4, C5 RF input interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.
C1 = 100 pF (Size 0402), C4 = 10 pF (Size 0402),
C5 = 0.01 μF (Size 0402)
T1, R1, C24, C25 IF output interface. T1 is a 1:1 impedance transformer used to provide
a single-ended IF output interface. Remove R1 for balanced output
operation. C24 and C25 are used to block the dc bias at the IF ports.
T1 = TC1-1-13M+ (Mini-Circuits),
R1 = 0 Ω (Size 0402),
C24, C25 = 560 pF (Size 0402)
C10, C12, R4 LO interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input
for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is
enabled when the LOSEL test point is logic low. LO2_IN is enabled
when LOSEL is pulled to logic high.
C10, C12 = 100 pF (Size 0402),
R4 = 10 kΩ (Size 0402)
R21 PWDN interface. R21 pulls the PWDN logic low and enables the device.
The PWR_UP test point allows the PWDN interface to be exercised
using the an external logic generator. Grounding the PWDN pin for
nominal operation is allowed. Using the PWDN pin when supply
voltages exceed 3.3 V is not allowed.
R21 = 10 kΩ (Size 0402)
C22, L3, R9, R14,
R22, R23, VGS0,
VGS1
Bias control. R22 and R23 form a voltage divider to provide 3 V for
logic control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins. It is
recommended to pull these two pins to ground for nominal operation.
R9 sets the bias point for the internal LO buffers.
C22 = 1 nF (Size 0402), L3 = 0 Ω (Size 0603),
R9 = 1.7 kΩ (Size 0402), R14 = 910 Ω (Size 0402),
R22 = 10 kΩ (Size 0402), R23 = 15 kΩ (Size 0402),
VGS0 = VGS1 = 3-pin shunt
ADL5369 Data Sheet
Rev. A | Page 22 of 23
13361-050
Figure 47. Evaluation Board Top Layer
13361-051
Figure 48. Evaluation Board Ground Plane, Internal Layer 1
13361-052
Figure 49. Evaluation Board Power Plane, Internal Layer 2
13361-053
Figure 50. Evaluation Board Bottom Layer
Data Sheet ADL5369
Rev. A | Page 23 of 23
OUTLINE DIMENSIONS
COMPLIANT
TO
JEDEC STANDARDS MO-220-WHHC.
111908-A
0.65
BSC
0.70
0.60
0.40
0.35
0.28
0.23
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
15
16
5
Figure 51. 20-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-20-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option
Ordering
Quantity
ADL5369ACPZ-R7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel CP-20-9 1,500
ADL5369-EVALZ Evaluation Board 1
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13361-0-5/16(A)