ZL50211/GBC - Zarlink Semiconductor, Inc.

SEMICMF.019 1

Features

• ZL50211 has eight Echo Voice Processors in a

single BGA package. This single device provides

256 channels of 64 msec echo cancellation or 128

channels at 128 msec echo cancellation

• Each Echo Voice Processor has the capability of

cancelling echo over 32 channels

• Each Echo Voice Processor (EVP) shares the

address bus and data bus with each other

• Fully compliant to ITU-T G.165, G.168 (2000) and

(2002) specifications

• Passed all AT&T voice quality tests for carrier

grade echo canceller

• The ZL50211 provides more than 58% board space

savings when compared with the eight Echo Voice

Processors packaged devices

• Each EVP has a Patented Advanced Non-Linear

Processor with high quality subjective performance

• Each EVP has protection against narrow band

signal divergence and instability in high echo

environments

• Each EVP can be programmed independently in

any mode e.g. Back-to-Back or Extended Delay to

provide capability of cancelling different echo tails.

• Each EVP has 0 to -12 dB level adjusters at all

signal ports (Rin, Sin, Sout and Rout)

• Each EVP has the same JTAG identification code

Applications

• Voice over IP network gateways

• Voice over ATM, Frame Relay

• T1/E1/J1 multichannel echo cancellation

• Wireless base stations

• Echo Canceller pools

• DCME, satellite and multiplexer system

Description

The ZL50211 Voice Echo Canceller implements a

cost effective solution for telephony voice-band echo

cancellation conforming to ITU-T G.168

requirements. The ZL50211 architecture contains 128

groups of two echo cancellers (ECA and ECB) which

can be configured to provide two channels of 64

milliseconds or one channel of 128 milliseconds echo

cancellation. This provides 256 channels of 64

milliseconds to 128 channels of 128 milliseconds

echo cancellation or any combination of the two

configurations. The ZL50211 supports ITU-T G.165

and G.164 tone disable requirements.

DS5030 ISSUE 1 July 2002

Ordering Information

ZL50211GB 535 - Ball BGA

-40°C to +85°C

ZL50211

256 Channel Voice Echo Canceller

Data Sheet

Figure 1 - ZL50211 Device Overview

EVP1

Rin1...Rin8

Sin1....Sin8

1..CS8

D0....D7

A0..A12

RESET1..RESET8

R/W

MLCK

C4i

Foi

ODE

Fsel

Rout1..Rout8

Sout1..Sout8

IRQ

1..

IRQ

DTA

1..

DTA

EVP4

EVP6 EVP7 EVP8

EVP5

EVP3EVP2

ZL5011GB

ZL50211 Data Sheet

2SEMICMF.019

Figure 2 - Single Echo Voice Processor (EVP) Overview

Features of Echo Voice Processor (EVP)

• Each EVP can cancel echo tails of 64ms (32 channels) to 128ms (16 channels) with the ability to mix

channels at 128ms or 64ms in any combination

• Independent Power Down mode for each group of 2 channels for power management

• Fully compliant to ITU-T G.165, G.168 (2000) and (2002) specifications

• Passed all AT&T voice quality tests for carrier grade echo canceller

• Compatible to ST-BUS and GCI interface at 2Mb/s serial PCM

• PCM coding, µ/A-Law ITU-T G.711 or sign magnitude

• Per channel Fax/Modem G.164 2100Hz or G.165 2100Hz phase reversal Tone Disable

• Per channel echo canceller parameters control

• Transparent data transfer and mute

• Fast reconvergence on echo path changes

• Fully programmable convergence speeds

• Patented Advanced Non-Linear Processor with high quality subjective performance

• Protection against narrow band signal divergence and instability in high echo environments

• 0 dB to -12 dB level adjusters (3 dB steps) at all signal ports

• Offset nulling of all PCM channels

• 10 MHz or 20 MHz master clock operation

• 3.3 V pads and 1.8V Logic core operation with 5-Volt tolerant inputs

• IEEE-1149.1 (JTAG) Test Access Port

RESET

Rout

IC0

Sout

DS CS R/W A12-A0 DTA D7-D0

Echo Canceller Pool

DD1 (3.3V)

TDI TDO TCK TRSTTMS

Rin

IRQ

C4i

F0i

MCLK

ODE

Sin

Fsel

Test PortMicroprocessor Interface

Timing

Unit

Serial

Parallel

Serial

PLL

Group 0

ECA/ECB

Group 4

ECA/ECB

Group 8

ECA/ECB

Group 12

ECA/ECB

Group 1

ECA/ECB

Group 5

ECA/ECB

Group 9

ECA/ECB

Group 13

ECA/ECB

Group 2

ECA/ECB

Group 6

ECA/ECB

Group 10

ECA/ECB

Group 14

ECA/ECB

Group 3

ECA/ECB

Group 7

ECA/ECB

Group 11

ECA/ECB

Group 15

ECA/ECB

Note:

Refer to Figure 4

for EVP block

diagram

DD2 (1.8V)

Data Sheet ZL50211

SEMICMF.017

Figure 3 - 535 Ball BGA Ball Grid Array

12 345 67 891011121314 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ZL50211GB

BGA BALL GRID ARRAY

ZL50211 Data Sheet

4SEMICMF.019

Pin Description

Signal

Name

Signal

Type BGA Ball # Signal

Description

VDD1 = 3.3V

(VDD_IO)

Power

AC5,AC26,AC27,AD26,AD5,AE5,AF12,AF13,AF1

4,AF17,AF18,AF19,AF24,AF6,AF7,AF8,AG24,AH

24,E13,E14,E17,E18,E19,E23,E24,E25,E6,E7,E8,

F5,G26,G27,G5,H26,H5,M26,M5,N26,N5,P26,P27

, P4,P5,U26,U27,U4,U5,V26,V5,W26,W5

Positive Power

Supply. Nominally

3.3 volt (I/O

voltage).

VDD2 = 1.8V

(VDD_Core)

Power

AA26,AA28,AA3,AA5,AB26,AB28,AB3,AB5,AF11,

AF20,AG10,AG21,AG22,AH10,AH11,AH22,AJ15,

AJ16,AJ9,AK9,C10,C11,C22,C23,C9,D10,D23,D9,

E11,E20,E21,E22,J26,J27,J4,J5,K26,K27,K3,K5,

L26,L27,L3,L5,Y26, Y27,Y3,Y5

Positive Power

Supply. Nominally

1.8 volt (Core

voltage).

VSS Power

A29,A30,AF5,AG15,AG16,AG26,AG27,AG4,AH15

AH16,AH21,AH28,AH3,AJ2,AJ21,AJ29,AK1,AK30,

B1,B15,B16,B2,B29,C15,C16,C28,C3,D15,D16,

D27,D4,E26,E5,N13,N14,N15,N16,N17,N18,P13,

P14,P15,P16,P17,P18,R13,R14,R15,R16,R17,

R18,R2,R27,R28,R29,R3,R4,T13,T14,T15,T16,

T17,T18,T2,T27,T28,T29,T3,T4,U13,U14,U15,

U16,U17,U18,V13,V14,V15,V16, V17,V18

Ground

TEST PINS

TE1, TE2,

TE3, TE4,

TE5, TE6,

TE7, TE8

Test Mo de

Pins

M4,AK26,M3,AJ4,AK4,AK25,K30,N28 Internal

Connection.

Connected to VSS

for normal

operation.

OUTPUT

TEST PINS

Test

pins

D8,P28,C12,AK10,AH12,AD29,H28,J29,AC28,

D12,P29,E9,AJ11,AK11,AD30,G28,H29,AB27,A3,

P2,A2,Y1,AA1,AJ17,C20,B21,AK17,B3,P1,D3,

AA2,AB1,AK18,B22,D21,AJ18,C2,R1,E3,AB2,

AB4,AH18,D19,A22,AK19,D2,T1,E4,AC1,AC2,

AG18,A21,B20,AJ19,C1,U1,F4,AC4,AD1,AK20,

C19,A20,AH19,F3,U2,E2,AC3,AD2,AK21,B19,

A19,AG19,E10,P30,B12,AJ12,AG13,AC29,J30,

G29,AC30,A11,N30,D11,AH13,AK12,AB29,H30,

G30,AB30,A10,N27,B11,AJ13,AG14,AA27,F29,

F30,AA29,A9,A14,B10,AG11,AG12,Y28,E29,E28,

AA30,A8,A13,B9,AJ10,AF10,Y29,D29,E30,Y30,

C8,B14,B8,AG9,AH9,W28,D26,D28,W29,C4,

E12,C5,AA4,Y4,R30,A23,B23,

T30,B4,P3,A4,Y2,W1,AG17,D20,C21,AH17

No connection.

These pins must be

left open for normal

operation.

INPUT TEST

PINS

SC_EN, SC_FCLK,

SC_IN, SC_M_MCLK,

SC_RESET,

SC_SET, SC_T_MCLK,

A27,D5,A25,A26,A24,B24,A28 Internal

Connection.

Connected to VSS

for normal

operation.

Data Sheet ZL50211

SEMICMF.017

THalt

and TStep

Halt

Step

C14, D14 Internal

Connection.

Connected to VSS

for normal

operation.

USER SIGNAL PINS

Signal Name Signal

Type BGA Ball # Signal Description

D0, D1, D2, D3, D4, D5,

D6, D7

User

Signals

AK7,AJ8,AK8,

AJ27,AK29,AJ28,

AH27, AJ30

Data Bus D0 to D7 (Bidirectional). These pins form

the 8-bit bidirectional data bus of the microprocessor

port. They are connected to all the EVP’s.

A0,A1,A2,A3,A4,A5,

A6,A7, A8, A9,

A10,A11,A12

User

Signals

AG28,AH29,

AH30,AG29,AF28,

AG30,AE28,AF29,

AE29,AF30,AD27,

AE30,AD28

Address A0 to A12 (Input). These inputs provide the

A12 - A0 address lines to the internal registers. They

are connected to all the EVP’s.

CS1,CS2,CS3,

CS4, CS5, CS6,

CS7, CS8

User

Signals

R5,L28,T5,AF15,

AF16,E16,T26,

R26

Chip Select (Input). These active low inputs are used

enable the microprocessor interface of each EVP.

RESET1 RESET2,

RESET3, RESET4,

RESET5, RESET6,

RESET7, RESET8

User

Signals

M2,AH23,M1,AH5,

AJ5,AJ23,N29,M30

EVP Reset (Schmitt Trigger Input). An active low

resets the device and puts the Voice Processor into a

low-power stand-by mode. When the RESET pin is

returned to logic high and a clock is applied to the

MCLK pin, the EVP will automatically execute

initialization routines, which preset all the Control

and Status Registers to their default power-up

values. Each reset pin controls a single processor. A

user can connect all of them together if required.

Rin1,Rin2,Rin3,

Rin4,Rin5,Rin6,

Rin7,Rin8

User

Signals

C6,V27,B5,AG5,

AH6,U28,B27,B28

Receive PCM Signal Inputs (Input). Port 1 TDM data

input streams. Each Rin pin receives serial TDM data

streams at 2.048 Mb/s with 32 channels per stream.

Sin1,Sin2,Sin3,Sin4,

Sin5,Sin6,Sin7,Sin8

User

Signals

C7,U30,B6,AG7,

AG6,U29,B30,C27

Send PCM Signal Inputs (Input). Port 2 TDM data

input streams. Each Sin pin receives serial TDM data

streams at 2.048 Mb/s with 32 channels per stream.

Rout1,Rout2,Rout3,

Rout4,Rout5,Rout6,

Rout7,Rout8,

User

Signals

A5,V30,A6,AH7,

AG8,V28,C26,C30

Receive PCM Signal Outputs (Output). Port 2 TDM

data output streams. Each Rout pin outputs serial

TDM data streams at 2.048 Mb/s with 32 channels per

stream.

Sout1,Sout2,Sout3,

Sout4,Sout5,Sout6,

Sout7,Sout8

User

Signals

B7,W27,A7,AH8,

AF9,W30,C29,D30

Send PCM Signal Outputs (Output). Port 1 TDM

data output streams. Each Sout pin outputs serial TDM

data streams at 2.048 Mb/s with 32 channels per

stream.

User

Signal

K29 Data Strobe (Input). This active low input works in

conjunction with CS to enable the read and write

operations. This signal is connected to all processors.

R/W

User

Signal

M29 Read/Write (Input). This input controls the direction of

the data bus lines (D7-D0) during a microprocessor

access. This signal is connected to all processors.

Pin Description (continued)

ZL50211 Data Sheet

6SEMICMF.019

DTA1, DTA2, DTA3,

DTA4, DTA5, DTA6,

DTA7, DTA8

User

Signals

N2,AK28,N1,AK6,

AJ7,AK27,M28,

M27

Data Transfer Acknowledgment (Open Drain

Output). These active low outputs indicate that a data

bus transfer is completed. A pull-up resistor (1K

typical) is required at these outputs.

ODE

User

Signal

V29 Output Drive Enable (Input). This input pin is

logically AND’d with the ODE bit-6 of the Main Control

high, the Rout and Sout ST-BUS outputs are enabled.

When the ODE bit is low or the ODE input pin is low,

the Rout and Sout ST-BUS outputs are high

impedance. This signal is connected to all processors.

F0i

User

Signal

B26 Frame Pulse (Input). This input accepts and

automatically identifies frame synchronization signals

formatted according to ST-BUS or GCI interface

specifications.This signal is connected to all

processors.

C4i

User

Signal

B25 Serial Clock (Input). 4.096 MHz serial clock for

shifting data in/out on the serial streams (Rin, Sin,

Rout, Sout).This signal is connected to all processors.

Fsel

User

Signal

A15 Frequency select (Input). This input selects the Mas-

ter Clock frequency operation. When Fsel pin is low,

nominal 20MHz Master Clock input must be applied.

When Fsel pin is high, nominal 10MHz Master Clock

input must be applied.This signal is connected to all

processors.

MCLK

User

Signal

A16 Master Clock (Input). Nominal 10MHz or 20MHz

Master Clock input. May be connected to an

asynchronous (relative to frame signal) clock

source.This signal is connected to all processors.

IRQ1, IRQ2, IRQ3,

IRQ4, IRQ5, IRQ6,

IRQ7, IRQ8

User

Signals

N4,AJ26,N3,AK5,

AJ6,AG23,L30,L29

Interrupt Request (Open Drain Output). These

outputs go low when an interrupt occurs in any

channel. Each IRQ returns high when all the interrupts

have been read from the Interrupt FIFO Register of

respective EVP. A pull-up resistor (1K typical) is

required at these outputs.

Extra Device Pins

- W3,E15,V4,AK16,

AK15,AK14,D13,

C13,V3,A12,B13,

AK13,AH14,U3,V2,

AJ14

No connection. The ball pins must be left open for

normal operation.

JTAG SIGNAL PINS

TMS JTAG

Signal

K2 Test Mode Select (3.3V Input). JTAG signal that

controls the state transitions of the TAP controller. This

pin is pulled high by an internal pull-up when not

driven. This signal is connected to all processors.

TCK

JTAG

Signal

D6 Test Clock (3.3V Input). Provides the clock to the

JTAG test logic.This signal is connected to all

processors.

Data Sheet ZL50211

SEMICMF.017

The following description applies to a single EVP (Echo Voice Processor). Note that the ZL50211 contains eight

EVP’s.

1.0 Single Echo Voice Processor (EVP) Description

Each single Echo Voice Processor (EVP) contains 32 echo cancellers divided into 16 groups. Each group has two

echo cancellers, Echo Canceller A (ECA) and Echo Canceller B (ECB). Each group can be configured in Normal,

Extended Delay or Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two

channels of 64ms echo cancellation, which run independently on different channels. In Extended Delay

configuration, a group of echo cancellers achieves 128ms of echo cancellation by cascading the two echo

cancellers (A & B). In Back-to-Back configuration, the two echo cancellers from the same group are positioned to

cancel echo coming from both directions in a single channel, providing full-duplex 64ms echo cancellation.

TRST

JTAG

Signal

D7 Test Reset (3.3V Input). Asynchronously initializes

the JTAG TAP controller by putting it in the

Test-Logic-Reset state. This pin should be pulsed low

on power-up or held low, to ensure that all the EVP’s

are in the normal functional mode. This pin is pulled by

an internal pull-down when not driven. This signal is

connected to all EVP’s.

TDI1,TDI2,TDI3,TDI4,

TDI5,TDI6,TDI7,TDI8

JTAG

Signals

K1,AK23,L2,AK2,

AJ3,AH20,F27,H27

Test Serial Data In (3.3V Input). JTAG serial test

instructions and data are shifted in on these pins.

These pins are pulled high by an internal pull-up when

not driven.

TDO1,TDO2,TDO3,

TDO4,TDO5,TDO6

TDO7,TDO8

JTAG

Signals

L1,AJ22,L4,AH4,

AK3,AK24,J28,K28

Test Serial Data Out (Output). JTAG serial data is

outputted on these pins on the falling edge of TCK.

These pins are held in high impedance state when

JTAG scan is not enabled.

PLL SIGNAL PINS

PLLVDD2 = 1.8V PLL

Power

H3,V1,H4,AE3,

AG2,AE26,D22,

C24, AE27

PLL Power Supply. Must be connected to PLLVDD2 =

1.8V.

PLLVSS1

PLLVSS2

PLL

Power

J3,W2,H2,AF4,

AF3,AF27,D24,

C25,AF26,H1,W4,

J2, AH1,AG3,AF22,

D25,E27,AF21

PLL Ground. Must be connected to VSS.

T1M1, T1M2, T1M3,

T1M4, T1M5, T1M6,

T1M7, T1M8

PLL Test

Signals

D1,AH26,E1,AE1,

AD4,AK22,D18,

C18

Internal Connection. Connected to VSS for normal

operation.

T2M1, T2M2, T2M3,

T2M4, T2M5, T2M6,

T2M7, T2M8

PLL Test

Signals

F2,AG25,G3,AF1,

AD3,AF25,B18,A18

Internal Connection. Connected to VSS for normal

operation.

SG1, SG2, SG3, SG4,

SG5, SG6, SG7, SG8

PLL Test

Signals

G4,AJ25,F1,AE2,

AG1,

AH25,B17,C17

Internal Connection. Connected to VSS for normal

operation.

DT1, DT2, DT3, DT4,

DT5, DT6, DT7, DT8

PLL Test

Signals

G2,AF23,G1,AF2,

AE4,AJ24,D17,

A17

No connection. These pins must be left open for

normal operation.

AT1, AT2, AT3, AT4,

AT5, AT6, AT7, AT8

PLL Test

Signals

K4,AJ20,J1,

AH2,AJ1,AG20,

F28,F26

No connection. These pins must be left open for

normal operation.

ZL50211 Data Sheet

8SEMICMF.019

Each Echo Voice Processor contains the following main elements (see Figure 4).

• Adaptive Filter for estimating the echo channel

• Subtractor for cancelling the echo

• Double-Talk detector for disabling the filter adaptation during periods of double-talk

• Path Change detector for fast reconvergence on major echo path changes

• Instability Detector to combat instability in very low ERL environments

• Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection

• Disable Tone Detectors for detecting valid disable tones at send and receive path inputs

• Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals

• Offset Null filters for removing the DC component in PCM channels

• 0 to -12dB level adjusters at all signal ports

• Parallel controller interface compatible with Motorola microcontrollers

• PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding

• Each echo canceller in the EVP has four functional states: Mute, Bypass, Disable Adaptation and Enable

Adaptation. These are explained in the section entitled Echo Canceller Functional States.

Figure 4 - Functional Block Diagram of an Echo Canceller

1.1 Adaptive Filter

The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then

subtracted from Sin. For each group of echo cancellers, the Adaptive Filter is a 1024 tap FIR adaptive filter which is

divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal

configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay

configuration, both sections are cascaded to provide 128ms of echo estimation in channel A. In Back-to-Back

configuration, the first section is used in the receive direction and the second section is used in the transmit

direction for the same channel.

Non-Linear

Processor

Offset

Null

Linear/

/A-Law

Microprocessor

Interface

Double - Talk

Detector

Control

Narrow-Band

Detector

/A-Law/

Linear

Offset

Null

Echo Canceller (N), where 0 < N < 31

Sout

Rin

Sin

Rout

Programmable Bypass

(channel N)

ST-BUS

PORT2 PORT1

MuteR

MuteS

0 to -12dB

Level Adjust

Linear/

/A-Law

0 to -12dB

Level Adjust

0 to -12dB

Level Adjust

/A-Law/

Linear

0 to -12dB

Level Adjust

Adaptive

Filter

Disable Tone

Detector

Disable Tone

Detector

Path Change

Instability

Detector

Data Sheet ZL50211

SEMICMF.017

1.2 Double-Talk Detector

Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.

When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter

coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller

continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the

relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition:

Lsin > Lrin + 20log10(DTDT)

where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0.

A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo

return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence

speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is

reduced by a factor of 2Slow relative to normal convergence for non-zero values of Slow. If Slow equals zero,

adaptation is halted completely.

In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk

Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the

DTDT is set internally to 0.5625 (-5 dB).

In some applications the return loss can be higher or lower than 6 dB. The EVP allows the user to change the

detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value

into the DTDT register.

The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:

DTDT(hex) = hex(DTDT(dec) * 32768)

where 0 < DTDT(dec) < 1

Example: For DTDT = 0.5625 (-5 dB), the hexadecimal value becomes hex(0.5625 * 32768) = 4800hex

1.3 Path Change Detector

Integrated into the EVP is a Path Change Detector. This permits fast reconvergence when a major change occurs

in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is

achieved, but at a much slower speed.

The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path

clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,

the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon

detection of a major path change.

ZL50211 Data Sheet

10 SEMICMF.019

1.4 Non-Linear Processor (NLP)

After echo cancellation, there is always a small amount of residual echo which may still be audible. The EVP uses

Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the Adaptive

Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal

as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be

calculated by the following equation:

TSUP = Lrin + 20log10(NLPTHR)

where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed

in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the

following equation:

NLPTHR(hex) = hex(NLPTHR(dec) * 32768)

where 0 < NLPTHR(dec) < 1

When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal

by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a

spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the

perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.

The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.

The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted

that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.

The patented Advanced NLP provides a number of new and improved features over the original NLP found in

previous generation devices. The differences between the Advanced NLP and the original NLP are summarized in

Table 1.

The NLPSel bit in Control Register 3 selects which NLP is used. A “1” will select the Advanced NLP, “0” selects the

original NLP.

The Advanced NLP uses a new noise ramping scheme to quickly and more accurately estimate the background

noise level. The noise ramping method of the original NLP can also be used. The InjCtrl bit in Control Register 3

selects the ramping scheme.

The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the

Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original NLP), a higher

Feature Register or Bit(s)

Advanced

NLP Default

Value

Original NLP

Default Value

NLP Selection NLPSel (Control Register 3) 1 0 (feature

not supported)

Reject uncanceled echo as noise NLRun1 (Control Register 3) 1 0 (feature

not supported)

Reject double-talk as noise NLRun2 (Control Register 3) 1 0 (feature

not supported)

Noise level estimator ramping scheme InjCtrl (Control Register 3) 1 0 (feature

not supported)

Noise level ramping rate NLInc (Noise Control) 5(hex) C(hex)

Noise level scaling Noise Scaling 16(hex) 74(hex)

Table 1 - Comparison of NLP Types

Data Sheet ZL50211

SEMICMF.017

value will give faster ramping. NLInc is a 4-bit value, so only values from 0 to F(hex) are valid.

The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will

scale the injected noise level down, conversely, raising the value will scale the comfort noise up. Due to differences

in the noise estimator operation, the Advanced NLP requires a different scaling value than the original NLP.

Important Note: NLInc and the Noise Scaling register have been pre-programmed with G.168 compliant values.

Changing these values may result in undesirable comfort noise performance!

The Advanced NLP also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for

background noise. These features were not present in the original NLP. They can be disabled by setting the NLRun1

and NLRun2 bits in Control Register 3 to “0”.

1.5 Disable Tone Detector

The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21Hz) sine

wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every

450 ms (±25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the

Tone Detector will trigger.

The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between

0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone

Detector will trigger.

Each EVP has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid

disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic

high and an interrupt is generated (i.e. IRQ pin low). Refer to Figure 5 and to the Interrupts section.

Figure 5 - Disable Tone Detection

Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to

maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. TD bit low) if the

signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the

frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is

generated (i.e. IRQ pin low).

The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per

channel basis. When the PHDis bit is set to “1”, G.164 tone disable requirements are selected.

In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the

Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors

internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by

setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the

interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a

given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state.

TD bit

Rin

Sin

Echo Canceller A

Tone Detector

Status reg

ECA

TD bit

Rin

Sin

Echo Canceller B

Tone Detector

Status reg

ECB

ZL50211 Data Sheet

12 SEMICMF.019

1.6 Instability Detector

In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause stability

problems in the Adaptive Filter. This instability can result in variable pitched ringing or oscillation. Should this ringing

occur, the Instability Detector will activate and suppress the oscillations.

The Instability Detector is activated by setting the RingClr bit in Control Register 3 to “1”.

1.7 Narrow Band Signal Detector (NBSD)

Single or dual frequency tones (i.e. DTMF tones) present in the receive input (Rin) of the echo canceller for a

prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is

designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow

band signals are detected, adaptation is halted but the echo canceller continues to cancel echo.

The NBSD will be active regardless of the EVP functional state. However the NBSD can be disabled by setting the

NBDis bit to “1” in Control Register 2.

1.8 Offset Null Filter

Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC

component, each EVP incorporates Offset Null filters in both Rin and Sin inputs.

The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.

1.9 Adjustable Level Pads

Each EVP provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be adjusted

both inside and outside the echo path. Each signal level may be independently scaled with anywhere from 0 to -12

dB level, in 3 dB steps. Level values are set using the Gains register.

CAUTION: Gain adjustment can help interface the ZL50211 to a particular system in order to provide optimum echo

cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels

and slow convergence. Exercise great care when adjusting these values.

The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of

attenuation at Rin, and override the values in the Gains register.

1.10 ITU-T G.168 Compliance

The ZL50211 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes

(i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.

The ZL50211 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL50211

was classified as “carrier grade” echo canceller.

Data Sheet ZL50211

SEMICMF.017

2.0 EVP Configuration

The EVP architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers

which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB). They can be set in three

distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8.

2.1 Normal Configuration

In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in

Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously.

Figure 6 - Normal Device Configuration (64ms)

2.2 Back-to-Back Configuration

In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming

from both directions in a single channel providing full-duplex 64ms echo cancellation. See Figure 7. This

configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB

contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo

cancellation is required.

Figure 7 - Back-to-Back Device Configuration (64ms)

Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo Canceller

A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 16 groups of 2 cancellers that can

be configured into Back-to-Back.

Rin

Rout

Sout

Sin

echo

path A

echo

path B

channel A

channel B

ECA

ECB

Adaptive

Filter (64ms)

Adaptive

Filter (64ms)

PORT1PORT2

ECA

Sin Sout

Rout Rin

ECB

echo echo

path path

Adaptive

Filter (64ms)

Adaptive

Filter (64ms)

PORT1PORT2

ZL50211 Data Sheet

14 SEMICMF.019

Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a

transmission device or between two codecs for echo control on analog trunks.

2.3 Extended Delay Configuration

In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds

echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and the second

timeslot normally associated with ECB contains quiet code.

Figure 8 - Extended Delay Configuration (128ms)

Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.

For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control

Table 4 shows the 16 groups of 2 cancellers that can each be configured into 64ms or 128ms echo tail capacity.

3.0 Echo Canceller Functional States

Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.

3.1 Mute

In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which

is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with quiet

code.

In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes

quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,

causes quiet code to be transmitted on Sout.

In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be

“0”. Refer to Figure 4 and to Control Register 2 for bit description.

LINEAR

16 bits

2’s

complement

SIGN/

MAGNITUDE

µ-Law

A-Law

CCITT (G.711)

µ-Law A-Law

+Zero

(quiet code)

0000hex 80hex FFhex D5hex

Table 2 - Quiet PCM Code Assignment

channel A

ECA

Sin Sout

Rout Rin

echo

path A Adaptive Filter

(128 ms)

PORT1PORT2

Data Sheet ZL50211

SEMICMF.017

3.2 Bypass

The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is

selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame

(125 µs) in order to properly clear the filter.

3.3 Disable Adaptation

When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The

adaptation process is halted, however, the echo canceller continues to cancel echo.

3.4 Enable Adaptation

In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller

to model the echo return path characteristics in order to cancel echo. This is the normal operating state.

The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:

MuteS, MuteR, Bypass and AdaptDis. Refer to the EVP Registers Description for details.

4.0 Echo Voice Processor (EVP) Throughput Delay

The throughput delay of the EVP varies according to the device configuration. For all device configurations, Rin to

Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and

Sin to Sout paths have a delay of two frames.

5.0 Serial PCM I/O channels

There are four TDM I/O streams, each with channels numbered from 0 to 31. One input stream is for Receive (Rin)

channels, and the other input stream is for Send (Sin) channels. Likewise, two output streams is for Rout PCM

channels, and Sout PCM channels. See Figure 9 for channel allocation.

5.1 Serial Data Interface Timing

The ZL50211 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.

The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s.

The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The EVP automatically detects the presence

of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of

the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way

into the bit cell (See Figure 11). In GCI format, every second rising edge of the C4i clock marks the bit boundary,

and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 12).

ZL50211 Data Sheet

16 SEMICMF.019

Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams

Base

Address + Echo Canceller A Base

Address + Echo Canceller B

Byte

-00

hex Control Reg 1 - 20hex Control Reg 1

-01

hex Control Reg 2 - 21hex Control Reg 2

-02

hex Status Reg - 22hex Status Reg

-03

hex Reserved - 23hex Reserved

-04

hex Flat Delay Reg - 24hex Flat Delay Reg

-05

hex Reserved - 25hex Reserved

-06

hex Decay Step Size Reg - 26hex Decay Step Size Reg

-07

hex Decay Step Number - 27hex Decay Step Number

-08

hex Control Reg 3 - 28hex Control Reg 3

-09

hex Control Reg 4 - 29hex Control Reg 4

-0A

hex Noise Scaling - 2Ahex Noise Scaling

-0B

hex Noise Control - 2Bhex Noise Control

0Dhex 0Chex Rin Peak Detect Reg 2Dhex 2Chex Rin Peak Detect Reg

0Fhex 0Ehex Sin Peak Detect Reg 2Fhex 2Ehex Sin Peak Detect Reg

11hex 10hex Error Peak Detect Reg 31hex 30hex Error Peak Detect Reg

13hex 12hex Reserved 33hex 32hex Reserved

15hex 14hex DTDT Reg 35hex 34hex DTDT Reg

17hex 16hex Reserved 37hex 36hex Reserved

19hex 18hex NLPTHR 39hex 38hex NLPTHR

1Bhex 1Ahex Step Size, MU 3Bhex 3Ahex Step Size, MU

1Dhex 1Chex Gains 3Dhex 3Chex Gains

1Fhex 1Ehex Reserved 3Fhex 3Ehex Reserved

Table 3 - Memory Mapping of Per Channel Control and Status Registers

F0i

Rin/Sin

Rout/Sout Channel 31Channel 0

125 µsec

Channel 1 Channel 30

ST-BUS

F0i

GCI interface

Note: Refer to Figure 11 and Figure 12 for timing details.

Data Sheet ZL50211

SEMICMF.017

6.0 Memory Mapped Control and Status registers

Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual

ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo

canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of

Echo Canceller B from group 2. It occupies the internal address space from 0A0hex to 0BFhex and interfaces to PCM

channel #5 on all serial PCM I/O streams.

As illustrated in Table 3, the “per channel” registers provide independent control and status bits for each echo

canceller. Figure 10 shows the memory map of the control/status register blocks for all echo cancellers of the EVP.

When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control

section.

Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended

Delay or Back-to-Back.

6.1 Normal Configuration

For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,

channels 2 and 3 are active.

6.2 Extended Delay Configuration

For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel

carries quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B

(Channel 5) will carry quiet code.

6.3 Back-to-Back Configuration

For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel

carries quiet code. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B

(Channel 11) will carry quiet code.

Group Channels Group Channels

00, 1816, 17

12, 3918, 19

24, 51020, 21

36, 71122, 23

48, 91224, 25

5 10, 11 13 26, 27

6 12, 13 14 28, 29

7 14, 15 15 30, 31

Table 4 - Group and Channel allocation

ZL50211 Data Sheet

18 SEMICMF.019

Figure 10 - Memory Mapping

6.4 Power Up Sequence

On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put each EVP in power

down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16

Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.

When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µs for the PLL to

lock. C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 16 groups

of echo cancellers individually, by writing a “1” into the PWUP bit in each group of echo canceller’s Main Control

For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute

their initialization routine. The initialization routine sets their registers, Base Address+00hex to Base Address+3Fhex,

to the default power-up value and clears the Adaptive Filter coefficients. Two frames are necessary for the

initialization routine to execute properly.

Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00hex

to Base Address+3Fhex, for the specific application.

6.5 Power Management

Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their

respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are

bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section

for description.

The typical power consumption can be calculated with the following equation:

PC = 9 * Nb_of_groups + 3.6, in mW

where 0 ≤ Nb_of_groups ≤ 16.

0000h -->

Channel 0, ECA Ctrl/Stat Registers 001Fh

0020h -->

Channel 1, ECB Ctrl/Stat Registers 003Fh

0040h -->

Channel 2, ECA Ctrl/Stat Registers 005Fh

0060h -->

Channel 3, ECB Ctrl/Stat Registers 007Fh

03C0h -->

Channel 30, ECA Ctrl/Stat Registers 03DFh

03E0h -->

Channel 31, ECB Ctrl/Stat Registers 03FFh

0400h --> 040Fh

Main Control Registers <15:0>

Group 0

Echo

Cancellers

Registers

Groups 2 --> 14

Echo Cancellers

Registers

Group 1

Echo

Cancellers

Registers

Group 15

Echo

Cancellers

Registers

0410h

Interrupt FIFO Register

0411h

Test Register

0412h ---> FFFFh

Reserved Test Register

Data Sheet ZL50211

SEMICMF.017

6.6 Call Initialization

To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting

the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.

Since the Narrow Band Detector is “ON” regardless of the functional state of the Echo Canceller it is recommended

that the Echo Cancellers are reset before any call progress tones are applied.

6.7 Interrupts

The EVP provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable

is detected and released.

Although each EVP may be configured to react automatically to tone disable status on any input PCM voice

channels, the user may want for the external HOST processor to respond to Tone Disable information in an

appropriate application-specific manner.

Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt when

a Tone Disable releases.

Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory

containing the channel number of the echo canceller that has generated the interrupt.

All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this

FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will

toggle low for each pending interrupt.

After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status

of Status register). The TD bit indicates the presence of a Tone Disable.

The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the EVP. To provide more flexibility, the MTDBI

(bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or unmasked

from generating an interrupt on a per channel basis. Refer to the Registers Description section.

7.0 JTAG Support

The EVP JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a

design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is

controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.

7.1 Test Access Port (TAP)

The TAP provides access to many test functions of the EVP. It consists of four input pins and one output pin. The

following pins are found on the TAP.

• Test Clock Input (TCK)

The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus

remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells

concurrent with the operation of the device and without interfering with the on-chip logic.

ZL50211 Data Sheet

20 SEMICMF.019

• Test Mode Select Input (TMS)

The logic signals received at the TMS input are interpreted by the TAP Controller to control the test

operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to

VDD1 when it is not driven from an external source.

• Test Data Input (TDI)

Serial input data applied to this port is fed either into the instruction register or into a test data register,

depending on the sequence previously applied to the TMS input. Both registers are described in a

subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is

internally pulled to VDD1 when it is not driven from an external source.

• Test Data Output (TDO)

Depending on the sequence previously applied to the TMS input, the contents of either the instruction

falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is

set to a high impedance state.

• Test Reset (TRST)

This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS.

7.2 Instruction Register

In accordance with the IEEE 1149.1 standard, the EVP uses public instructions. The JTAG Interface contains a 3-bit

instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller

is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test

data register that will operate while the instruction is current, and to define the serial test data register path, which

is used to shift data between TDI and TDO during data register scanning.

7.3 Test Data Registers

As specified in IEEE 1149.1, each of the Echo Voice Processor’s JTAG Interface contains three test data registers:

• Boundary-Scan register

The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path

around the boundary of each EVP core logic.

• Bypass Register

The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.

• Device Identification register

The Device Identification register provides access to the following encoded information:

device version number, part number and manufacturer's name.

Data Sheet ZL50211

SEMICMF.017

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing

† Characteristics are over recommended operating conditions unless otherwise stated

‡ Typical figures are at 25°C, VDD1 =3.3V and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

1 I/O Supply Voltage (VDD1)V

DD_IO -0.5 5.0 V

2 Core Supply Voltage (VDD2)V

DD_CORE -0.5 2.5 V

3 Input Voltage VI3 VSS - 0.5 VDD1+0.5 V

4 Input Voltage on any 5V Tolerant I/O pins VI5 VSS - 0.3 7.0 V

5 Continuous Current at digital outputs Io20 mA

6 Package power dissipation PD3.0 W

7 Storage temperature TS-55 150 °C

Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated

Characteristics Sym Min Typ‡Max Units

1 Operating Temperature TOP -40 +85 °C

2 I/O Supply Voltage (VDD_IO)V

DD1 3.0 3.3 3.6 V

3 Core Supply Voltage (VDD_CORE)V

DD2 1.6 1.8 2.0 V

4 Input High Voltage on 3.3V tolerant I/O VIH3 0.7VDD1 VDD1 V

5 Input High Voltage on 5V tolerant I/O pins VIH5 0.7VDD1 5.5 V

6 Input Low Voltage VIL 0.3VDD1 V

DC Electrical Characteristics† - Voltages are with respect to ground (Vss) unless otherwise stated.

Characteristics Sym Min Typ‡Max Units Test Conditions

Static Supply Current ICC 250 µA RESET = 0

IDD_IO (VDD1 = 3.3V)

Single EV Processor

IDD_IO 10 mA 32 channels of single

EVP are active

IDD_CORE (VDD2 = 1.8V)

Single EV Processor

IDD_CORE 65 mA 32 channels of single

EVP are active

2 Power Consumption PC1.2 W All EVP’s i.e. 256 chan-

nels are active

3 Input High Voltage VIH 0.7VDD1 V

4 Input Low Voltage VIL 0.3VDD1 V

5 Input Leakage

Input Leakage on Pullup

Input Leakage on Pulldown

IIH/IIL

ILU

ILD

-100

100

µA

VIN=VSS to VDD1or 5.5V

VIN=VSS

VIN=VDD1

6 Input Pin Capacitance CI10 pF

Output High Voltage VOH 0.8VDD1 VI

OH = 12 mA

8 Output Low Voltage VOL 0.4 V IOL = 12 mA

9 High Impedance Leakage IOZ 10 µAV

IN=VSS to 5.5V

10 Output Pin Capacitance CO10 pF

ZL50211 Data Sheet

22 SEMICMF.019

† Characteristics are over recommended operating conditions unless otherwise stated

‡ Typical figures are at 25°C, VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing

† Characteristics are over recommended operating conditions unless otherwise stated

‡ Typical figures are at 25°C, VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing

† Characteristics are over recommended operating conditions unless otherwise stated

‡ Typical figures are at 25°C, VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing

AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels

- Voltages are with respect to ground (Vss) unless otherwise stated.

Characteristics Sym Level Units Conditions

1CMOS Threshold V

TT 0.5VDD1 V

2 CMOS Rise/Fall Threshold Voltage High VHM 0.7VDD1 V

3 CMOS Rise/Fall Threshold Voltage Low VLM 0.3VDD1 V

AC Electrical Characteristics† - Frame Pulse and C4i

Characteristic Sym Min Typ‡Max Units Notes

1 Frame pulse width (ST-BUS, GCI) tFPW 20 2*

tCP-20

2 Frame Pulse Setup time before

C4i falling (ST-BUS or GCI)

tFPS 10 122 150 ns

3Frame Pulse Hold Time from C4i

falling (ST-BUS or GCI)

tFPH 10 122 150 ns

4C4i Period tCP 190 244 300 ns

5C4i Pulse Width High tCH 85 150 ns

6C4i Pulse Width Low tCL 85 150 ns

7C4i Rise/Fall Time tr, tf10 ns

AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes

Characteristic Sym Min Typ‡Max Units Test Conditions

1 Rin/Sin Set-up Time tSIS 10 ns

2 Rin/Sin Hold Time tSIH 10 ns

3 Rout/Sout Delay

- Active to Active

tSOD 60 ns

4 Output Data Enable (ODE)

Delay

tODE 30 ns

AC Electrical Characteristics† - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated.

Characteristic Sym Min Typ‡Max Units Notes

1 Master Clock Frequency,

- Fsel = 0

- Fsel = 1

fMCF0

fMCF1

19.0

9.5

20.0

10.0

21.0

10.5

MHz

2 Master Clock Low tMCL 20 ns

3 Master Clock High tMCH 20 ns

Data Sheet ZL50211

SEMICMF.017

† Characteristics are over recommended operating conditions unless otherwise stated

‡ Typical figures are at 25°C, VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing

Figure 11 - ST-BUS Timing at 2.048 Mb/s

AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode

Characteristics Sym Min Typ‡Max Units Test Conditions

1CS setup from DS falling tCSS 0ns

2R/W setup from DS falling tRWS 0ns

3 Address setup from DS falling tADS 0ns

4CS hold after DS rising tCSH 0ns

5R/W hold after DS rising tRWH 0ns

6 Address hold after DS rising tADH 0ns

7 Data delay on read tDDR 79 ns

8 Data hold on read tDHR 315ns

9 Data setup on write tDSW 0ns

10 Data hold on write tDHW 0ns

11 Acknowledgment delay tAKD 80 ns

12 Acknowledgment hold time tAKH 08ns

13 IRQ delay tIRD 20 65 ns

VTT

F0i

C4i

tFPW

Rout/Sout

Rin/Sin

tFPH

tSOD

tSIH

tCH tCL

Bit 0, Channel 31

tFPS tCP

tSIS

VTT

Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0

Bit 0, Channel 31 Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0

VHM

VLM

ZL50211 Data Sheet

24 SEMICMF.019

Figure 12 - GCI Interface Timing at 2.048 Mb/s

Figure 13 - Output Driver Enable (ODE)

Figure 14 - Master Clock

VTT

F0i

C4i

tFPW

Sout/Rout

Sin/Rin

tFPH

tSOD

tSIH

tCH tCL

Bit 7, Channel 31

tFPS tCP

tSIS

VTT

Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0

Bit 7, Channel 31 Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0

VHM

VLM

VTTHiZ

HiZ

Sout/Rout

ODE

tODE

Valid Data

VTT

tMCH

tMCL

VTT

MCLK

Data Sheet ZL50211

SEMICMF.017

Figure 15 - Motorola Non-Multiplexed Bus Timing

A0-A12

D0-D7

READ

WRITE

tCSS tCSH

tADH

tDHR

tRWS

R/W

tADS

tRWH

tDHW

tAKD

tDSW

tDDR

tAKH

DTA

VTT

VALID ADDRESS

VALID READ DATA

VALID WRITE DATA

tIRD

IRQ VTT

ZL50211 Data Sheet

26 SEMICMF.019

8.0 EVP Registers Description

Echo Canceller A (ECA): Control Register 1

Power-up 00hex R/W Address: 00hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset INJDis BBM PAD Bypass AdpDis 0 ExtDI

Functional Description of Register Bits

Reset When high, the power-up initialization is executed. This presets all register bits including

this bit and clears the Adaptive Filter coefficients.

INJDis When high, the noise injection process is disabled. When low noise injection is enabled.

BBM When high, the Back to Back configuration is enabled. When low, the Normal

configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at

the same time. Always set both BBM bits of the two echo cancellers (Control Register 1)

of the same group to the same logic value to avoid conflict.

PAD When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains

Bypass When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The

Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low,

output data on both Sout and Rout is a function of the echo canceller algorithm.

AdpDis When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.

When low, the echo canceller dynamically adapts to the echo path characteristics.

0 Bits marked as “1” or “0” are reserved bits and should be written as indicated.

ExtDl When high, Echo Cancellers A and B of the same group are internally cascaded into one

128ms echo canceller. When low, Echo Cancellers A and B of the same group operate

independently.

Echo Canceller B (ECB): Control Register 1

Power-up 02hex R/W Address: 20hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset INJDis BBM PAD Bypass AdpDis 1 0

Functional Description of Register Bits

Reset When high, the power-up initialization is executed which presets all register bits including

this bit and clears the Adaptive Filter coefficients.

INJDis When high, the noise injection process is disabled. When low, noise injection is enabled.