TECHNICAL DATA
19
Dual D Flip-Flop
High-Voltage Silicon-Gate CMOS
The IW4013B consists of two identical, independent data-type flip-
flops. Each flip-flop has independent data, set, reset, and clock inputs
and Q and Q outputs. These devices can be used for shift register
applications, and, by connecting Q output to the data input, for counter
and toggle applications. The logic level present at the D input is
transferred to the Q output during the positive-going transition of the
clock pulse. Setting or resetting is independent of the clock and is
accomplished by a high level on the set or reset line, respectively.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
IW4013B
ORDERING INFORMATION
IW4013BN Plastic
IW4013BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =VCC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Clock Data Reset Set Q Q
L LLL H
HLLHL
XLLQQ
XXHLLH
XXLHHL
X X HHH H
X = don’t care
IW4013B
20
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±10 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
PDPower Dissipation per Output Transistor 100 mW
Tstg Storage T emperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
Thi s device contains p rote ction c ircuitr y to guard a gainst damage due to hi gh static voltage s or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
IW4013B
21
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V ≥-55°C25
°C≤125
°CUnit
VIH Minimum High-Level
Input Voltage VOUT=0.5 V or VCC - 0.5 V
VOUT=1.0 V or VCC - 1.0 V
VOUT=1.5 V or VCC - 1.5 V
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
VIL Maximum Low -Level
Input Voltage VOUT=0.5 V or VCC - 0.5 V
VOUT=1.0 V or VCC - 1.0 V
VOUT=1.5 V or VCC - 1.5 V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
VOH Minimum High-Level
Output Voltage VIN=GND or VCC 5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
VOL Maximum Low-Level
Output Voltage VIN=GND or VCC 5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
IIN Max imu m Inp ut
Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
ICC Max imu m Qu iescent
Supply Current
(per Package)
VIN= GND or VCC 5.0
10
15
20
1
2
4
20
1
2
4
20
30
60
120
600
µA
IOL Minimu m Ou tput Low
(Sink) Current VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
mA
IOH Minimu m Ou tput
High (Source) Current VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2.0
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
IW4013B
22
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C25
°C≤125°CUnit
fmax Maximum Clock Freque ncy (Figure 1) 5.0
10
15
3.5
8
12
3.5
8
12
1.75
4
6
MHz
tPLH, tPHL Maximum Prop agation Delay, Clock to Q or Q
(Figure 1) 5.0
10
15
300
130
90
300
130
90
600
260
180
ns
tPLH Maximum Propagation Delay, Set to Q or Reset
to Q (Figure 2) 5.0
10
15
300
130
90
300
130
90
600
260
180
ns
tPHL Maximum Propagation Delay, Set to Q or Reset
to Q (Figure 2) 5.0
10
15
400
170
120
400
170
120
800
340
240
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figure 1) 5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN Maximum Input Capacitance - 7.5 pF
TIMING REQUIREMENTS(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C25
°C≤125°CUnit
twMinimum Pulse Width, Clo ck (Figure 1) 5.0
10
15
140
60
40
140
60
40
280
120
80
ns
twMinimum Pulse Width, Set or Reset (Figure 2) 5.0
10
15
180
80
50
180
80
50
360
160
100
ns
tsu Minimu m Setup Time, Da ta to Cl ock
(Figure 3) 5.0
10
15
40
20
15
40
20
15
80
40
30
ns
thMinimu m Hold Time, Cloc k t o Data
(Figure 3) 5.0
10
15
5
5
5
5
5
5
10
10
10
ns
tr, tfMaximum Input Rise or Fall Time, Cloc k
(Figure 1) 5.0
10
15
500
30
6
500
30
6
1000
60
12
µs
IW4013B
23
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/2 of the Device)