General Description
The MAX1110/MAX1111 are low-power, 8-bit, 8-chan-
nel analog-to-digital converters (ADCs) that feature an
internal track/hold, voltage reference, clock, and serial
interface. They operate from a single +2.7V to +5.5V
supply and consume only 85µA while sampling at rates
up to 50ksps. The MAX1110’s 8 analog inputs and the
MAX1111’s 4 analog inputs are software-configurable,
allowing unipolar/bipolar and single-ended/differential
operation.
Successive-approximation conversions are performed
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter-
mined by the 2.048V internal reference, or by an
externally applied reference ranging from 1V to VDD.
The 4-wire serial interface is compatible with the SPI™,
QSPI™, and MICROWIRE™ serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
The MAX1110/MAX1111 have a software-program-
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 6µA at 1ksps, and only 52µA at
10ksps. Power-down can also be controlled using the
SHDN input pin. Accessing the serial interface automat-
ically powers up the device.
The MAX1110 is available in 20-pin SSOP and DIP
packages. The MAX1111 is available in small 16-pin
QSOP and DIP packages.
________________________Applications
Portable Data Logging
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Solar-Powered Remote Systems
4mA to 20mA-Powered Remote
Data-Acquisition Systems
____________________________Features
o+2.7V to +5.5V Single Supply
oLow Power: 85µA at 50ksps
6µA at 1ksps
o8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1110)
o4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1111)
oInternal Track/Hold; 50kHz Sampling Rate
oInternal 2.048V Reference
oSPI/QSPI/MICROWIRE-Compatible Serial Interface
oSoftware-Configurable Unipolar or Bipolar Inputs
oTotal Unadjusted Error: ±1 LSB max
±0.3 LSB typ
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
________________________________________________________________
Maxim Integrated Products
1
INPUT
SHIFT
REGISTER CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.048V
REFERENCE
T/H
ANALOG
INPUT
MUX
8-BIT
SAR ADC
IN
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7*
CH6*
CH5*
CH4*
COM
REFOUT
*MAX1110 ONLY
REFIN
OUT
REF
CLOCK
MAX1110
MAX1111
CS
SHDN
________________Functional Diagram
19-1194; Rev 3; 2/10
EVALUATION KIT
AVAILABLE
Ordering Information
Ordering Information continued at end of data sheet.
*
Dice are specified at TA= +25°C, DC parameters only.
Pin Configurations appear at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PART TEMP RANGE PIN-PACKAGE
MAX1110CPP 0°C to +70°C 20 Plastic DIP
MAX1110CAP 0°C to +70°C 20 SSOP
MAX1110C/D 0°C to +70°C Dice*
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND..............................................................-0.3V to 6V
AGND to DGND .......................................................-0.3V to 0.3V
CH0–CH7, COM, REFIN,
REFOUT to AGND ......................................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND ...............................................-0.3V to 6V
Digital Outputs to DGND............................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
16 Plastic DIP (derate 10.53mW/°C above +70°C) ......842mW
16 QSOP (derate 8.30mW/°C above +70°C)................667mW
16 CERDIP (derate 10.00mW/°C above +70°C) ..........800mW
20 Plastic DIP (derate 11.11mW/°C above +70°C) ......889mW
20 SSOP (derate 8.00mW/°C above +70°C) ................640mW
20 CERDIP (derate 11.11mW/°C above +70°C) ..........889mW
Operating Temperature Ranges
MAX1110C_P/MAX1111C_E................................0°C to +70°C
MAX1110E_P/MAX1111E_E .............................-40°C to +85°C
MAX1110MJP/MAX1111MJE..........................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+240°C
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA= TMIN to TMAX; unless otherwise noted.)
-3dB rolloff MHz1.5Small-Signal Bandwidth
kHz800
VCH_ = 2.048Vp-p, 25kHz (Note 4)
External reference, 2.048V
VDD = 2.7V to 3.6V
VDD = 2.7V to 3.6V
No missing codes over temperature
±0.35 ±1
CONDITIONS
Full-Power Bandwidth
±1Internal or external reference LSBGain Error (Note 3)
dB-75Channel-to-Channel Crosstalk
dB68SFDRSpurious-Free Dynamic Range
dB-70THD
Total Harmonic Distortion
(up to the 5th harmonic)
±0.15 ±0.5
LSB±0.1
Channel-to-Channel
Offset Matching
ppm/°C±0.8Gain Temperature Coefficient
LSB±1DNLDifferential Nonlinearity
UNITSMIN TYP MAXSYMBOLPARAMETER
LSB±0.3 ±1TUETotal Unadjusted Error
Bits8Resolution
dB49SINAD
Signal-to-Noise
and Distortion Ratio
VDD = 5.5V (Note 2) LSB
±0.2
INLRelative Accuracy (Note 1)
VDD = 5.5V (Note 2) LSB
±0.5
Offset Error
DC ACCURACY
DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 2.048Vp-p, 50ksps, 500kHz external clock)
V
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA= TMIN to TMAX; unless otherwise noted.)
On/off-leakage current, VCH_ = 0V or VDD
Used for data transfer only
(Note 6)
External clock, 2MHz
CONDITIONS
ppm/°C±50
mA3.5REFOUT Short-Circuit Current
pF18Input Capacitance
µA±0.01 ±1Multiplexer Leakage Current
1
2
50 500
kHz400Internal Clock Frequency
0mA to 0.5mA output load mV2.5Load Regulation (Note 8)
ns10Aperture Delay
µs1tACQ
Track/Hold Acquisition Time
UNITSMIN TYP MAXSYMBOLPARAMETER
ps
V
1 VDD +
50mV
Input Voltage Range
(Note 9) µA120Input Current
<50Aperture Jitter
External clock, 500kHz, 10 clocks/conversion 20
Internal clock µs
25 55
tCONV
Conversion Time (Note 5)
Bipolar input, COM = VREFIN / 2
Unipolar input, COM = 0V
COM ±
VREFIN / 2
V
0V
REFIN
Input Voltage Range, Single-
Ended and Differential (Note 7)
V1.968 2.048 2.128REFOUT Voltage
External Clock-Frequency Range MHz
kHz
Capacitive Bypass at REFOUT µF
REFOUT Temperature Coefficient
V2.7 5.5VDD
Supply Voltage
85 250
IDD
Supply Current (Note 2)
VDD = 2.7V to 3.6V
Full-scale input
CLOAD = 10pF
VDD = 2.7V to 3.6V; external reference,
2.048V; full-scale input mV±0.4 ±4PSR
Power-Supply Rejection
(Note 10)
Operating mode
2
µA
Power-down 3.2 10
Software
SHDN at DGND
Operating mode 120 250
VDD = 5.5V
Full-scale input
CLOAD = 10pF
Reference disabled
Reference disabled
45
80
CONVERSION RATE
ANALOG INPUT
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REFIN
POWER REQUIREMENTS
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA= TMIN to TMAX; unless otherwise noted.)
CS = VDD (Note 6)
CS = VDD
ISOURCE = 0.5mA
ISINK = 5mA
SHDN = open
SHDN = 0V or VDD
(Note 6)
Digital inputs = 0V or VDD
SHDN = open
CONDITIONS
pF15COUT
Three-State Output Capacitance
µA±0.01 ±10IL
Three-State Leakage Current
VVDD - 0.5VOH
Output High Voltage
V
0.4
VOL
Output Low Voltage
nA±100
SHDN Maximum Allowed Leakage
for Mid-Input
VVDD / 2VFLT
SHDN Voltage, Floating
µA±4
SHDN Input Current
VVDD - 0.4VSH
SHDN Input High Voltage
V0.8VIL
DIN, SCLK, CS Input Low Voltage
V1.1 VDD - 1.1
ISINK = 16mA
VSM
0.8
pF15CIN
DIN, SCLK, CS Input Capacitance
µA±1IIN
DIN, SCLK, CS Input Leakage
SHDN Input Mid-Voltage
V0.2VHYST
DIN, SCLK, CS Input Hysteresis
UNITSMIN TYP MAXSYMBOLPARAMETER
V0.4VSL
SHDN Input Low Voltage
VDD ≤3.6V
VDD > 3.6V V
2
VIH
DIN, SCLK, CS Input High Voltage 3
DIGITAL INPUTS: DIN, SCLK, CS
DIGITAL OUTPUTS: DOUT, SSTRB
SHDN INPUT
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
ns100tCSS
Figure 1, external clock mode only,
CLOAD = 100pF ns
CS to SCLK Rise Setup
240
Figure 1, CLOAD = 100pF ns
20 200
ns0tCSH
CONDITIONS
CS to SCLK Rise Hold
240tDV
CS Fall to Output Enable
Figure 2, CLOAD = 100pF ns240tTR
CS Rise to Output Disable
tSDV
CS Fall to SSTRB Output Enable
(Note 6)
Figure 2, external clock mode only,
CLOAD = 100pF ns240tSTR
CS Rise to SSTRB Output
Disable (Note 6)
Figure 11, internal clock mode only ns0tSCK
SSTRB Rise to SCLK Rise
(Note 6)
ns200tCH
SCLK Pulse Width High
ns200tCL
SCLK Pulse Width Low
CLOAD = 100pF ns240tSSTRB
SCLK Fall to SSTRB
ns0tDH
DIN to SCLK Hold
µs1tACQ
Track/Hold Acquisition Time
ns100tDS
DIN to SCLK Setup
UNITSMIN TYP MAXSYMBOLPARAMETER
TIMING CHARACTERISTICS (Figures 8 and 9)
(VDD = +2.7V to +5.5V, TA= TMIN to TMAX, unless otherwise noted.)
Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2: See
Typical Operating Characteristics.
Note 3: VREFIN = 2.048V, offset nulled.
Note 4: On-channel grounded; sine wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for the analog inputs is from AGND to VDD.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: External reference at 2.048V, full-scale input, 500kHz external clock.
Note 10: Measured as |VFS (2.7V) - VFS (3.6V) |.
Note 11: 1µF at REFOUT; internal reference settling to 0.5 LSB.
ns
20 240
tDO
SCLK Fall to Output Data Valid Figure 1,
CLOAD = 100pF
MAX111_C/E
MAX111_M
External reference 20
Internal reference (Note 11)
µs
12
tWAKE
Wake-Up Time ms
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
6 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(VDD = +2.7V; fSCLK = 500kHz; external clock (50% duty cycle); RL= ∞; TA = +25°C, unless otherwise noted.)
400
100
2.5 6.0
SUPPLY CURRENT vs. SUPPLY VOLTAGE
150
350
MAX1110-01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
3.0 3.5 4.0 4.5 5.0 5.5
300
250
200
OUTPUT CODE = 10101010
CLOAD = 60pF
CLOAD = 30pF
160
60
-60 140
SUPPLY CURRENT vs. TEMPERATURE
80
140
MAX1110-02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
-20 20 60 100
120
100
OUTPUT CODE = FULL SCALE
CLOAD = 10pF
VDD = 5.5V
VDD = 3.6V
5.0
2.0
-60 140
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
2.5
4.5
MAX1110-03
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (µA)
-20 20 60 100
4.0
3.5
3.0
SHDN = DGND
0.8
0
2.5 6.0
OFFSET ERROR vs. SUPPLY VOLTAGE
0.1
0.7
0.6
MAX1110-04
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
3.0 3.5 4.0 4.5 5.0 5.5
0.5
0.4
0.3
0.2
0.5
0
2.5 6.0
INTEGRAL NONLINEARITY vs.
SUPPLY VOLTAGE
0.1
0.4
MAX1110-05
SUPPLY VOLTAGE (V)
INL (LSB)
3.0 3.5 4.0 4.5 5.0 5.5
0.3
0.2
0.3
-0.3
0256
DIFFERENTIAL NONLINEARITY
vs. CODE
-0.2
0.2
0.1
MAX1110-06
DIGITAL CODE
DNL (LSB)
64 128 192
0
-0.1
0.6
0
-60 140
OFFSET ERROR vs. TEMPERATURE
0.1
0.2
0.5
MAX1110-07
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-20 20 60 100
0.4
0.3
0.20
-0.20
0 256
INTEGRAL NONLINEARITY
vs. CODE
-0.10
-0.15
0.15
0.10
0.05
MAX1110-08
DIGITAL CODE
INL (LSB)
64 128 192
0
-0.05
20
-100
025
FFT PLOT
-80
-20
0
MAX1110-09
FREQUENCY (kHz)
AMPLITUDE (dB)
5101520
-60
-40
fCH_ = 10.034kHz, 2Vp-p
fSAMPLE = 50ksps
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
16 SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1110/
MAX1111 begin the A/D conversion and goes high when the conversion is done.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
20 VDD Positive Supply Voltage, +2.7V to +5.5V
18 CS Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
high, DOUT is high impedance. The voltage at CS may exceed VDD (up to 5.5V).
19 SCLK
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%). The voltage at
SCLK may exceed VDD (up to 5.5V).
17 DIN Serial-Data Input. Data is clocked in at SCLK’s rising edge. The voltage at DIN may
exceed VDD (up to 5.5V).
12 REFOUT Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND.
14 DGND Digital Ground
15 DOUT Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high.
13 AGND Analog Ground
10 SHDN
Three-Level Shutdown Input. Normally floats. Pulling SHDN low shuts the MAX1110/
MAX1111 down to 10µA (max) supply current; otherwise, the devices are fully opera-
tional. Pulling SHDN high shuts down the internal reference.
11 REFIN Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
5–8 CH4–CH7 Sampling Analog Inputs
1–4 CH0–CH3 Sampling Analog Inputs
+3V
3k
CLOAD
DGND
DOUT
CLOAD
DGND
3k
DOUT
a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
+3V
3k
CLOAD
DGND
DOUT
CLOAD
DGND
3k
DOUT
a) VOH to High-Z b) VOL to High-Z
Figure 2. Load Circuits for Disable Time
12
16
14
15
13
8
10
11
9
6
7
—
1–4
59 COM Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5 LSB.
PIN
MAX1111
NAME FUNCTION
MAX1110
_______________Detailed Description
The MAX1110/MAX1111 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 shows the Typical Operating Circuit.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in Figure 4, the equivalent input cir-
cuit. In single-ended mode, IN+ is internally switched to
the selected input channel, CH_, and IN- is switched to
COM. In differential mode, IN+ and IN- are selected
from the following pairs: CH0/CH1, CH2/CH3,
CH4/CH5, and CH6/CH7. Configure the MAX1110
channels with Table 1 and the MAX1111 channels with
Table 2.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5 LSB (±0.1 LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans two SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLD as a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLD from the positive input (IN+) to the negative
input (IN-). In single-ended mode, IN- is simply COM.
This unbalances node ZERO at the input of the com-
parator. The capacitive DAC adjusts during the remain-
der of the conversion cycle to restore node ZERO to 0V
within the limits of 8-bit resolution. This action is equiva-
lent to transferring a charge of 18pF x (VIN+ - VIN-) from
CHOLD to the binary-weighted capacitive DAC, which in
turn forms a digital representation of the analog input
signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the sixth bit of the 8-bit control byte has
been shifted in. It enters its hold mode on the falling
clock edge after the eighth bit of the control byte has
been shifted in. If the converter is set up for single-
ended inputs, IN- is connected to COM, and the con-
verter samples the “+” input; if it is set up for differential
inputs, IN- connects to the “-” input, and the difference
(IN+ - IN-) is sampled. At the end of the conversion, the
positive input connects back to IN+, and CHOLD
charges to the input signal.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
8 _______________________________________________________________________________________
VDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
SHDN
SSTRB
DOUT
DIN
SCLK
CS
COM
DGND
AGND
VDD
CH7
1µF
0.1µF1µF
CH0
ANALOG
INPUTS
MAX1110
MAX1111
CPU
+2.7V
REFIN
REFOUT
Figure 3. Typical Operating Circuit
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
CH7*
COM
CSWITCH
TRACK
T/H
SWITCH
CHOLD
HOLD
CAPACITIVE DAC
REFIN
ZERO
COMPARATOR
–+
18pF
6.5k
RIN
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*.
*MAX1110 ONLY
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
Table 1a. MAX1110 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
Table 1b. MAX1110 Channel Selection in Differential Mode (SGL/DIF = 0)
Table 2a. MAX1111 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
Table 2b. MAX1111 Channel Selection in Differential Mode (SGL/DIF = 0)
–+
111
–+
1
CH2
10
–+
0
CH3
11
–+
0
CH1
10
+ –
1
+
CH0
01
+ –
100
+ –
001
–
COMCH7CH6SEL2 CH5CH4
000
SEL0SEL1
+–
111
+–
0
CH2
11
– +
1
CH3
01
+–
0
–
CH1
01
–+
1
+
CH0
10
–+
010
+ –
100
CH7CH6SEL2 CH5CH4
000
SEL0SEL1
+
X11
+
X
CH1
10
+
CH0
+
X01
SEL2 CH3CH2
X00
SEL0SEL1
+–
X11
+–
X
–
CH1
01
+
CH0
–+
X10
SEL2 CH3CH2
X00
SEL0SEL1
–
–
–
–
COM
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
10 ______________________________________________________________________________________
Table 3. Control-Byte Format
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)
NAME
SGL/DIF
2
BIT
1= single ended, 0= differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage differ-
ence between two channels is measured. See Tables 1 and 2.
DESCRIPTION
UNI/BIP
3
START
1= unipolar, 0= bipolar. Selects unipolar or bipolar conversion mode. Select differential operation
if bipolar mode is used. See Table 4.
PD00 (LSB)
7 (MSB)
1= external clock mode, 0= internal clock mode.
Selects external or internal clock mode.
The first logic “1” bit after CS goes low defines the beginning of the control byte.
SEL2
SEL1
SEL0
6
5
4
Select which of the input channels are to be used for the conversion (Tables 1 and 2).
PD111 = fully operational, 0 = power-down.
Selects fully operational or power-down mode.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by:
tACQ = 6 x (RS+ RIN) x 18pF
where RIN = 6.5kΩ, RS= the source impedance of the
input signal, and tACQ is never less than 1µs. Note that
source impedances below 2.4kΩdo not significantly
affect the AC performance of the ADC.
Input Bandwidth
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Inputs
Internal protection diodes, which clamp the analog
input to VDD and AGND, allow the channel input pins to
swing from (AGND - 0.3V) to (VDD + 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDD by more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
The MAX1110/MAX1111 can be configured for differen-
tial or single-ended inputs with bits 2 and 3 of the con-
trol byte (Table 3). In single-ended mode, the analog
inputs are internally referenced to COM with a full-scale
input range from COM to VREFIN + COM. For bipolar
operation, set COM to VREFIN / 2.
In differential mode, choosing unipolar mode sets the
differential input range at 0V to VREFIN. In unipolar
mode, the output code is invalid (code zero) when a
negative differential input voltage is applied. Bipolar
mode sets the differential input range to ±VREFIN / 2.
Note that in this mode, the common-mode input range
includes both supply rails. Refer to Table 4 for input
voltage ranges.
Quick Look
To quickly evaluate the MAX1110/MAX1111’s analog
performance, use the circuit of Figure 5. The
MAX1110/MAX1111 require a control byte to be written
to DIN before each conversion. Tying DIN to +3V feeds
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
______________________________________________________________________________________ 11
in control bytes of $FF (hex), which trigger single-
ended, unipolar conversions on CH7 (MAX1110) or
CH3 (MAX1111) in external clock mode without power-
ing down between conversions. In external clock mode,
the SSTRB output pulses high for two clock periods
before the most significant bit of the 8-bit conversion
result is shifted out of DOUT. Varying the analog input
alters the output code. A total of 10 clock cycles is
required per conversion. All transitions of the SSTRB
and DOUT outputs occur on SCLK’s falling edge.
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a bit
from DIN into the MAX1110/MAX1111’s internal shift reg-
ister. After CS falls, the first arriving logic “1” bit at DIN
defines the MSB of the control byte. Until this first start bit
arrives, any number of logic “0” bits can be clocked into
DIN with no effect. Table 3 shows the control-byte format.
The MAX1110/MAX1111 are compatible with MICROWIRE,
SPI, and QSPI devices. For SPI, select the correct clock
polarity and sampling edge in the SPI control registers:
set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and
QSPI all transmit a byte and receive a byte at the same
time. Using the Typical Operating Circuit (Figure 3), the
simplest software interface requires three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
8-bit conversion result). Figure 6 shows the MAX1110/
MAX1111 common serial-interface connections.
1µF
0.1µF
VDD
DGND
AGND
CS
SCLK
DIN
DOUT
SSTRB
SHDN
+3V
N.C.
0.01µF
CH7 (CH3)
COM
REFOUT
REFIN
C1
1µF
0V TO
+2.048V
ANALOG
INPUT
OSCILLOSCOPE
CH1 CH2 CH3 CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FF (HEX)
( ) ARE FOR THE MAX1111.
MAX1110
MAX1111
+3V
500kHz
OSCILLATOR
SCLK
SSTRB
DOUT*
Figure 5. Quick-Look Circuit
Table 4. Full-Scale and Zero-Scale Voltages
UNIPOLAR MODE
VREFIN + COM +VREFIN / 2
+ COM
Full Scale
COM COM -VREFIN / 2
+ COM
Positive
Full Scale
Zero Scale Zero
Scale
BIPOLAR MODE
Negative
Full Scale
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 50kHz to 500kHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 7 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with two leading zeros and six trailing zeros. The total
conversion time is a function of the serial-clock
frequency and the amount of idle time between 8-bit
transfers. Make sure that the total conversion time does
not exceed 1ms, to avoid excessive T/H droop.
Digital Inputs
CS, SCLK, and DIN can accept input signals up to
5.5V, regardless of the supply voltages. This allows the
MAX1110/MAX1111 to accept digital inputs from both
3V and 5V systems.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SSTRB
CS
SCLK
DIN
DOUT
14 8 12 16 20 24
START
SEL2 SEL1 SEL0 UNI/
BIP SGL/
DIF PD1 PD0
B7 B6 B5 B4 B3 B2 B1 B0
ACQUISITION
(fSCLK = 500kHz)
IDLE
FILLED WITH ZEROS
IDLE
CONVERSION
tACQ
A/D STATE
RB1 RB2 RB3
4µs
Figure 7. Single-Conversion Timing, External Clock Mode, 24 Clocks
CS
SCLK
DOUT
I/O
SCK
MISO
+3V
SS
a) SPI
CS
SCLK
DOUT
CS
SCK
MISO
+3V
SS
b) QSPI
MAX1110
MAX1111
MAX1110
MAX1111
MAX1110
MAX1111
CS
SCLK
DOUT
I/O
SK
SI
c) MICROWIRE
Figure 6. Common Serial-Interface Connections to the
MAX1110/MAX1111
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
______________________________________________________________________________________ 13
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15). For bipolar inputs, the output is two’s-com-
plement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format.
Clock Modes
The MAX1110/MAX1111 can use either an external ser-
ial clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the devices. Bit
PD0 of the control byte programs the clock mode.
Figures 8–11 show the timing characteristics common
to both modes.
External Clock
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
conversion steps. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successive-
approximation bit decisions are made and appear at
DOUT on each of the next eight SCLK falling edges
(Figure 7). After the eight data bits are clocked out,
subsequent clock pulses clock out zeros from the
DOUT pin.
SSTRB and DOUT go into a high-impedance state
when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 9 shows the SSTRB
timing in external clock mode.
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors may degrade conversion
results. Use internal clock mode if the serial-clock fre-
quency is less than 50kHz, or if serial-clock interruptions
could cause the conversion interval to exceed 1ms.
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
tCSH
tCSS tCL
tDS
tDH
tDV tDO
tCH
tDO tTR
tCSH
Figure 8. Detailed Serial-Interface Timing
• • •
• • • • • •
• • • •
• • •
tSDV
tSSTRB
PD0 CLOCKED IN
tSTR
SSTRB
SCLK
CS
tSSTRB
• • • •
Figure 9. External Clock Mode SSTRB Detailed Timing
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
14 ______________________________________________________________________________________
SSTRB
CS
SCLK
DIN
DOUT
14 8 12 15 17
START
SEL2 SEL1 SEL0 UNI/
BIP SGL/
DIF PD1 PD0
B7 B6 B1 B0
tACQ
4µs (fSCLK = 500kHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
25µs TYP
A/D STATE
2 3 5 6 7 9 10 11 16 18
tCONV
Figure 10. Internal Clock Mode Timing
PD0 CLOCK IN
tSSTRB
tCSH
tCONV
tSCK
SSTRB
SCLK
tCSS
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 11. Internal Clock Mode SSTRB Detailed Timing
Internal Clock
Internal clock mode frees the µP from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz. SSTRB goes
low at the start of the conversion and then goes high
when the conversion is complete. SSTRB is low for
25µs (typically), during which time SCLK should remain
low for best noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the second falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 10). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1110/MAX1111 and three-states DOUT, but it
does not adversely affect an internal clock-mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 11 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1110/MAX1111 at clock rates up to 2MHz, pro-
vided that the minimum acquisition time, tACQ, is kept
above 1µs.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
______________________________________________________________________________________ 15
SCLK
DIN
DOUT
CS
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B7 B0 B7 B0 B7
CONVERSION RESULT 1 CONVERSION RESULT 2
SSTRB
CONTROL BYTE 2S
188810 1 10 110 1
CONTROL BYTE 3S
Figure 12a. Continuous Conversions, External Clock Mode, 10 Clocks/Conversion Timing
CS
SCLK
DIN
DOUT
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B7 B0 B7
CONVERSION RESULT 1
Figure 12b. Continuous Conversions, External Clock Mode, 16 Clocks/Conversion Timing
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on the falling edge of SCLK, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after VDD is applied.
OR
The first high bit clocked into DIN after the MSB of a
conversion in progress is clocked onto the DOUT
pin.
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is
terminated, and a new one is started.
The fastest the MAX1110/MAX1111 can run is 10
clocks per conversion. Figure 12a shows the serial-
interface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
Many microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conver-
sion is typically the fastest that a microcontroller can
drive the MAX1110/MAX1111. Figure 12b shows the
serial-interface timing necessary to perform a conver-
sion every 16 SCLK cycles in external clock mode.
Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1110/MAX1111 in internal clock mode. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. No conversions should
be performed until the reference voltage has stabilized
(see
Electrical Characteristics
).
Power-Down
When operating at speeds below the maximum sam-
pling rate, the MAX1110/MAX1111’s automatic power-
down mode can save considerable power by placing
the converters in a low-current shutdown state between
conversions. Figure 13 shows the average supply cur-
rent as a function of the sampling rate.
Select power-down with PD1 of the DIN control byte
with SHDN high or floating (Table 3). Pull SHDN low at
any time to shut down the converters completely. SHDN
overrides PD1 of the control byte. Figures 14a and 14b
illustrate the various power-down sequences in both
external and internal clock modes.
Software Power-Down
Software power-down is activated using bit PD1 of the
control byte. When software power-down is asserted, the
ADCs continue to operate in the last specified clock
mode until the conversion is complete. The ADCs then
power down into a low quiescent-current state. In internal
clock mode, the interface remains active, and conversion
results may be clocked out after the MAX1110/
MAX1111 have entered a software power-down.
The first logical 1 on DIN is interpreted as a start bit,
which powers up the MAX1110/MAX1111. If the DIN byte
contains PD1 = 1, then the chip remains powered up. If
PD1 = 0, power-down resumes after one conversion.
Hard-Wired Power-Down
Pulling SHDN low places the converters in hard-wired
power-down. Unlike software power-down, the conver-
sion is not completed; it stops coincidentally with SHDN
being brought low. SHDN also controls the state of the
internal reference (Table 5). Letting SHDN float enables
the internal 2.048V voltage reference. When returning to
normal operation with SHDN floating, there is a tRC
delay of approximately 1MΩx CLOAD, where CLOAD is
the capacitive loading on the SHDN pin. Pulling SHDN
high disables the internal reference, which saves power
when using an external reference.
External Reference
An external reference between 1V and VDD should be
connected directly at the REFIN terminal. The DC input
impedance at REFIN is extremely high, consisting of
leakage current only (typically 10nA). During a conver-
sion, the reference must be able to deliver up to 20µA
average load current and have an output impedance of
1kΩor less at the conversion clock frequency. If the
reference has higher output impedance or is noisy,
bypass it close to the REFIN pin with a 0.1µF capacitor.
If an external reference is used with the MAX1110/
MAX1111, tie SHDN to VDD to disable the internal refer-
ence and decrease power consumption.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
16 ______________________________________________________________________________________
Table 5. Hard-Wired Power-Down and
Internal Reference State
SHDN
STATE
DEVICE
MODE
1Enabled
Floating Enabled
0Power-Down
INTERNAL
REFERENCE
Disabled
Disabled
Enabled
1000
1
010 30 50
10
100
MAX1110-fig13
SAMPLING RATE (ksps)
SUPPLY CURRENT (µA)
20 40
VDD = VREFIN = 3V
CLOAD AT DOUT AND SSTRB
CLOAD = 30pF
CODE = 11111111
CLOAD = 30pF
CODE = 10101010
CLOAD = 60pF
CODE = 10101010
Figure 13. Average Supply Current vs. Sampling Rate
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
______________________________________________________________________________________ 17
Internal Reference
To use the MAX1110/MAX1111 with the internal refer-
ence, connect REFIN to REFOUT. The full-scale range
of the MAX1110/MAX1111 with the internal reference is
typically 2.048V with unipolar inputs, and ±1.024V with
bipolar inputs. The internal reference should be
bypassed to AGND with a 1µF capacitor placed as
close to the REFIN pin as possible.
Transfer Function
Table 4 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 15 depicts the nominal, unipo-
lar I/O transfer function, and Figure 16 shows the bipolar
I/O transfer function when using a 2.048V reference.
Code transitions occur at integer LSB values. Output cod-
ing is binary, with 1 LSB = 8mV (2.048V/256) for unipolar
operation and 1 LSB = 8mV [(2.048V/2 - -2.048V/2)/256]
for bipolar operation.
POWERED UP POWER-
DOWN POWERED
UP
POWERED UP
DATA VALID DATA VALID DATA
INVALID
EXTERNALEXTERNAL
INTERNAL
SXXXXX11 S 01
XXXXX XX XXX
S11
POWER-
DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS POWER-
DOWN MODE
Figure 14a. Power-Down Modes, External Clock Timing Diagram
POWER-DOWN
POWERED
UP
POWERED UP
DATA VALID DATA VALID
INTERNAL CLOCK MODE
SXXXXX10 S 00
XXXXX S
MODE
DOUT
DIN
SETS INTERNAL
CLOCK MODE
SETS POWER-DOWN MODE
CONVERSION
CONVERSION
SSTRB
Figure 14b. Power-Down Modes, Internal Clock Timing Diagram
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 17 shows the recommended system ground
connections. A single-point analog ground (star ground
point) should be established at AGND, separate from
the logic ground. Connect all other analog grounds and
DGND to the star ground. No other digital system
ground should be connected to this ground. The
ground return to the power supply for the star ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the VDD power supply may
affect the comparator in the ADC. Bypass the supply to
the star ground with 0.1µF and 1µF capacitors close to
the VDD pin of the MAX1110/MAX1111. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +3V power supply is very noisy, a 10Ωresistor can
be connected to form a lowpass filter.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
18 ______________________________________________________________________________________
+3V GND
SUPPLIES
DGND+3VDGND
AGNDVDD
DIGITAL
CIRCUITRY
MAX1110
MAX1111
R* = 10Ω
* OPTIONAL
Figure 17. Power-Supply Grounding Connections
01111111
OUTPUT CODE
01111110
00000010
00000001
00000000
11111111
11111110
11111101
10000001
10000000
-FS COM
INPUT VOLTAGE (LSB) +FS - 1 LSB
2
+FS = VREFIN + COM
2
-FS = -VREFIN + COM
2
COM = VREFIN
2
1LSB = VREFIN
256
Figure 16. Bipolar Transfer Function
OUTPUT CODE FULL-SCALE
TRANSITION
11111111
11111110
11111101
00000011
00000010
00000001
00000000
123
0FS
FS - 1LSB
FS = VREFIN + COM
1LSB = VREFIN
256
INPUT VOLTAGE (LSB)
(COM)
Figure 15. Unipolar Transfer Function
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
______________________________________________________________________________________ 19
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
VDD
SCLK
CS
DIN
CH3
CH2
CH1
CH0
TOP VIEW
SSTRB
DOUT
DGND
AGND
CH7
CH6
CH5
CH4
12
11
9
10
REFOUT
REFIN
SHDN
COM
MAX1110
DIP/SSOP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
CH0
CH1
CH2
CH3
COM
SHDN
REFIN
REFOUT
MAX1111
DIP/QSOP
Pin Configurations
Chip Information
Ordering Information (continued)
**
Contact factory for availability.
/V denotes an automotive qualified part.
TRANSISTOR COUNT: 1996
SUBSTRATE CONNECTED TO DGND
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 Plastic DIP P20-3 21-0043
20 SSOP A20-1 21-0056
20 CERDIP J20-2 21-0045
16 Plastic DIP P16-1 21-0043
16 QSOP E16-1 21-0055
16 CERDIP J16-3 21-0045
PART TEMP RANGE PIN-PACKAGE
MAX1110EPP -40°C to +70°C 20 Plastic DIP
MAX1110EAP -40°C to +70°C 20 SSOP
MAX1110MJP -55°C to +70°C 20 CERDIP**
MAX1111CPE 0°C to +70°C 16 Plastic DIP
MAX1111CEE 0°C to +70°C 16 QSOP
MAX1111EPE -40°C to +70°C 16 Plastic DIP
MAX1111EEE -40°C to +70°C 16 QSOP
MAX1111EEE/V+ -40°C to +70°C 16 QSOP
MAX1111MJE -55°C to +70°C 16 CERDIP**
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
3 2/10 Added automotive qualified part to data sheet 19
