08/2001
ARA3000
Address-Programmable Telephony
Reverse Amplifier with Step Attenuator
PRELIMINARY DATA SHEET - Rev 1.1
FEATURES
·Low cost integrated amplifier with step
attenuator
·Attenuation Range: 0-56 dB, adjustable in 2 dB
increments via a 3 wire serial control
·Meets DOCSIS distortion requirements at a
+60dBmV output signal level
·Programmable address allows multiple parts
to share control bus
·Programmable 2 bit data port output
·Low distortion and low noise
·Frequency range: 5-100 MHz
·5 Volt operation
·-40 to +85 oC temperature range
APPLICATIONS
·DOCSIS Compliant IP Telephony Systems
·CATV Interactive Set-Top Box
·OpenCable Set-Top Box
·Residential Gateway
The ARA3000 is designed to provide additional
reverse path amplification and isolation in IP
Telephony systems. It incorporates a digitally
controlled precision step attenuator, followed by a
single-stage output amplifier that exceeds DOCSIS
distortion and noise requirements at a +60dBmV
output level while only requiring a single polarity +5V
supply. The precision attenuator can handle input
powers up to +58 dBmV, and provides up to 56 dB of
attenuation in 2 dB increments. The output amplifier
stage can be shut down and bypassed by a low
insertion loss switch on-chip to save power. The
ARA3000 has a programmable address that allows
multiple devices to share a common control bus,
and a 2-bit data port for control of external devices.
The ARA3000 is offered in a 28-pin SSOP package
featuring an exposed paddle on the bottom of the
package.
PRODUCT DESCRIPTION
Figure 1. Functional Block Diagram
S23 Package
28 Pin SSOP
with Exposed Paddle
Serial to Parallel
Interface
5 Bit Attenutor
32 / 16 / 8 / 4 / 2dB
2
Data Port
D[1:0]
ATTN
IN
CLK ENDAT Address
C[1:0] V
CTRL
AMP
OUT
Bypass
2
2PRELIMINARY DATA SHEET - Rev 1.1
08/2001
ARA3000
Table 1: Pin Description
Figure 2: Pin Out
NIP EMAN NOITPIRCSED NIP EMAN NOITPIRCSED
1PMA
NI
tupnIreifilpmA510C0sserddAeciveD
2NTTA
TUO
tuptuOrotaunettA
)2(
611C1sserddAeciveD
3C/NnoitcennoCoN
)1(
710D0tuptuOtroPataD
4NTTA
2GCA
2dnuorGCArotaunettA
)3(
811D1tuptuOtroPataD
5NTTA
2GCA
2dnuorGCArotaunettA
)3(
91DNG
SOMC
SOMClatigiDrofdnuorG
tiucriC
6NTTA
2GCA
2dnuorGCArotaunettA
)3(
02DNGdnuorG
7NTTA
1GCA
1dnuorGCArotaunettA
)3(
12V
LRTC
lortnoCreifilpmA
)ssapyB/elbanE(
8NTTA
1GCA
1dnuorGCArotaunettA
)3(
22PMA
1GCA
1dnuorGCAreifilpmA
)3(
9NTTA
NI
tupnIrotaunettA
)2(
32PMA
TUO
tuptuOreifilpmA
01V
NTTA
ylppuSrotaunettA42DNGdnuorG
11V
SOMC
SOMClatigiDroFylppuS
tiucriC 52DNGdnuorG
21KLCkcolC62PMA
2GCA
2dnuorGCAreifilpmA
)3(
31TADataD72ssapyBtuptuOssapyBreifilpmA
)2(
41NEelbanE82DNGdnuorG
Notes:
(1) The N/C pin should be grounded
(2) Pins should be AC-coupled. No external DC bias should be applied.
(3) Pins should be AC-grounded. No external DC bias should be applied.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AMP
IN
GND
V
CMOS
CLK
ATTN
ACG2
N/C
DAT
ATTN
OUT
EN
ATTN
IN
V
CTRL
D1
D0
AMP
OUT
C1
Bypass
C0
V
ATTN
GND
CMOS
GND
ATTN
ACG1
ATTN
ACG1
ATTN
ACG2
ATTN
ACG2
GND
GND
AMP
ACG1
AMP
ACG2
PRELIMINARY DATA SHEET - Rev 1.1
08/2001
3
ARA3000
ELECTRICAL CHARACTERISTICS
RETEMARAP NIM XAM TINU
)32,01snip(ylppuSgolanA09CDV
V:ylppuSlatigiD CMOS )11nip( 06 CDV
V:lortnoCreifilpmA CTRL )12nip(5-6V
FR
tupnItarewoP
)9nip(
-85VmBd
)61,51,41,31,21snip(ecafretnIlatigiD5.0-V
CMOS 5.0+V
erutarepmeTegarotS55-002+
o
C
erutarepmeTgniredloS-062
o
C
emiTgniredloS-5ceS
Table 2: Absolute Minimum and Maximum Ratings
Table 3: Operating Ranges
RETEMARAP NIM PYT XAM TINU
V:ylppuSgolanA
DD
)32,01snip(5.457 CDV
V:ylppuSlatigiD
CMOS
)11nip(0.3-5.5CDV
)61,51,41,31,21snip(ecafretnIlatigiD0-V
CMOS
V
V:lortnoCreifilpmA
CTRL
)12nip( 03 5.5V
erutarepmeTesaC04-5258
o
C
Stresses in excess of the absolute ratings may cause permanent damage. Functional
operation is not implied under these conditions. Exposure to absolute ratings for
extended periods of time may adversely affect reliability.
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical specifications.
Notes:
1. Pins 2, 9 and 27 should be AC-coupled. No external DC bias should be applied.
2. Pin 1 should be pulled to ground through a resistor. No external DC bias should be
applied.
3. Pins 4, 5, 6, 7, 8, 22 and 26 should be AC-grounded. No external DC bias should be
applied.
4PRELIMINARY DATA SHEET - Rev 1.1
08/2001
ARA3000
RETEMARAP NIM PYT XAM TINU STNEMMOC
)32,01snip(tnerruCylppuSgolanA -
-
021
21
-
-Am delbanereifilpmA
dessapybreifilpmA
)11nip(tnerruCylppuSlatigiDSOMC-2-AmgnittesnoitaunettaxaM
noitpmusnoCrewoPlatoT -
-
016
07
-
-
Wm
Wm
delbanereifilpmA
dessapybreifilpmA
Note: As measured in ANADIGICS test fixture
Table 4: DC Electrical Specifications
TA=25°C; VDD, VCMOS = +5.0 VDC; VCTRL = +5.0 V (Amp enabled); VCTRL = 0 V (Amp bypassed)
RETEMARAP NIM PYT XAM TINU STNEMMOC
niaG
4161-Bd,gnittesnoitaunettaBd0
delbanereifilpma
5.2-7.1--Bd,gnittesnoitaunettaBd0
dessapybreifilpma
ssentalFniaG-5.0-BdzHM24ot5
erutarepmeTrevonoitairaVniaG-600.0--C°/Bd
spetSnoitaunettA
Bd2
Bd4
Bd8
Bd61
Bd23
45.1
6.3
7.7
5.51
2.03
57.1
9.3
1.8
9.51
7.03
0.2
2.4
3.8
3.61
2.13
BdcinotonoM
noitalosImumixaM-06-Bd,gnittesnoitunettaBd26
delbasidreifilpma
2
dn
leveLnoitrotsiDcinomraH
-55-84-cBd P
OUT
57otniVmBd06+=
delbanereifilpma,smhO
-06-84-cBd P
IN
57morfVmBd85+=
dessapybreifilpma,smhO
3
dr
leveLnoitrotsiDcinomraH
-06-84-cBd P
OUT
57otniVmBd06+=
delbanereifilpma,smhO
-06-84-cBd P
IN
57morfVmBd85+=
dessapybreifilpma,smhO
Table 5: AC Electrical Specifications
TA=25°C; VDD, VCMOS = +5.0 VDC; VCTRL = +5.0 V (Amp enabled); VCTRL = 0 V (Amp bypassed)
PRELIMINARY DATA SHEET - Rev 1.1
08/2001
5
ARA3000
RETEMARAP NIM PYT XAM TINU STNEMMOC
tpecretnItuptuOredrOdr387-- VmBddelbanereifilpmA
tnioPnoisserpmoCniaGBd1-07- VmBddelbanereifilpmA
erugiFesioN-5.3-Bd
ecnadepmItupnI-57- smhO
ssoLnruteRtupnI -
-
02-
31-
-
-Bd delbanereifilpmA
dessapybreifilpmA
ecnadepmItuptuO-57- smhO
ssoLnruteRtuptuO -
-
51-
31-
-
-Bd delbanereifilpmA
dessapybreifilpmA
Note: As measured in ANADIGICS test fixture
continued: AC Electrical Specifications
TA=25°C; VDD, VCMOS = +5.0 VDC; VCTRL = +5.0 V (Amp enabled); VCTRL = 0 V (Amp bypassed)
6PRELIMINARY DATA SHEET - Rev 1.1
08/2001
ARA3000
Figure 3: Test Circuit
227
16
15
1
14
22
24
25
23
21
20
19
18
17
28
26
9
8
7
10
6
11
5
12
4
13
3
AMP
IN
N/C
ATTN
ACG2
ATTN
OUT
V
ATTN
V
CMOS
CLK
DAT
EN C0
V
CTRL
AMP
OUT
GND
AMP
ACG1
GND
CMOS
GND
GND
D0
Bypass
C1
GND
ATTN
IN
AMP
ACG2
ATTN
ACG1
ATTN
ACG1
ATTN
ACG2
ATTN
ACG2
D1
(75 Ohms)
0.1uF
0.1uF RF Outpu
(75 Ohms
+5 V
1uF
0.1uF
Clock
Enable
Data
+5 V
0.1uF
RF Input
0.1uF
ARA3000
1uF
0.1uF
0.1uF 10uH
0.1uF
D0
0.1uF
1 KOhm
0.1uF
Note:
Pins 15 and 16 are grounded
on the ANADIGICS test fixture,
identifying device address "00".
PRELIMINARY DATA SHEET - Rev 1.1
08/2001
7
ARA3000
DATA
CLOCK
ENABLE
ENABLE
OR
D
15
: MSB D
14
D
8
D
7
D
1
D
0
: LSB
Table 6: Programming Word
LOGIC PROGRAMMING
Table 7: Data Description
Figure 4: Serial Data Input Timing
EULAV
RETSIGER
"00"SSERDDA
NOITCNUF
RETSIGER
"11"SSERDDA
NOITCNUF
)ssapyb=0,no=1(
7PA/NA/N
6PA/NA/N
5PA/NtiBrotaunettABd23
4PA/NtiBrotaunettABd61
3PA/NtiBrotaunettABd8
2PA/NtiBrotaunettABd4
1P ataDlanretxE
tuptuO1troP tiBrotaunettABd2
0PataDlanretxE
tuptuO0troP A/N
Table 8: Device Address
OTTUPNILEVELCIGOL
ECIVEDSSERDDA
1C 0C )1C(61niP )0C(51niP
00 0 0
10 1 0
01 0 1
11 1 1
TIBATAD D
51
D
41
D
31
D
21
D
11
D
01
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
eulaV 7P6P5P4P3P2P1P0P 0001 1C0C1A0A
Programming Instructions
The programming word is set through a 16 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the
data entry, then set high to latch the shift register.
The rising edge of the clock pulse shifts each data
value into the register.
1A 0A NOITCNUF
00 delbanEtuptuOtroPataD
11 delbanElortnoCrotaunettA
Table 9: Register Address
The device is selected when the logic inputs at pins
16 and 15 match the values of data bits C1 and C0,
respectively.
8PRELIMINARY DATA SHEET - Rev 1.1
08/2001
ARA3000
APPLICATION INFORMATION
Amplifier Enable and Disable/Bypass
The amplifier in the ARA3000 can be shut down and
bypassed via external control pin VCTRL (pin 21). By
applying a logic high voltage to this pin, the amplifier
is enabled and the output is routed to AMPOUT (pin
23). A logic low will disable the amplifier, bypass it,
and route the attenuator output to the Bypass pin
(pin 27).
A practical way to implement amplifier control is to
connect one of the data port outputs to the VCTRL input,
allowing the attenuator to be controlled through the
serial programming interface.
Output Power Control
The amplifier is designed to achieve the specified
distortion levels at a nominal output power of +60
dBmV. When higher input powers are applied to the
device, the attenuator should be adjusted to maintain
the appropriate output power.
Thermal Layout Considerations
The device package for the ARA3000 features an
exposed paddle on the bottom of the package body.
Use of the paddle is an integral part of the device
design. Soldering this paddle to the ground plane of
the PC board will ensure the lowest possible thermal
resistance for the device, and will result in the longest
MTF (mean time to failure.)
A PC board layout that optimizes the benefits of the
paddle is shown in Figure 5. The via holes located
under the body of the device must be plated through
to a ground plane layer of metal, in order to provide a
sufficient heat sink. The recommended solder mask
outline is shown in Figure 6.
ESD Sensitivity
Electrostatic discharges can cause permanent
damage to this device. Electrostatic charges
accumulate on test equipment and the human body,
and can discharge without detection. Proper
precautions and handling are strongly
recommended. Refer to the ANADIGICS application
note on ESD precautions.
Figure 5: PC Board Layout
PRELIMINARY DATA SHEET - Rev 1.1
08/2001
9
ARA3000
Figure 6: Solder Mask Outline
10 PRELIMINARY DATA SHEET - Rev 1.1
08/2001
ARA3000
NOTE
1. PACKAGE BODY S IZES EXC LUDE MOLD FLASH AND
GATE BURRS
2. TOLERANCE 0.004in.[0.10 mm] UNLESS OTHERWISE SPECIFIED
3. CONTROLL ING DIMENSION ARE INCHES.
4. REF. - MO-137
A1
y
θ
D
e
L
E
H
b
C
A2
SYMBOLS
A0.0040.000
0.025
0.150
0°
−−−
0.016
0.228
0.386
0.007
0.008
0.004
8°
0.394
0.050
0.157
0.244
0.012
0.010
DIMEN SIONS IN INCHES
0.057
MIN MAX
0.061
θ
S
T0.096
0.190
−−−
−−−
0.100.00
.64
3.81
0°
−−−
0.40
5.80
9.80
0.18
0.20
0.10
8°
10.00
1.27
4.00
6.20
0.30
0.25
DIM EN SION S IN MILLIMETERS
1.45
MIN MAX
1.55
2.43
4.82
−−−
−−−
0.057 1.45
Figure 7: S23 Package Outline - 28 Pin SSOP with Exposed Paddle
PACKAGE OUTLINE
PRELIMINARY DATA SHEET - Rev 1.1
08/2001
11
ARA3000
COMPONENT PACKAGING
Figure 9: Tape Dimensions
Volume quantities of the ARA3000 are supplied on
tape and reel. Each reel holds 3,500 pieces. Smaller
quantities are available in plastic tubes of 50 pieces.
Figure 8: Reel Dimensions
DIRECTION OF FEED
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a products formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
PRELIMINARY DATA SHEET - Rev 1
08/2001
12
ARA3000
REBMUNREDRO ERUTAREPMET
EGNAR
EGAKCAP
NOITPIRCSED GNIGAKCAPTNENOPMOC
1P32S0003ARA58ot04-
o
ChtiwPOSSniP82
elddaPdesopxE leerdnaepateceip005,3
0P32S0003ARA58ot04-
o
ChtiwPOSSniP82
elddaPdesopxE )ebutrepseceip05(sebutcitsalP
ORDERING INFORMATION
