UC1825A-SP www.ti.com ..................................................................................................................................................... SLUS873A - JANUARY 2009 - REVISED APRIL 2009 RAD-TOLERANT CLASS-V, HIGH-SPEED PWM CONTROLLER FEATURES DESCRIPTION 1 * * * * * * * * * * (1) QML-V Qualified, SMD 5962-87681 Rad-Tolerant: 30 kRad (Si) TID (1) Compatible With Voltage-Mode or Current-Mode Control Methods Practical Operation at Switching Frequencies to 1 MHz 50-ns Propagation Delay to Output High-Current Dual Totem Pole Outputs (2-A Peak) Trimmed Oscillator Discharge Current Low 100-A Startup Current Pulse-by-Pulse Current Limiting Comparator Latched Overcurrent Comparator With Full Cycle Restart The UC1825A PWM controller is an improved version of the standard UC1825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is assured to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100 A, is ideal for off-line applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the startup current specification. In addition each output is capable of 2-A peak currents during transitions. xxx xxx Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for details. BLOCK DIAGRAM 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009, Texas Instruments Incorporated UC1825A-SP SLUS873A - JANUARY 2009 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Functional improvements have also been implemented in this family. The UC1825 shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The UC1825 CLOCK pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing. The UC1825A has dual alternating outputs and the same pin configuration of the UC1825. A version parts have UVLO thresholds identical to the original UC1825. ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING -55C to 125C CDIP-16 5962-8768105VEA UC1825AJ-SP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. PIN ASSIGNMENTS J PACKAGE (TOP VIEW) INV NI EAOUT CLK/LEB RT CT RAMP SS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VREF VCC OUTB VC PGND OUTA GND ILIM THERMAL INFORMATION (1) 2 PACKAGE JA JC J-16 80-120 28 (1) JC data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states, "The baseline values shown are worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device die size greater than 14400 square mils use the following values; dual-in-line, 11C/W; flat pack, 10C/W; pin grid array, 10C/W". Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP UC1825A-SP www.ti.com ..................................................................................................................................................... SLUS873A - JANUARY 2009 - REVISED APRIL 2009 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION CLK/LEB 4 O Output of the internal oscillator CT 6 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. EAOUT 3 O Output of the error amplifier for compensation GND 10 ILIM 9 I Input to the current limit comparator INV 1 I Inverting input to the error amplifier NI 2 I Non-inverting input to the error amplifier OUTA 11 O High current totem pole output A of the on-chip drive stage. OUTB 14 O High current totem pole output B of the on-chip drive stage. PGND 12 RAMP 7 I Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input. RT 5 I Timing resistor connection pin for oscillator frequency programming SS 8 I Soft-start input pin which also doubles as the maximum duty cycle clamp. VC 13 Power supply pin for the output stage. This pin should be bypassed with a 0.1-F monolithic ceramic low ESL capacitor with minimal trace lengths. VCC 15 Power supply pin for the device. This pin should be bypassed with a 0.1-F monolithic ceramic low ESL capacitor with minimal trace lengths VREF 16 Analog ground return pin Ground return pin for the output driver stage O 5.1-V reference. For stability, the reference should be bypassed with a 0.1-F monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) VALUE UNIT VIN Supply voltage, VC, VCC 22 V IO Source or sink current,DC OUTA, OUTB 0.5 A IO Source or sink current, pulse (0.5 s) OUTA, OUTB 2.2 A INV, NI, RAMP -0.3 to 7 V ILIM, SS -0.3 to 6 V 0.2 V Analog inputs Power ground PGND Outputs OUTA, OUTB Clock output current PGND - 0.3 to VC + 0.3 V CLK/LEB -5 mA IO(EA) Error amplifier output current EAOUT 5 mA ISS Soft-start sink current SS 20 mA IOSC Oscillator charging current RT -5 mA TJ Operating virtual junction temperature range -55 to 150 C TSTG Storage temperature -65 to 150 C 300 C ICLK Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP 3 UC1825A-SP SLUS873A - JANUARY 2009 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (TA = TJ = -55C to 125C), unless otherwise noted. VCC MIN MAX 12 20 V Sink/source output current (continuous or time average) 0 100 mA Reference load current 0 10 mA Supply voltage UNIT ELECTRICAL CHARACTERISTICS TA = -55C to 125C, RT = 3.65 k, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.05 5.1 5.15 V REFERENCE, VREF VO Ouput voltage range TJ = 25C, IO = 1 mA Line regulation 12 V VCC 20 V 2 15 Load regulation 1 mA IO 10 mA 5 20 Total output variation Line, load, temperature Temperature stability (1) T(min) < TA < T(max) Output noise voltage 10 Hz < f < 10 kHz Short circuit current VREF = 0 V 5.03 0.2 mV 5.17 V 0.4 mV/C VRMS 50 30 60 90 mA TJ = 25C 375 400 425 kHz RT = 6.6 k, CT = 220 pF, TA = 25C 0.9 1 1.1 MHz Line, temperature 350 450 kHz RT = 6.6 k, CT = 220 pF 0.82 1.18 MHz OSCILLATOR fOSC Initial accuracy (1) Total variation (1) Voltage stability 12 V < VCC < 20 V Temperature stability T(min) < TA < T(max) High-level output voltage, clock 1% 5% 3.7 4 Ramp peak 2.6 2.8 3 Ramp valley 0.7 1 1.25 1.55 1.8 2 8.5 10 11 mA mV Low-level output voltage, clock 0 Ramp valley-to-peak IOSC Oscillator discharge current RT = OPEN, VCT = 2 V 0.2 V ERROR AMPLIFIER Input offset voltage 2 10 Input bias current 0.6 3 Input offset current 0.1 1 A Open loop gain 1 V < VO < 4 V 60 CMRR Common mode rejection ratio 1.5 V < VCM < 5.5 V 75 95 PSRR Power supply rejection ratio 12 V < VCC < 20 V 85 110 IO(sink) Output sink current VEAOUT = 1 V 1 2.5 IO(src) Output source current VEAOUT = 4 V -0.5 -1.3 High-level output voltage IEAOUT = -0.5 mA 4.5 4.7 5 Low-level output voltage IEAOUT = -1 mA 0 0.5 1 Gain bandwidth product (1) f = 200 kHz 6 12 Mhz 5 7 V/s Slew rate (1) (1) 4 95 dB mA V Parameters ensured by design and/or characterization, if not production tested. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP UC1825A-SP www.ti.com ..................................................................................................................................................... SLUS873A - JANUARY 2009 - REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS (Continued) TA = -55C to 125C, RT = 3.65 k, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIIONS MIN TYP MAX UNIT PWM COMPARATOR IBIAS Bias current, RAMP VRAMP = 0 V -1 Minimum duty cycle -8 A 0% Maximum duty cycle 85% tLEB Leading edge blanking time RLEB = 2 k, CLEB = 470 pF RLEB Leading edge blanking resistance VCLK/LEB = 3 V VZDC Zero dc threshold voltage, EAOUT VRAMP = 0 V tDELAY Delay-to-output time (1) 300 375 450 ns 8.5 10.0 11.5 k 1.10 1.25 1.4 V 50 120 ns 20 A A VEAOUT = 5 V to 0 V step CURRENT LIMIT / START SEQUENCE / FAULT ISS Soft-start charge current VSS Full soft-start threshold voltage IDSCH Restart discharge current ISS Restart threshold voltage IBIAS ILIM bias current ICL Current limit threshold voltage 0.95 1 1.05 Overcurrent threshold voltage 1.14 1.2 1.26 50 80 td Delay-to-output time, ILIM (1) VSS= 2.5 V VSS= 2.5 V 8 14 4.3 5 100 250 350 0.3 0.5 V 15 A 0 V VILIM 1.5 V VILIM = 0 V to 2 V step V V ns OUTPUT tr, tf Low-level output saturation voltage IOUT = 20 mA 0.25 0.45 IOUT = 200 mA 1.2 2.2 High-level output saturation voltage IOUT = -20 mA 1.9 2.9 2 3 20 45 Rise/fall time (1) IOUT = -200 mA CL = 1 nF V ns UNDERVOLTAGE LOCKOUT (UVLO) Start threshold voltage 8.3 9.2 9.6 UVLO hysteresis 0.4 0.8 1.25 100 300 A 28 36 mA V SUPPLY CURRENT Isu Startup current ICC Input current (1) VC = VCC = 8 V Parameters ensured by design and/or characterization, if not production tested. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP 5 UC1825A-SP SLUS873A - JANUARY 2009 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com APPLICATION INFORMATION The oscillator of the UC1825A is a saw tooth. The rising edge is governed by a current controlled by the RT pin and value of capacitance at the CT pin (CCT). The falling edge of the sawtooth sets dead time for the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based on the desired frequency (RT) and DMAX. The design equations are: RT + 3V (10 mA) 1 * DMAX CT + 1.6 R T D MAX f (1) Recommended values for RT range from 1 k to 100 k. Control of DMAX less than 70% is not recommended. UDG-95102 Figure 1. Oscillator OSCILLATOR FREQUENCY vs TIMING RESISTANCE MAXIMUM DUTY CYCLE vs TIMING RESISTANCE 100 10 M DMAX - Maximum Duty Cycle - % f - Frequency - Hz 95 1M 100 k 10 k 90 85 80 75 70 1k 10 k 100 k 1k RT - Timing Resistance - W Figure 2. 6 10 k RT - Timing Resistance - W 100 k Figure 3. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP UC1825A-SP www.ti.com ..................................................................................................................................................... SLUS873A - JANUARY 2009 - REVISED APRIL 2009 LEADING EDGE BLANKING The UC1825A performs fixed frequency pulse width modulation control. The UC1825A outputs are alternately controlled. During every other cycle, one output is off. Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%. To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator. On the falling edge of the clock, the appropriate output is driven high. The end of the pulse is controlled by the PWM comparator, current limit comparator, or the overcurrent comparator. Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not require any filtering as result of leading edge blanking. To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal 10-k resistor determines the blanked interval. The 10-k resistor has a 10% tolerance. For more accuracy, an external 2-k 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 k with a tolerance of 2.4%. The design equation is: t LEB + 0.5 R o 10 kW C (2) Values of R less than 2 k should not be used. Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold, the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this reason, some noise filtering may be required on the ILIM pin. UDG-95105 Figure 4. Leading Edge Blanking Operational Waveforms UVLO, SOFT-START AND FAULT MANAGEMENT Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier output is also forced low. While the internal 9-A source charges the SS pin, the error amplifier output follows until closed loop regulation takes over. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP 7 UC1825A-SP SLUS873A - JANUARY 2009 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is then discharged by a 250-A current sink. No more output pulses are allowed until soft-start is fully discharged and ILIM is below 1.2 V. At this point the fault latch resets and the chip executes a soft-start. Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor does not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions. UDG-95106 Figure 5. Soft-Start and Fault Waveforms ACTIVE LOW OUTPUTS DURING UVLO The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate. UDG-95108 Figure 6. Output Voltage vs Output Current 8 Submit Documentation Feedback UDG-95106 Figure 7. Output V and I During UVLO Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP UC1825A-SP www.ti.com ..................................................................................................................................................... SLUS873A - JANUARY 2009 - REVISED APRIL 2009 CONTROL METHODS Current Mode Voltage Mode UDG-95110 UDG-95109 . Figure 8. Control Methods SYNCHRONIZATION The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge of the CLK/LEB pin can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no longer accepts an incoming synchronizing signal. UDG-95113 Figure 9. General Oscillator Synchronization Figure 10. Two Unit Interface UDG-95112 Figure 11. Operational Waveforms Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP 9 UC1825A-SP SLUS873A - JANUARY 2009 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com HIGH CURRENT OUTPUTS Each totem pole output of the UC1825A can deliver a 2-A peak current into a capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground (PGND) pins help decouple the device's analog circuitry from the high-power gate drive noise. The use of 3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC and PGND are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive load, typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. DO NOT USE standard silicon diodes. UDG-95114 Figure 12. Power MOSFET Drive Circuit GROUND PLANES Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high frequency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection for input power to the system and the bulk input capacitor. The output should be clamped with a high current Schottky diode to both VCC and PGND. Nothing else should be connected to power ground. VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog circuitry should likewise be bypassed to the signal ground plane. 10 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP UC1825A-SP www.ti.com ..................................................................................................................................................... SLUS873A - JANUARY 2009 - REVISED APRIL 2009 UDG-95115 Figure 13. Ground Planes Diagram OPEN LOOP TEST CIRCUIT This test fixture is useful for exercising many functions of this device family and measuring their specifications. As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly recommended. UDG-95116 Figure 14. Open Loop Test Circuit Schematic Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825A-SP 11 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 5962-8768102V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-8768102VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 5962-8768105VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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