eGaN(R) FET DATASHEET EPC2014 EPC2014 - Enhancement Mode Power Transistor VDSS , 40 V RDS(ON) , 16 mW ID , 10 A NEW PRODUCT EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 55 years. GaN's exceptionally high electron mobility and low temperature coefficient allows very low RDS(ON), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. EPC2014 eGaN(R) FETs are supplied only in passivated die form with solder bumps Maximum Ratings VDS ID VGS TJ TSTG Drain-to-Source Voltage (Continuous) 40 V Drain-to-Source Voltage (up to 10,000 5ms pulses at 125 C) 48 V Continuous (TA = 25C, JA = 40) 10 Pulsed (25C, Tpulse = 300 s) 40 Gate-to-Source Voltage 6 Gate-to-Source Voltage -5 Operating Temperature -40 to 150 Storage Temperature -40 to 150 PARAMETER Applications * High Speed DC-DC conversion * Class D Audio * Hard Switched and High Frequency Circuits A Benefits * Ultra High Efficiency * Ultra Low RDS(on) * Ultra low QG * Ultra small footprint V C TEST CONDITIONS MIN 40 TYP MAX UNIT Static Characteristics (TJ= 25C unless otherwise stated) BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 A IDSS Drain Source Leakage VDS = 32 V, VGS = 0 V 50 100 Gate-Source Forward Leakage VGS = 5 V 0.4 2 Gate-Source Reverse Leakage VGS = -5 V 0.1 0.5 VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 2 mA 1.4 2.5 V RDS(ON) Drain-Source On Resistance VGS = 5 V, ID = 5 A 12 16 m IGSS 0.7 V A mA Source-Drain Characteristics (TJ= 25C unless otherwise stated) VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V, T = 25C 1.3 IS = 0.5 A, VGS = 0 V, T = 125C 1.4 V All measurements were done with substrate shorted to source. Thermal Characteristics TYP RJC Thermal Resistance, Junction to Case 6.9 C/W RJB Thermal Resistance, Junction to Board 32 C/W RJA Thermal Resistance, Junction to Ambient (Note 1) 80 C/W Note 1: RJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 1 eGaN(R) FET DATASHEET EPC2014 Dynamic Characteristics (TJ= 25C unless otherwise stated) CISS Input Capacitance COSS Output Capacitance CRSS 300 325 150 170 Reverse Transfer Capacitance 10.2 12.5 QG Total Gate Charge 2.48 2.8 QGD Gate to Drain Charge 0.48 0.6 QGS Gate to Source Charge 0.67 0.8 QOSS Output Charge 4.8 6 QRR Source-Drain Recovery Charge VDS = 20 V, VGS = 0 V VDS = 20 V, ID = 10 A VDS = 20 V, VGS = 0 V pF nC 0 All measurements were done with substrate shorted to source. Figure 2: Transfer Characteristics 40 35 35 30 30 25 ID Drain Current (A) ID Drain Current (A) Figure 1: Typical Output Characteristics 40 VGS = 5 VGS = 4 VGS = 3 VGS = 2 20 15 15 5 5 0.4 0.6 0.8 1 1.2 1.4 VDS - Drain to Source Voltage (V) 1.6 1.8 0 2 Figure 3: RDS(ON) vs. VGS for Various Drain Current 70 50 ID = 4 A ID = 6 A ID = 15 A ID = 30 A 40 RDS(ON) - Drain to Source Resistance (m) RDS(ON) - Drain to Source Resistance (m) 20 10 0.2 30 20 10 0 1.5 2 2.5 3 3.5 VGS - Gate to Source Voltage (V) 4 4.5 VDS = 3 V 25 10 0 0 25C 125C 0 0.5 1 1.5 2 2.5 3 VGS - Gate to Source Voltage (V) 3.5 4 Figure 4: RDS(ON) vs. VGS for Various Temperatures 25C 125C 60 50 40 30 20 10 0 2 2.5 EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | 3 3.5 4 4.5 VGS - Gate to Source Voltage (V) 5 5.5 | PAGE 2 eGaN(R) FET DATASHEET 0.35 EPC2014 Figure 5: Capacitance Figure 6: Gate Charge 5 ID = 10 A VD = 20 V 0.25 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 0.2 4 VGS - Gate to Source Voltage (V) C - Capacitance (nF) 0.3 0.15 0.1 3 2 1 0.05 0 0 20 5 10 15 20 25 30 VDS - Drain to Source Voltage (V) 35 Normalized On-State Resistance - RDS(ON) ISD - Source to Drain Current (A) 1 1.5 2 QG - Gate Charge (nC) 2.5 Figure 8: Normalized On Resistance vs. Temperature VGS = 0 V 10 5 0 0.5 1 1.5 2 2.5 3 VSD - Source to Drain Voltage (V) ID = 10 A VGS = 5 V 2 1.8 1.6 1.4 1.2 1 0.8 -20 3.5 Figure 9: Normalized Threshold Voltage vs. Temperature 40 60 80 100 TJ - Junction Temperature ( C ) 120 140 160 25C 125C .025 IG - Gate Current (A) 1 0.8 0.6 0.2 -20 20 Figure 10: Gate Current 1.2 0.4 0 .03 1.4 Normalized Threshold Voltage 0.5 2.2 15 1.6 0 Figure 7: Reverse Drain-Source Characteristics 25C 125C 0 0 40 .02 .015 .01 .005 ID = 2 mA 0 20 40 60 80 100 120 140 160 0 0 1 TJ - Junction Temperature ( C ) 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) All measurements were done with substrate shortened to source. EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 3 eGaN(R) FET DATASHEET EPC2014 Figure 11: Transient Thermal Response Curves Normalized Maximum Transient Thermal Impedance ZJB, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.1 0.2 0.1 0.05 0.01 0.02 0.01 t1 Single Pulse 0.001 0.0001 PDM 10-5 10-4 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZJB x RJB + TB 10-3 10-2 10-1 1 10 100 tp, Rectangular Pulse Duration, seconds Normalized Maximum Transient Thermal Impedance ZJC, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.1 0.2 0.1 PDM 0.05 t1 0.01 0.02 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZJC x RJC + TC Single Pulse 0.001 t2 10-6 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds 100 I D- Drain Current (A) Figure 12: Safe Operating Area 10 s 10 100 s limited by RDS(ON) 1 ms 1 10 ms 100 ms/DC 0.1 TJ = Max Rated, TC = +25C, Single Pulse 0.1 1 10 100 VDS - Drain-Source Voltage (V) EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 4 eGaN(R) FET DATASHEET EPC2014 TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7" reel b e d g f Loaded Tape Feed Direction 7" reel Die orientation dot c a Gate solder bar is under this corner Die is placed into pocket solder bar side down (face side down) EPC2014 (note 1) Dimension (mm) target a b c (see note) d e f (see note) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 min max 7.90 8.30 1.65 1.85 3.45 3.55 3.90 4.10 3.90 4.10 1.95 2.05 1.5 1.6 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2014 YYYY Die orientation dot Part Number ZZZZ Gate Pad bump is under this corner Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 2014 YYYY ZZZZ EPC2014 A DIE OUTLINE f Solder Bar View f X3 DIM 4 A B c d e f g c 3 5 B d X2 2 1 MAX 1672 1057 834 327 235 195 400 1702 1087 837 330 250 200 400 1732 1117 840 333 265 205 400 g X2 SEATING PLANE 100 +/- 20 (685) Side View g micrometers Nominal 815 Max e MIN EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 5 00 eGaN(R) FET DATASHEET EPC2014 RECOMMENDED LAND PATTERN The land pattern is solder mask defined Solder mask is 10um smaller per side than bump (measurements in m) 1702 Pad no. 1 is Gate 507 5 2 Pad no. 2 is Substrate 1 Pad no. 3 and 5 are Drain Pad no. 4 is Source 3 4 5 2 400 180 400 X2 180 X3 4 5 3 4 5 1087 3 1 817 310 1702 2 400 X2 180 180 X3 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN(R) is a registered trademark of Efficient Power Conversion Corporation. U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398 EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | Information subject to change without notice. revised July, 2013 | PAGE 6 1087 4 3 817 310 1