August 2009
Copyright © Alliance Memory Inc. . All rights reserved.
®
AS7C1025B
5V 128K X 8 CMOS SRAM (Center power and ground)
Aug 2009 v 1.4 Alliance Memory Inc. P. 1 of 9
Features
•Industrial and commercial temperatures
•Organization: 131,072 x 8 bits
•High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
•Low power consumption: ACTIVE
- 605mW / max @ 10 ns
•Low power consumption: STANDBY
- 55 mW / max CMOS
•6 T 0.18 u CMOS technology
•Easy memory expansion with
CE
,
OE
inputs
•Center power and ground
•TTL/LVTTL-compatible , three-state I/O
•JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
•ESD protection ≥ 2000 volts
•Latch-up current ≥ 200 mA
Logic block diagram
512 x 256 x 8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE
WE
Column decoder
Row decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
AS7C1025B
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
Selection guide
-10 -12-15-20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum operating current 110 100 90 80 mA
Maximum CMOS standby current 10 10 10 10 mA
AS7C1025B
Aug/09, v. 1.4Alliance Memory Inc. P. 2 of 9
®
Functional description
The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8
bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high-
performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full
standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.
A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data on the input pins I/O0 through I/O7 is written on
the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common
industry standard packages.
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key: X = don’t care, L = low, H = high.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +7.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 o C
Ambient temperature with VCC applied Tbias –55 +125 o C
DC current into outputs (low) IOUT –20mA
Truth table
CE WE OE
Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHL D
OUT Read (ICC)
LLX D
IN Write (ICC)
AS7C1025B
Aug/09, v. 1.4Alliance Memory Inc. P. 3 of 9
®
VIL min = -1.0V for pulse width less than 5ns
VIH max = VCC+2.0V for pulse width less than 5ns.
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
Input voltage VIH 2.2 – VCC + 0.5 V
VIL –0.5 – 0.8 V
Ambient operating temperature commercial TA0– 70
o C
industrial TA–40 – 85 o C
DC operating characteristics (over the operating range)1
Parameter Symbol Test conditions
-10 -12 -15 -20
UnitMin Max Min Max Min Max Min Max
Input leakage current | ILI | VCC = Max, VIN = GND to VCC –1–1–1–1µA
Output leakage
current | ILO | VCC = Max, CE = VIH,
Vout = GND to VCC
–1–1–1–1µA
Operating power
supply current ICC
VCC = Max
CE ≤ VIL, f = fMax, IOUT = 0 mA – 110 – 100 – 90 – 80 mA
Standby power supply
current1ISB
VCC = Max
CE ≥ VIH, f = fMax
–50–45–45–40mA
ISB1
VCC = Max
CE ≥ VCC–0.2 V,
VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V,
f = 0
–10 10 10 10 mA
Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 2.4 – 2.4 – 2.4 – V
Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2
Parameter Symbol Signals Te st co nditions Max Unit
Input capacitance CIN A,
CE
,
WE
,
OE
VIN = 0 V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0 V 7 pF
AS7C1025B
Aug/09, v. 1.4Alliance Memory Inc. P. 4 of 9
®
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE and OE controlled)3,6,8,9
Read cycle (over the operating range)3,9
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time tRC 10 - 12 – 15 – 20 – ns
Address access time tAA - 10 – 12 – 15 – 20 ns 3
Chip enable (
CE
) access time tACE - 10 – 12 – 15 – 20 ns 3
Output enable (
OE
) access time tOE -5–6–7–8 ns
Output hold from address change tOH 3 - 3 – 3 – 3 – ns 5
CE
low to output in low Z tCLZ 3 - 3 – 3 – 3 – ns 4, 5
CE
low to output in high Z tCHZ - 4 – 5 – 6 – 7 ns 4, 5
OE
low to output in low Z tOLZ 0 - 0 – 0 – 0 – ns 4, 5
OE
high to output in high Z tOHZ - 4 – 5 – 6 – 7 ns 4, 5
Power up time tPU 0 - 0 – 0 – 0 – ns 4, 5
Power down time tPD - 10 – 12 – 15 – 20 ns 4, 5
Undefined/don’t careFalling inputRising input
A
ddress
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE
t
OHZ
AS7C1025B
Aug/09, v. 1.4Alliance Memory Inc. P. 5 of 9
®
Write waveform 1 (WE controlled)10,11
Write cycle (over the operating range)11
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time tWC 10 - 12 – 15 – 20 – ns
Chip enable (
CE
) to write end tCW 8-9–10–12– ns
Address setup to write end tAW 8-9–10–10– ns
Address setup time tAS 0-0–0–0– ns
Write pulse width tWP 7 - 8 – 9 – 12 – ns
Write recovery time tWR 0-0–0–0– ns
Address hold from end of write tAH 0-0–0–0– ns
Data valid to write end tDW 5 - 6 – 8 – 10 – ns
Data hold time tDH 0 - 0 – 0 – 0 – ns 4, 5
Write enable to output in high Z tWZ - 5 – 6 – 7 – 8 ns 4, 5
Output active from write end tOW 1 - 1 – 1 – 2 – ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
AS7C1025B
Aug/09, v. 1.4Alliance Memory Inc. P. 6 of 9
®
Write waveform 2 (CE controlled)10,11
AC test conditions
Notes
1 During VCC power-up, a pull-up resistor to VCC on
CE
is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4t
CLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6
WE
is high for read cycle.
7
CE
and
OE
are low for read cycle.
8 Address is valid prior to or coincident with
CE
transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data valid
D
IN
t
WR
– Output load: see Figure B.
– Input pulse level: GND to 3.5 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
168
Ω
Thevenin equivalent:
D
OUT
+1.728 V
255
Ω
C
13
480
Ω
D
OUT
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.5 V
Figure A: Input pu lse
2 ns
AS7C1025B
Aug/09, v. 1.4Alliance Memory Inc. P. 7 of 9
®
Package dimensions
eD
E1
Pin 1
b
B
A1
A2 c
E
Seating
plane
E2
A
32-pin SOJ
300 mil/400 mil
Symbol
32-pin SOJ
300 mil 32-pin SOJ
400 mil
Min Max Min Max
A0.128 0.145 0.132 0.146
A1 0.025 - 0.025 -
A2 0.095 0.105 0.105 0.115
B0.026 0.032 0.026 0.032
b0.016 0.020 0.015 0.020
c0.007 0.010 0.007 0.013
D0.820 0.830 0.820 0.830
E0.255 0.275 0.354 0.378
E1 0.295 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
e0.050 BSC 0.050 BSC
AS7C1025B
Aug/09, v. 1.4Alliance Memory Inc. P. 8 of 9
®
Note: Add suffix ‘N’ to t he ab ove part number for LEAD FREE parts. (Ex AS7C1025B-10TJCN)
Ordering Codes
Package \
Access time Temperature 10 ns 12 ns 15 ns 20 ns
300-mil SOJ Commercial AS7C1025B-10TJC AS7C1025B-12TJC AS7C1025B-15TJC AS7C1025B-20TJC
Industrial AS7C1025B-10TJI AS7C1025B-12TJI AS7C1025B-15TJI AS7C1025B-20TJI
400-mil SOJ Commercial AS7C1025B-10JC AS7C1025B-12JC AS7C1025B-15JC AS7C1025B-20JC
Industrial AS7C1025B-10JI AS7C1025B-12JI AS7C1025B-15JI AS7C1025B-20JI
Part numbering system
AS7C 1025B –XX X X X
SRAM
prefix Device number Access time
Package:
TJ = SOJ 300 mil
J = SOJ 400 mil
Temperature range
C = commercial, 0° C to 70° C
I = industrial, -40° C to 85° C
N = LEAD FREE
PART
®
AS7C1025B
®
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS7C1025B
Document Version: v. 1.4
© Copyright 2009 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any
product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or
warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
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trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
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claims arising from such use.
