1
2
3
4
5
DCQ PACKAGE
RESET/FB
OUT
GND
IN
ENABLE
SOT223-5
(TOP VIEW)
1
2
3
4
8
7
6
5
OUT
FB
GND
NC
IN
GND
GND
ENABLE
D PACKAGE
(TOP VIEW)
NC − No internal connection
1
KTT PACKAGE
(TOP VIEW)
2 3 4 5
ENABLE
IN
GND
OUT
DDPAK
RESET/FB
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
www.ti.com
SLVS341E MAY 2002REVISED JUNE 2010
LOW INPUT VOLTAGE, 1-A LOW-DROPOUT LINEAR REGULATORS WITH SUPERVISOR
Check for Samples: TPS72501,TPS72515,TPS72516,TPS72518,TPS72525
1FEATURES DESCRIPTION
1-A Output Current The TPS725xx family of 1-A low-dropout (LDO) linear
regulators has fixed voltage options available that are
Available in 1.5-V, 1.6-V, 1.8-V, 2.5-V commonly used to power the latest DSPs, FPGAs,
Fixed-Output and Adjustable Versions and microcontrollers. An adjustable option ranging
(1.2-V to 5.5-V) from 1.22 V to 5.5 V is also available. The integrated
Input Voltage Down to 1.8 V supervisory circuitry provides an active low RESET
Low 170-mV Dropout Voltage at 1 A signal when the output falls out of regulation. The no
(TPS72525) capacitor/any capacitor feature allows the customer
to tailor output transient performance as needed.
Stable With Any Type/Value Output Capacitor Therefore, compared to other regulators capable of
Integrated Supervisor (SVS) With 50-ms providing the same output current, this family of
RESET Delay Time regulators can provide a stand-alone power supply
Low 210-µA Ground Current at Full Load solution or a post regulator for a switch mode power
supply.
(TPS72525)
Less than 1-µA Standby Current These regulators are ideal for higher current
applications. The family operates over a wide range
±2% Output Voltage Tolerance Over Line, of input voltages (1.8 V to 6 V) and has very low
Load, and Temperature (-40°C to 125°C) dropout (170 mV at 1-A).
Integrated UVLO Ground current is typically 210 µA at full load and
Thermal and Overcurrent Protection drops to less than 80 µA at no load. Standby current
5-Lead SOT223-5 or DDPAK and 8-Pin SOP is less than 1 µA.
(TPS72501 only) Surface Mount Package Each regulator option is available in either a
SOT223-5, D (TPS72501 only), or DDPAK package.
APPLICATIONS With a low input voltage and properly heatsinked
PCI Cards package, the regulator dissipates more power and
Modem Banks achieves higher efficiencies than similar regulators
Telecom Boards requiring 2.5 V or more minimum input voltage and
higher quiescent currents. These features make it a
DSP, FPGA, and Microprocessor Power viable power supply solution for portable,
Supplies battery-powered equipment.
Portable, Battery-Powered Applications
NOTE: TPS72501 replaces RESET with FB. Tab is GND for the DCK and KTT packages.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341E MAY 2002REVISED JUNE 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
Although an output capacitor is not required for stability, transient response and output noise are improved with a
10-µF output capacitor.
Unlike some regulators that have a minimum current requirement, the TPS725 family is stable with no output
load current. The low noise capability of this family, coupled with its high current operation and ease of power
dissipation, make it ideal for telecom boards, modem banks, and other noise-sensitive applications.
ORDERING INFORMATION
TJVOLTAGE(1) SOT223-5(2) SYMBOL DDPAK(3) D(4) SYMBOL
Adjustable (1.2 V to 5 V) TPS72501DCQ PS72501 TPS72501KTT TPS72501D TPS72501
1.5 V TPS72515DCQ PS72515 TPS72515KTT TPS72515
-40°C to 1.6 V TPS72516DCQ PS72516 TPS72516KTT TPS72516
125°C 1.8 V TPS72518DCQ PS72518 TPS72518KTT TPS72518
2.5 V TPS72525DCQ PS72525 TPS72525KTT TPS72525
(1) Other voltage options are available upon request from the manufacturer.
(2) To order a taped and reeled part, add the suffix Rto the part number (e.g., TPS72501DCQR).
(3) To order a 50-piece reel, add the suffix T(e.g., TPS72501KTTT); to order a 500-piece reel, add the suffix R(e.g., TPS72501KTTR).
(4) To order a taped and reeled part, add the suffix Ror T(2500 or 500) to the part number (e.g. TPS72501DR)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Input voltage, VI(2) -0.3 to 7 V
Voltage range at EN, FB -0.3 to VI+ 0.3 V
Voltage on OUT, RESET 6 V
ESD rating, HBM 2 kV
Continuous total power dissipation See Dissipation Ratings Table
Operating junction temperature range, TJ-50 to 150 °C
Maximum junction temperature range, TJ150 °C
Storage temperature, Tstg -65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Input voltage, VI(1) 1.8 6 V
Continuous output current, IO0 1 A
Operating junction temperature, TJ-40 125 °C
(1) Minimum VI= VO(nom) + VDO.
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Line regulation (mV) +ǒ%ńVǓ VOǒ5.5 V *VIminǓ
100 1000
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
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SLVS341E MAY 2002REVISED JUNE 2010
PACKAGE DISSIPATION RATINGS
PACKAGE BOARD RqJC RqJA
DDPAK High K(1) 2 °C/W 23 °C/W
SOT223 Low K(2) 15 °C/W 53 °C/W
D-8 High K(1) 39.4 °C/W 55 °C/W
(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2) The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), two-layer board with 2 ounce
copper traces on top of the board.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range VI= VO(typ) + 1 V, IO= 1 mA, EN = IN, Co= 1 µF, Ci= 1 µF (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bandgap voltage reference 1.177 1.220 1.263 V
TPS72501 0 µA < IO< 1 A(1) 1.22 V VO5.5 V 0.965 VO1.035 VO
Adjustable TJ= 25°C 1.5
TPS72515 0 µA< IO< 1 A 1.8 V VI5.5 V 1.47 1.53
TJ= 25°C 1.6
TPS72516
VOOutput voltage V
0 µA < IO< 1 A 2.6 V VI5.5 V 1.568 1.632
TJ= 25°C 1.8
TPS72518 0 µA < IO< 1 A 2.8 V VI5.5 V 1.764 1.836
TJ= 25°C 2.5
TPS72525 0 µA < IO< 1 A 3.5 V VI5.5 V 2.45 2.55
IO= 0 µA 75 120
I Ground current µA
IO= 1 A 210 300
EN < 0.4 V TJ= 25°C 0.2
Standby current µA
EN < 0.4 V 1
BW = 200 Hz to 100 kHz, Co= 10 µF, IO= 1
VnOutput noise voltage 150 µV
TJ= 25°C mA
PSRR Ripple rejection f = 1 kHz, Co= 10 µF TJ= 25°C 60 dB
Current limit(2) 1.1 1.6 2.3 A
Output voltage line regulation VO+ 1 V < VI5.5 V -0.15 0.02 0.15 %/V
(ΔVO/VO)(3)
Output voltage load regulation 0 µA < IO< 1 A -0.25 0.05 0.25 %/A
VIH EN high level input(2) 1.3 V
VIL EN low level input(2) -0.2 0.4
IIEN input current EN = 0 V or VI0.01 100 nA
I(FB) Feedback current TPS72501 V(FB) = 1.22 -100 100 nA
UVLO threshold VCC rising 1.45 1.57 1.70 V
UVLO hysteresis TJ= 25°C, VCC rising 50 mV
UVLO deglitch TJ= 25°C, VCC rising 10 µs
UVLO delay TJ= 25°C, VCC rising 100 µs
(1) Minimum IN operating voltage used for testing is VO(typ) + 1 V.
(2) Test condition includes output voltage VO= VO- 15% and pulse duration = 10 ms.
(3) VImin = (VO+ 1) or 1.8 V whichever is greater.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341E MAY 2002REVISED JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range VI= VO(typ) + 1 V, IO= 1 mA, EN = IN, Co= 1 µF, Ci= 1 µF (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO= 1 A TJ= 25°C 170
TPS72525 (4) IO= 1 A 280
VDO Dropout voltage mV
IO= 1 A TJ= 25°C 210
TPS72518 (5) IO= 1 A 320
Minimum input voltage for valid 1.3 V
RESET
Trip threshold voltage 90 93 96 %VO
Hysteresis voltage 10 mV
RESET t(RESET) delay time 25 50 75 ms
Rising edge deglitch 10 µs
Output low voltage (at 700 µA) -0.3 0.4 V
Leakage current 100 nA
(4) Dropout voltage is defined as the differential voltage between VOand VIwhen VOdrops 100 mV below the value measured with
VI= VO+ 1 V.
(5) Dropout voltage is defined as the differential voltage between VOand VIwhen VOdrops 100 mV below the value measured with
VI= VO+ 1 V.
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Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
TPS72501
OUT
IN
FB
GND
EN
Vref
Current
Limit/Thermal
Protection
1.220
TPS72515/16/18/25
OUT
IN
GND
EN
Vref
Current
Limit/Thermal
Protection
0.93 × Vref
Deglitch
and
Delay
RESET
1.220
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
www.ti.com
SLVS341E MAY 2002REVISED JUNE 2010
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
TERMINAL FUNCTIONS
TERMINAL
NO.D I/O DESCRIPTION
NO.
NAME CQ &
DKTT
ENABLE 5 1 I Enable input
FB 2 Feedback
GND 3, 6, 7 3 Ground
IN 8 2 I Input supply voltage
RESET/FB 5 O/I This terminal is the feedback point for the adjustable option TPS72501. For all other options, this
terminal is the RESET output terminal. When used with a pullup resistor, this open-drain output
provides the active low RESET signal when the regulator output voltage drops more than 5% below
its nominal output voltage. The RESET delay time is typically 50 ms.
NC 4 No connection
OUT 1 4 O Regulated output voltage
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
NOTES:A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for
semiconductor symbology.
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
IN
VRES
(see Note A) VRES
t
t
t
OUT
Threshold
Voltage
RESET
Output 50 ms
Delay 50 ms
Delay
Output
Undefined
Output
Undefined
VIT+(see Note B)
VIT–
(see Note B)
VIT+(see Note B)
B. VIT –T rip voltage is typically 7% lower than the output voltage (93%VO) VIT to VIT+ is the hysteresis voltage.
VIT–
(see Note B)
1.785
1.795
1.805
−40−25−10 5 20 35 50 65 80 95 110 125
1.790
1.800
VI = 2.8 V
Co = 1 µF
TJ − Junction Temperature − °C
− Output Voltage − V
VO
IO = 1 A
IO = 0 mA
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341E MAY 2002REVISED JUNE 2010
www.ti.com
RESET TIMING DIAGRAM
TYPICAL CHARACTERISTICS
TPS72518 TPS72518 TPS72518
OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT
vs vs vs
OUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
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0
50
100
150
200
250
300
0 0.2 0.4 0.6 0.8 1
TJ = 125°C
TJ = 25°C
TJ = −40°C
− Dropout Voltage − mV
IO − Output Current − A
VDO
VO = 2.5 V (nom)
−40−25−10 5 20 35 50 65 80 95 110 125
IO = 1 A
IO = 10 mA
VO = 1.7 V
Co = 1 µF
TJ − Junction Temperature − °C
− Dropout Voltage − mV
VDO
0
50
100
150
200
250
300
VO = 2.8 V
Co = 10 µF
Ci = 1 µF
− Output Current − AOutput Voltage − mV
VO
IO
− Change in
t − Time − µs
0 5 10 15 20 25 30 35 40 45 50
0
0.5
1
−100
0
100
t − Time − µs
100
−100
0 50 100 150 200 250 300
2.8
350 400 450 500
3.8
0
IO = 1 A
Co = 10 µF
− Input Voltage − V− Output Voltage − mVVOVI
1.5
2
2.5
3
3.5
4
4.5
1.5 2 2.5 3 3.5 4 4.5
TJ = 25°C
TJ = 125°C
TJ = −40°C
− Minimum Required Input Voltage − V
VO − Output Voltage − V
VI
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
www.ti.com
SLVS341E MAY 2002REVISED JUNE 2010
TYPICAL CHARACTERISTICS (continued)
TPS72518 TPS72525 TPS72518
GROUND CURRENT DC DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs vs
OUTPUT CURRENT OUTPUT CURRENT JUNCTION TEMPERATURE
Figure 4. Figure 5. Figure 6.
MINIMUM REQUIRED
INPUT VOLTAGE
vs TPS72518 TPS72518
OUTPUT VOLTAGE LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 7. Figure 8. Figure 9.
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Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
IO
t − Time − µs
0 15105 20 25 3530 40 45 50
− Output Current − A
VI = 2.8 V
Co = 1 µF
CI = 1 µF
1
0.5
0
−100
100
0
Output Voltage − mV
VO
− Change in
160
2
VO
t − Time − µs
0 604020 80 100 140120 180 200
− Output Voltage − V
VI = 2.8 V
IO = 1 A
Co = 10 µF
Enable Voltage − V
1
1
0
0
1.5
2
3
0.5
t − Time − µs
1
0 100 200 300 400 500 600
− Input Voltage − V
3
700 800 900 1000
5
0
− Output Voltage − VVOVI
4
2
VO
VI
RL = 1.8
Co = 1 µF
Ci = 1 µF
0
0.5
1
1.5
2
2.5
3
3.5
10 100 1 k 10 k 100 k
f − Frequency − Hz
IO = 1 mA
VI = 2.8 V
Co = 10 µF
IO = 1 A
V/ HzOutput Spectral Noise Density − µ
50
30
20
010 100 1 k 10 k
Ripple Rejection − dB
70
90
f − Frequency − Hz
100
100 k 1 M
80
60
40
10
10 µF / 1mA
10 µF / 1 A
VI= 2.8 V,
VO = 1.8 V,
CO = 10 µF
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
1.5 2 2.5 3 3.5 4 4.5 5 5.5
TJ = 25°C
VI − Input voltage − V
Current Limit − A
TJ = −40°C
TJ = 125°C
0
50
100
150
200
250
300
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VI − Input Voltage − V
− Dropout Voltage − mV
VDO
TJ = 25°C
TJ = −40°C
TJ = 125°C
0
100
200
300
400
500
600
0123456
I = 0 A
VI − Input Voltage − V
Ground Current − Aµ
I = 1 A
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341E MAY 2002REVISED JUNE 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TPS72518 OUTPUT VOLTAGE,
ENABLE VOLTAGE
TPS72518 vs TPS72518
LOAD TRASIENT RESPONSE TIME (START-UP) POWER UP/POWER DOWN
Figure 10. Figure 11. Figure 12.
TPS72518 OUTPUT SPECTRAL TPS72518
NOISE DENSITY RIPPLE REJECTION CURRENT LIMIT
vs vs vs
FREQUENCY FREQUENCY INPUT VOLTAGE
Figure 13. Figure 14. Figure 15.
TPS72515 GROUND CURRENT DROPOUT VOLTAGE
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 16. Figure 17.
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VO+Vref ǒ1)R1
R2Ǔ
R1 +ǒVO
Vref *1Ǔ R2
VO
VIOUT
FB
R1
R2
GND
EN
IN
TPS72501
1mF
CO
V =1.22V ´
O1+ R1
R2
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
www.ti.com
SLVS341E MAY 2002REVISED JUNE 2010
APPLICATION INFORMATION
The TPS725xx family of low-dropout (LDO) regulators has numerous features that make it applicable to a wide
range of applications. The family operates with very low input voltage (1.8 V) and low dropout voltage (typically
200 mV at full load), making it an efficient stand-alone power supply or post regulator for battery or switch mode
power supplies. Both the active low RESET and 1-A output current make the TPS725xx family ideal for powering
processor and FPGA supplies. The TPS725xx family also has low output noise (typically 150 µVRMS with 10-µF
output capacitor), making it ideal for use in telecom equipment.
External Capacitor Requirements
A 1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS725xx, is required for stability. To improve transient response, noise rejection, and ripple rejection, an
additional 10-µF or larger, low ESR capacitor is recommended. A higher-value, low ESR input capacitor may be
necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the
power source, especially if the minimum input voltage of 1.8 V is used.
Although an output capacitor is not required for stability, transient response and output noise are improved with a
10-µF output capacitor.
Programming the TPS72501 Adjustable LDO Regulator
The output voltage of the TPS72501 adjustable regulator is programmed using an external resistor divider as
shown in Figure 18. The output voltage is calculated using:
(1)
Where:
VFB = VREF = 1.22 V typical (see the electrical characteristics for VREF range)
Resistors R1 and R2 should be chosen for approximately 10-µA divider current. Lower value resistors offer no
inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase
the output voltage error. The recommended design procedure is to choose R2 = 120 kto set the divider current
at 10 µA and then calculate R1 using:
(2)
Figure 18. TPS72501 Adjustable Typical Application Diagram
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VO
VIOUT
RESET
10kW
GND
EN
IN
TPS725xx
1mF
CO
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341E MAY 2002REVISED JUNE 2010
www.ti.com
Figure 19. TPS72501 Fixed Output Typical Application Diagram
Table 1. Output Voltage Programming Guide (Standard 1% Resistor Values)
PROGRAM VOLTAGE R1 (kΩ) R2 (kΩ) ACTUAL VOLTAGE
1.8 V 56.2 118 1.801
2.5 V 127 121 2.5
3.3 V 196 115 3.299
3.6 V 205 105 3.602
Regulator Protection
The TPS725xx pass element has a built-in back diode that safely conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be
appropriate.
The TPS725xx also features internal current limiting and thermal protection. During normal operation, the
TPS725xx limits output current to approximately 1.6 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the
device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below
145°C, regulator operation resumes.
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PDmax +ǒVI(avg) *VO(avg)Ǔ IO(avg) )VI(avg)x I(Q)
A
B
C
TJ
A
RθJC
TC
B
RθCS
TA
C
RθSA
(a) (b)
DDPAK Package
SOT223 Package
CIRCUIT BOARD COPPER AREA
B
A
C
TJ+TA)PDmax x ǒRθJC )RθCS )RθSAǓ
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
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SLVS341E MAY 2002REVISED JUNE 2010
THERMAL INFORMATION
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it
dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax)
above which normal operation is not assured. A system designer must design the operating environment so that
the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two
main environmental variables that a designer can use to improve thermal performance are air flow and external
heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment
for a linear regulator that is operating at a specific power level.
In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as:
(3)
Where:
VI(avg) is the average input voltage.
VO(avg) is the average output voltage.
IO(avg) is the average output current.
I(Q) is the quiescent current.
For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;
therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the
ambient temperature (TA) and the increase in temperature due to the regulator's power dissipation. The
temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal
resistances between the junction and the case (RqJC), the case to heatsink (RqCS), and the heatsink to ambient
(RqSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the
device, the more surface area available for power dissipation and the lower the object's thermal resistance.
Figure 20 illustrates these thermal resistances for (a) a SOT223 package mounted in a JEDEC low-K board, and
(b) a DDPAK package mounted on a JEDEC high-K board.
Figure 20. Thermal Resistances
Equation 4 summarizes the computation:
(4)
The RqJC is specific to each regulator as determined by its package, lead frame, and die size provided in the
regulator's data sheet. The RqSA is a function of the type and size of heatsink. For example, black body radiator
type heatsinks can have RqCS values ranging from 5°C/W for very large heatsinks to 50°C/W for very small
heatsinks. The RqCS is a function of how the package is attached to the heatsink. For example, if a thermal
compound is used to attach a heatsink to a SOT223 package, RqCSof 1°C/W is reasonable.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
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TJ+TA)PDmax x RθJA
RθJA +TJ–TA
PDmax
PDmax +(5*2.5)V x 1 A +2.5 W
RθJAmax +(125 *55)°Cń2.5 W +28°CńW
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341E MAY 2002REVISED JUNE 2010
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Even if no external black body radiator type heatsink is attached to the package, the board on which the
regulator is mounted provides some heatsinking through the pin solder connections. Some packages, like the
DDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board's ground plane
for additional heatsinking to improve their thermal performance. Computer-aided thermal modeling can be used
to compute very accurate approximations of an integrated circuit's thermal performance in different operating
environments (e.g., different types of circuit boards, different types and sizes of heatsinks, different air flows,
etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between
junction and ambient (RqJA). This RqJAis valid only for the specific operating environment used in the computer
model.
Equation 4 simplifies into Equation 5:
(5)
Rearranging Equation 5 gives Equation 6:
(6)
Using Equation 5 and the computer model generated curves shown in Figure 21 and Figure 24, a designer can
quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power
dissipation, and operating environment.
DDPAK Power Dissipation
The DDPAK package provides an effective means of managing power dissipation in surface mount applications.
The DDPAK package dimensions are provided in the Mechanical Data section at the end of the data sheet. The
addition of a copper plane directly underneath the DDPAK package enhances the thermal performance of the
package.
To illustrate, the TPS72525 in a DDPAK package was chosen. For this example, the average input voltage is 5
V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, the air flow is
150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current,
the maximum average power is:
(7)
Substituting TJmax for TJinto Equation 6 gives Equation 8:
(8)
From Figure 21, DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be 1 cm2for
the part to dissipate 2.5 W. The operating environment used in the computer model to construct Figure 21
consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The
package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane.
Figure 22 shows the side view of the operating environment used in the computer model.
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Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
15
20
25
30
35
40
0.1 1 10 100
Copper Heatsink Area − cm2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
150 LFM
250 LFM
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
2 oz. Copper Solder Pad
with 25 Thermal Vias
Thermal Vias, 0.3 mm
Diameter, 1,5 mm Pitch
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
www.ti.com
SLVS341E MAY 2002REVISED JUNE 2010
Figure 21. DDPAK Thermal Resistance vs Copper Heatsink Area
Figure 22. DDPAK Thermal Resistance
From the data in Figure 23 and rearranging Equation 6, the maximum power dissipation for a different ground
plane area and a specific ambient temperature can be computed.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
− Maximum Junction Temperature − 125
TJM C
°
1
2
3
4
5
0.1 1 10 100
− Maximum Power Dissipation − W
PD
Copper Heatsink Area − cm2
TA = 55°C
No Air Flow
150 LFM
250 LFM
PDmax +(3.3 *2.5)V x 1 A +800 mW
RθJAmax +(125 *55)°Cń800 mW +87.5°CńW
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341E MAY 2002REVISED JUNE 2010
www.ti.com
Figure 23. Maximum Power Dissipation vs Copper Heatsink Area
SOT223 Power Dissipation
The SOT223 package provides an effective means of managing power dissipation in surface mount applications.
The SOT223 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The
addition of a copper plane directly underneath the SOT223 package enhances the thermal performance of the
package.
To illustrate, the TPS72525 in a SOT223 package was chosen. For this example, the average input voltage is
3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, no air flow is
present, and the operating environment is the same as documented below. Neglecting the quiescent current, the
maximum average power is:
(9)
Substituting TJmax for TJinto Equation 6 gives Equation 10:
(10)
From Figure 24, RΘJA vs PCB Copper Area, the ground plane needs to be 0.55 in2for the part to dissipate 800
mW. The operating environment used to construct Figure 24 consisted of a board with 1 oz. copper planes. The
package is soldered to a 1 oz. copper pad on the top of the board. The pad is tied through thermal vias to the 1
oz. ground plane.
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Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
0
100
120
140
160
180
PCB Copper Area − in2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
80
60
40
20
0.1 1 10
0
1
2
3
6
0 25 50 75 100 150
− Maximum Power Dissipation − W
PD
125
TA = 25°C
TA − Ambient Temperature − °C
4
5
4 in2 PCB Area
0.5 in2 PCB Area
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
www.ti.com
SLVS341E MAY 2002REVISED JUNE 2010
Figure 24. SOT223 Thermal Resistance vs PCB AREA
From the data in Figure 24 and rearranging Equation 6, the maximum power dissipation for a different ground
plane area and a specific ambient temperature can be computed (as shown in Figure 25).
Figure 25. SOT223 Power Dissipation
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341E MAY 2002REVISED JUNE 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2004) to Revision E Page
Deleted Figure 14, Output Impedance vs Frequency ........................................................................................................... 8
Updated Figure 18 ................................................................................................................................................................ 9
Added Figure 19 ................................................................................................................................................................. 10
Added Table 1,Output Voltage Programming Guide ......................................................................................................... 10
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Product Folder Link(s): TPS72501 TPS72515 TPS72516 TPS72518 TPS72525
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TPS72501DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS72501
TPS72501DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS72501
TPS72501DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS72501
TPS72501DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS72501
TPS72501DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
72501
TPS72501DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
72501
TPS72501DT ACTIVE SOIC D 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
72501
TPS72501DTG4 ACTIVE SOIC D 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
72501
TPS72501KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI -40 to 125
TPS72501KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS
72501
TPS72501KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS
72501
TPS72501KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS
72501
TPS72501KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS
72501
TPS72515DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS72515
TPS72515DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS72515
TPS72515DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS72515
TPS72515DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS72515