TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C www.ti.com SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 Dual Channel, Current-Limited, Power-Distribution Switches Check for Samples: TPS2062C, TPS2066C, TPS2060C, TPS2064C, TPS2002C, TPS2003C FEATURES 1 * * * * * * * * * 2 * * * Dual Power Switch Family Rated Currents of 1 A / 1.5 A / 2 A Accurate 20% Current-limit Tolerance Fast Overcurrent Response - 2 s (Typical) 70-m (Typical) High-Side N-Channel MOSFET Operating Range: 4.5 V to 5.5 V Deglitched Fault Reporting (FLTx) Output Discharge When Disabled Reverse Current Blocking Built-in Softstart Pin for Pin with Existing TI Switch Portfolio Ambient Temperature Range: -40C to 85C APPLICATIONS * * * * USB Ports/Hubs, Laptops, Desktops High-Definition Digital TVs Set Top Boxes Short-Circuit Protection DESCRIPTION The TPS20xxC dual power-distribution switch family is intended for applications such as USB where heavy capacitive loads and short-circuits may be encountered. This family offers multiple devices with fixed current-limit thresholds for applications between 1 A and 2 A. The TPS20xxC dual family limits the output current to a safe level by operating in a constant-current mode when the output load exceeds the current-limit threshold. This provides a predictable fault current under all conditions. The fast overcurrent response time eases the burden on the main 5 V supply to provide regulated power when the output is shorted. The power-switch rise and fall times are controlled to minimize current surges during turnon and turn-off. DGN (Top View) GND IN EN 1 or EN 1 EN 2 or EN 2 1 2 3 4 PAD 8 7 6 5 DRC (Top View) D (Top View) FLT 1 OUT 1 OUT 2 FLT 2 1 2 3 4 GND IN EN 1 or EN 1 EN 2 or EN 2 VIN 8 7 6 5 GND IN IN EN 1 or EN 1 EN 2 or EN 2 FLT 1 OUT 1 OUT 2 FLT 2 1 2 3 4 5 PAD 10 9 8 7 6 FLT 1 OUT 1 OUT 2 NC FLT 2 0.1 mF IN RFLT1 RFLT2 10 kW 10 kW FLT1 FLT2 Fault Signals OUT 1 VOUT1 OUT 2 VOUT2 150 mF x 2 GND Pad EN1 or EN1 EN2 or EN2 Control Signals Figure 1. TYPICAL APPLICATION Table 1. Devices (1) RATED CURRENT DEVICES 1A (1) STATUS MSOP-8 (PowerPadTM) SON -10 SOIC-8 TPS2062C/66C Active / Active - Preview / Preview 1.5 A TPS2060C/64C Active / Active - - 2A TPS2002C/03C - Preview / Preview - For more details, see the DEVICE INFORMATION table 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2012, Texas Instruments Incorporated TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION (1) (2) MAXIMUM OPERATING CURRENT (1) (2) (3) PACKAGE DEVICES (3) ENABLE OUTPUT DISCHARGE BASE PART NUMBER 1 Low Y TPS2062C - VRBQ 1 High Y TPS2066C - VRDQ 1.5 Low Y TPS2060C - - VRAQ 1.5 High Y TPS2064C - - VRCQ 2 Low Y TPS2002C - - VREQ 2 High Y TPS2003C - - VRFQ SOIC-8 (D) MSOP-8 SON-10 (DGN) (DRC) PowerPADTM MARKING For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package code for MSOP-8 is "DGN" and for SON is "DRC". "-" indicates the device is not available in this package. ABSOLUTE MAXIMUM RATINGS (1) (2) VALUE Voltage range on IN, OUTx, ENx or ENx, FLTx (3) MAX -0.3 6 V -6 6 V Voltage range from IN to OUT Maximum junction temperature, TJ Internally Limited Human Body Model ESD 2 Charged Device Model IEC 61000-4-2, Contact / Air (4) (1) (2) (3) (4) UNIT MIN C kV 500 V 8 / 15 kV Absolute maximum ratings apply over recommended junction temperature range. All voltages are with respect to GND unless otherwise noted. See INPUT AND OUTPUT CAPACITANCE section. VOUT was surged on a PCB with input and output bypassing per Figure 1 (except input capacitor was 22 F) with no device failure. THERMAL INFORMATION THERMAL METRIC (1) (2) D DGN DRC 8 PINS 8 PINS 10 PINS JA Junction-to-ambient thermal resistance 129.9 57.2 45.4 JCtop Junction-to-case (top) thermal resistance 83.5 110.5 58 JB Junction-to-board thermal resistance 70.4 60.7 21.1 JT Junction-to-top characterization parameter 36.6 7.8 1.9 JB Junction-to-board characterization parameter 66.9 24 21.3 JCbot Junction-to-case (bottom) thermal resistance n/a 14.3 9.1 (1) (2) 2 UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C www.ti.com SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 RECOMMENDED OPERATING CONDITIONS MIN VIN Input voltage, IN VEnable Input voltage, ENx or ENx IOUTx Continuous ouput current, OUTx TJ Operating junction temperature IFLTx Sink current into FLTx NOM MAX 4.5 5.5 0 5.5 TPS2062C/66C 1 TPS2060C/64C 1.5 TPS2002C/03C 2 UNIT V A -40 125 C 0 5 mA ELECTRICAL CHARACTERISTICS (1) (2) TJ = TA = 25CVIN = 5 V, VENx = VIN or VENx = 0V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SWITCH rDS(on) On-resistance TPS2062C/66C (1 A) DGN 70 84 TPS2062C/66C (1 A), -40C (TJ, TA ) 85C DGN 70 95 TPS2062C/66C (1 A) D 84 TPS2062C/66C (1 A), -40C (TJ, TA ) 85C D 84 m TPS2060C/64C (1.5 A) 70 84 TPS2060C/64C (1.5 A), -40C (TJ, TA ) 85C 70 95 TPS2002C/03C (2 A) 70 84 TPS2002C/03C (2 A), -40C (TJ, TA ) 85C 70 95 CURRENT LIMIT IOS tIOS Current limit, See Figure 7 Short-circuit response time TPS2062C/66C (1 A) 1.28 1.61 1.94 TPS2060C/64C (1.5 A) 1.83 2.29 2.75 TPS2002C/03C (2 A) 2.43 2.96 3.49 VIN = 5 V (see Figure 6), One-half full load R(SHORT) = 50 m, Measure from application to when current falls below 120% of final value 2 A s SUPPLY CURRENT ISD Supply current, device disabled I(OUTx) = 0 mA 0.01 1 IS1E Supply current, single switch enabled I(OUTx) = 0 mA 60 75 IS2E Supply current, both switches enabled I(OUTx) = 0 mA 100 120 ILKG Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured IOUTx 0.15 1 470 600 A OUTPUT DISCHARGE RPD (1) (2) Output pull-down resistance (2) VIN = V(OUTx) = 5 V, disabled 400 Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty. Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C 3 TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS -40C (TJ = TA) 125C, 4.5 V VIN 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A, typical values are at 5 V and 25C (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX DGN 70 112 D 84 135 TPS2060C/64C (1.5 A) 70 112 TPS2002C/03C (2 A) 70 112 UNIT POWER SWITCH TPS2062C/66C (1 A) rDS(on) On-resistance m ENABLE INPUT (ENx or ENx) VIH ENx (ENx), High-level input voltage VIL ENx (ENx), Low-level input Voltage ton 4.5 V VIN 5.5 V 2 0.8 Hysteresis VIN = 5 V Leakage current VENx = 5.5 V or 0 V, VENx = 0 V or 5.5 V Turn-on time VIN = 5 V, CL = 1 F, RL = 100 , ENx or ENx , See Figure 4, Figure 5, and Figure 2 0.14 -1 0 1 1.4 1.9 2.4 Turn-off time 1.95 2.60 3.25 0.58 0.82 1.15 1A / 1.5A / 2A Rated 0.33 0.47 0.66 TPS2062C/66C (1 A) 1.12 1.61 2.10 TPS2060C/64C (1.5 A) 1.72 2.29 2.86 TPS2002C/03C (2 A) 2.22 2.96 3.7 VIN = 5 V, CL = 1 F, RL = 100 , ENx or EN , See Figure 4, Figure 5, and Figure 2 ms 1 A / 1.5 A / 2 A Rated tr Rise time, output tf Fall time, output A ms 1 A / 1.5 A / 2 A Rated toff V CL = 1 F, RL = 100 , see Figure 3 1A / 1.5 A / 2 A Rated CL = 1 F, RL = 100 , see Figure 3 ms ms CURRENT LIMIT IOS Current-limit, See Figure 7 Short-circuit response time (2) tIOS VIN = 5 V (see Figure 6), One-half full load R(SHORT) = 50 m, measure from application to when current falls below 120% of final value 2 A s SUPPLY CURRENT ISD Supply current, switch disabled Standard conditions, I(OUTx) = 0 mA IS1E Supply current, single switch enabled 0.01 10 Standard conditions, I(OUTx) = 0 mA 90 IS2E Supply current, both switches enabled Standard conditions, I(OUTx) = 0 mA 150 ILKG Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured I(OUTx) A 0.20 UNDERVOLTAGE LOCKOUT UVLO Low-level input voltage, IN VIN rising 3.4 Hysteresis, IN (2) 4.0 0.14 V V FLTx (1) (2) 4 Output low voltage, FLTx I(FLTx) = 1 mA Off-state leakage V(FLTx) = 5.5 V FLTx deglitch FLTx overcurrent assertion/deassertion 0.2 7 10 V 1 A 13 ms Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C www.ti.com SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (continued) -40C (TJ = TA) 125C, 4.5 V VIN 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A, typical values are at 5 V and 25C (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX VIN = 5 V, VOUT = 5 V, disabled 300 470 800 VIN = 4 V, VOUT = 5 V, disabled 350 560 1200 In current limit 135 Not in current limit 155 UNIT OUTPUT DISCHARGE RPD Output pull-down resistance (3) THERMAL SHUTDOWN Junction thermal shutdown threshold C Hysteresis (3) (3) 20 C These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty. OUTx RL CL 90% tr tf VOUT Figure 2. Output Rise / Fall Test Load 10% Figure 3. Power-On and Off Timing SPACER VEN VEN 50% 50% 50% 50% toff ton toff 90% ton 90% VOUT VOUT 10% 10% Figure 4. Enable Timing, Active High Enable Figure 5. Enable Timing, Active Low Enable SPACER VIN Decreasing Load Slope = -rDS(on) VOUT Resistance 120% x IOS IOUT IOS 0V 0A 0A tIOS Figure 6. Output Short Circuit Parameters SPACER Copyright (c) 2011-2012, Texas Instruments Incorporated IOUT IOS Figure 7. Output Characteristic Showing Current Limit Submit Documentation Feedback Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C 5 TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM IN CS OUT1 Current Sense Charge Pump Disable+UVLO Current Limit EN1 or Driver EN1 FLT1 UVLO OTSD Thermal Sense UVLO 10-ms Deglitch CS OUT2 Current Sense Disable+UVLO Current Limit EN2 or EN2 Driver UVLO FLT2 OTSD GND 6 Submit Documentation Feedback Thermal Sense 10-ms Deglitch Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C www.ti.com SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 DEVICE INFORMATION PIN FUNCTIONS - MSOP-8 PACKAGES NAME TPS2066C/64C TPS2062C/60C I/O DESCRIPTION GND 1 1 Pwr Ground connection IN 2 2 I Input voltage and power-switch drain; connect a 0.1 F or greater ceramic capacitor from IN to GND close to the IC EN1 3 - I Enable input channel 1, logic high turns on power switch EN1 - 3 I Enable input channel 1, logic low turns on power switch EN2 4 - I Enable input channel 2, logic high turns on power switch EN2 - 4 I Enable input channel 2, logic low turns on power switch FLT2 5 5 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on channel 2 OUT2 6 6 O Power-switch output channel 2, connected to load OUT1 7 7 O Power-switch output channel 1, connected to load FLT1 8 8 O Active-low open-drain output, asserted during over-current, or overtemperature conditions on channel 1 PAD PAD Pwr PowerPADTM Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect PAD to GND plane as a heatsink. PIN FUNCTIONS - SOIC-8 PACKAGES NAME TPS2066C TPS2062C I/O DESCRIPTION GND 1 1 Pwr Ground connection IN 2 2 I Input voltage and power-switch drain; connect a 0.1 F or greater ceramic capacitor from IN to GND close to the IC EN1 3 - I Enable input channel 1, logic high turns on power switch EN1 - 3 I Enable input channel 1, logic low turns on power switch EN2 4 - I Enable input channel 2, logic high turns on power switch EN2 - 4 I Enable input channel 2, logic low turns on power switch FLT2 5 5 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on channel 2 OUT2 6 6 O Power-switch output channel 2, connected to load OUT1 7 7 O Power-switch output channel 1, connected to load FLT1 8 8 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on channel 1 PIN FUNCTIONS - SON-10 PACKAGES NAME TPS2003C TPS2002C I/O 1 1 Pwr 2, 3 2, 3 I Input voltage and power-switch drain; connect a 0.1 F or greater ceramic capacitor from IN to GND close to the IC EN1 4 - I Enable input channel 1, logic high turns on power switch EN1 - 4 I Enable input channel 1, logic low turns on power switch EN2 5 - I Enable input channel 2, logic high turns on power switch EN2 - 5 I Enable input channel 2, logic low turns on power switch FLT2 6 6 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on channel 2 NC 7 7 OUT2 8 8 O Power-switch output channel 2, connect to load OUT1 9 9 O Power-switch output channel 1, connect to load FLT1 10 10 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on channel 1 PAD PAD Pwr Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect PAD to GND plane as a heatsink. GND IN PowerPADTM DESCRIPTION Ground connection No connect - leave floating. Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C 7 TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS IOUT1 IOUT2 0.1 F VIN IN VOUT1 VOUT2 OUT1 OUT2 3.01 k 3.01 k RLoad1 FLT1 GND FLT2 Pad EN1 or EN1 EN2 or EN2 Fault Signals Control Signals CL1 RLoad2 CL2 Figure 8. Test Circuit for System Operation in Typical Characteristics Section 8 8 VIN = 5 V, CLx = 1 F, RLoadx = 5 , TPS2062C 6 4 ENx (V) ENx (V) 6 VIN = 5 V, CLx = 1 F, RLoadx = 5 , TPS2062C ENx OUTx 2 4 OUTx 2 ENx 0 0 -2 -3m -2m -1m 0 1m 2m Time (s) 3m 4m -2 -3m 5m Figure 9. TPS2062C Turn on Delay and Rise Time With 1-F Load 8 -1m 0 1m 2m Time (s) 3m 4m 5m Figure 10. TPS2062C Turn off Delay and Fall Time With 1-F Load 8 VIN = 5 V, CLx = 150 F, RLoadx = 5 , TPS2062C 6 VIN = 5 V, CLx = 150 F, RLoadx = 5 , TPS2062C 6 4 ENx ENx (V) ENx (V) -2m OUTx 2 4 OUTx 2 ENx 0 -2 -3m 0 -2m -1m 0 1m 2m Time (s) 3m 4m Figure 11. TPS2062C Turn on Delay and Rise Time With 150-F Load 8 Submit Documentation Feedback 5m -2 -3m -2m -1m 0 1m 2m Time (s) 3m 4m 5m Figure 12. TPS2062C Turn off Delay and Fall Time With 150-F Load Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C www.ti.com SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) 4 2 5.0 5 4.0 3.0 ENx 0 2.0 OUTx -2 1.0 OUTx Current -4 0.0 -6 -10m 0 10m 20m Time (s) 30m 3.0 3 2.5 OUTx -1 -3 150 F -9 -2m 0 2m 0.5 680 F 0.0 4m Time (s) 6m 8m -0.5 10m 8 5.0 6 VIN = 5 V, CLx = 150 F, RLoadx = 5 , TPS2062C 6.0 5.0 4.0 FLTx 2 3.0 OUTx 0 2.0 -2 1.0 IOUTx -4 0 4m 0.0 -1.0 12m 8m Time (s) FLTx, OUTx, VIN (V) VIN VIN -4m 1.5 1.0 -5 6.0 OUTx Current (A) FLTx, OUTx, VIN (V) 6 -6 -8m 1000 F Figure 14. TPS2062C Inrush Current With Different Load Capacitance VIN = 5 V, CLx = 150 F, RLoadx = 5 , TPS2062C 4 2.0 220 F Figure 13. TPS2062C Enable Into Short 8 FLTx ENx 1 -7 -1.0 50m 40m 3.5 VIN = 5 V, RLoadx = 5.0 , TPS2062C OUTx Current (A) FLTx 7 4 4.0 2 3.0 FLTx 0 2.0 OUTx -2 1.0 IOUTx -4 -6 -4m OUTx Current (A) ENx ,OUTx , FLTx (V) 6 6.0 ENx ,OUTx , FLTx (V) VIN = 5 V, CLx = 150 F, RLoadx = 0 , TPS2062C OUTx Current (A) 8 0.0 0 4m 8m 12m -1.0 16m Time (s) Figure 15. TPS2062C Power Up - Enabled Figure 16. TPS2062C Power Down - Enabled 4.2 8 VIN = 5 V, CLx = 150 F, RLoadx = 2.0 , TPS2062C 3.6 6 FLTx ENx, OUTx, FLTx (V) ENx 3.0 4 2 2.4 OUTx 1.8 0 1.2 -2 IOUTx -4 0.6 0.0 -6 -8 -4m -2m 0 2m 4m 6m Time (s) 8m 10m 12m -0.6 14m Figure 17. TPS2062C Enable With 2- Load Copyright (c) 2011-2012, Texas Instruments Incorporated Figure 18. TPS2062C Enable With 1- Load Submit Documentation Feedback Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C 9 TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 3.5 8 4.2 8 VIN = 5 V, CLx = 150 F, RLoadx = 10 , TPS2062C VIN = 5 V, CLx = 150 F, RLoadx = 0 , TPS2062C 6 3.6 6 3.0 4 3.0 ENx 2 2.4 1.8 0 OUTx -2 1.2 IOUTx -4 0.6 -8 -8m -4m 0 4m 8m 2 1.5 0 ENx -2 -4 0 2m 12.0 8 10.0 6 6.0 OUTx 4.0 0 2m 4m 6m Time (s) 8m 42 30 OUTx 24 3 18 12 1 6 2 Figure 23. TPS2064C Short Applied 3 6 ENx, OUTx, FLTx (V) IOUTx Submit Documentation Feedback 1 0 -3m -2m -1m 0 1m Time (s) 2m 3m 4m -1 5m 12.0 VIN = 5 V, CLx = 150 F, RLoadx = 0 , TPS2003C 36 1 2 8 VIN = 5 V, CLx = 0 F, RLoadx = 50 m, TPS2064C 0 Time (s) 3 Figure 22. TPS2064C Enable into 3.3 and 150-F Laod 7 -1 0 -2 -8 -4m -2.0 10m 12m 14m Figure 21. TPS2064C Enable into Short 5 4 ENx -6 0.0 0 5 IOUTx -4 OUTx (V) 6 -4 IOUTx 10 7 VIN = 5 V, CLx = 150 F, RLoadx = 3.3 , TPS2064C 2 2.0 -2 -2 -0.5 8m 10m 12m 14m 16m 18m Time (s) OUTx OUTx, ENx (V) ENx, OUTx, FLTx (V) ENx 2 -1 -3 6m 4 8.0 4 -6 -6m -4m -2m 4m Figure 20. TPS2062C Enable/Disable into 10- Load VIN = 5 V, CLx = 150 F, RLoadx = 0 , TPS2064C FLTx 0.5 0.0 Figure 19. TPS2062C Enable/Disable into Output Short 6 1.0 IOUTx -8 -2m -0.6 12m 16m 20m 24m 28m 32m Time (s) 8 2.0 -6 0.0 -6 2.5 OUTx FLTx OUTx Current (A) 4 ENx, OUTx, FLTx (V) ENx, OUTx, FLTx (V) FLTx 10.0 FLTx 8.0 4 ENx 2 6.0 OUTx 4.0 0 -2 2.0 IOUTx 0.0 0 -4 -6 -6 -6m -4m -2m 0 2m 4m 6m Time (s) 8m -2.0 10m 12m 14m Figure 24. TPS2003C Enable into Short Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C www.ti.com SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) 7 8 3.4 VIN = 5 V, CLx = 150 F, RLoadx = 2.5 , TPS2003C 2.0 A rated VIN = 5.5 V 3.2 6 6 3 ENx 5 OUTx 2.8 2.6 2 4 0 3 -2 2 2 1 1.8 -4 -8 -3m -2m -1m 0 1m 2m 3m Time (s) 1.5 A rated 2.4 2.2 1.0 A rated 1.6 IOUTx -6 IOS (A) OUTx, ENx (V) 4 0 4m 5m 6m 1.4 -1 7m 1.2 -40 Figure 25. TPS2003C Enable into 2.5 and 150-F Laod 0 20 40 60 80 Junction Temperature (C) 100 120 Figure 26. Current Limit (IOS) vs Temperature 100 2.5 VIN = 5 V VIN = 5 V 2 A rated 90 1.0 A rated 2 80 1.5 ISD (A) RDSON (m) -20 1 A rated 70 60 1.5 A rated 2.0 A rated 1 0.5 1.5 A rated 50 0 40 -40 -20 0 20 40 60 80 Junction Temperature (C) 100 -0.5 -40 120 Figure 27. Input - output Resistance (RDS(ON)) vs Temperature -20 0 20 40 60 80 Junction Temperature (C) 100 120 Figure 28. Supply Current (Device Disable) - ISD vs Temperature Supply Current - Device Enable (A) 130 VIN = 5 V 1.0 A rated(IS2E) 120 110 2.0 A rated(IS2E) 100 90 1.5 A rated(IS2E) 2.0 A rated(IS1E) 80 1.5 A rated(IS1E) 70 60 50 -40 1.0 A rated(IS1E) -20 0 20 40 60 80 Junction Temperature (C) 100 120 Figure 29. Supply Current (Enable) - ISE vs Temperature Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C 11 TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 www.ti.com DETAILED DESCRIPTION OVERVIEW The TPS20xxC dual are current-limited, power-distribution switches providing between 1 A and 2 A of continuous load current in 5-V circuits. These parts use N-channel MOSFETs for low resistance, maintaining output voltage load regulation. They are designed for applications where short circuits or heavy capacitive loads will be encountered. Device features include UVLO, ON/OFF control (Enable), reverse blocking when disabled, output discharge when disabled, overcurrent protection, over-temperature protection, and deglitched fault reporting. They are pin for pin with existing TI Switch Portfolio. UNDERVOLTAGE LOCKOUT (UVLO) The undervoltage lockout (UVLO) circuit disables the power switch when the input voltage is below the UVLO threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current surges. FLTx is high impedance when the TPS20xxC dual is in UVLO. ENABLE (ENx or ENx) The logic input of ENx or ENx disables all of the internal circuitry while maintaining the power switch OFF. The supply current of the device can be reduced to less than 1 A when both switches are disabled. A logic low input on ENx or a logic high input on ENx enables the driver, control circuits, and power switch of corresponding channel. The ENx or ENx input voltage is compatible with both TTL and CMOS logic levels. The FLTx is immediately cleared and the output discharge circuit is enabled when the device is disabled. DEGLITCHED FAULT REPORTING FLTx is an open-drain output that asserts (active low) during an overcurrent or overtemperature condition on each corresponding channel. The FLTx output remains asserted until the fault condition is removed or the channel is disabled. The TPS20xxC dual eliminates false FLTx reporting by using internal delay circuitry after entering or leaving an overcurrent condition. The "deglitch" time is typically 10 ms. This ensures that FLTx is not accidentally asserted under overcurrent conditions with a short time, such as starting into a heavy capacitive load. Over temperature conditions are not deglitched. The FLTx pin is high impedance when the device is disabled and in undervoltage lockout (UVLO). The fault circuits are independent so that another channel continues to operate when one channel is in a fault condition. OVERCURRENT PROTECTION The TPS20xxC dual responds to overloads by limiting each channel output current to the static IOS levels shown in the Electrical Characteristics table. When an overload condition is present, the device maintains a constant current (IOS) and reduces the output voltage accordingly, with the output voltage falling to (IOS x RSHORT). Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before voltage is applied to IN. The device senses over-current and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant a short -circuit occurs, high currents may flow for several microseconds (tIOS) before the current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit has responded. In the third condition, the load is increased gradually beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached. The devices are capable of delivering current up to the current-limit threshold without damage. Once the threshold is reached, the device switches into constantcurrent mode. For all of the above three conditions, the device may begin thermal cycling if the overcurrent condition persists. 12 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C www.ti.com SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 OVERTEMPERATURE PROTECTION The TPS20xxC dual includes per channel overtemperature protection circuitry, which activates at 135C (min) junction temperature while in current limit. There is an overall thermal shutdown of 155C (min) junction temperature when the TPS20xxC dual is not in current limit. The device remains off until the junction temperature cools 20C and then restarts. Thermal shutdown may occur during an overload due to the relatively large power dissipation [(VIN - VOUT) x IOS] driving the junction temperature up. The power switch cycles on and off until the fault is removed. This topology allows one channel to continue normal operation even if the other channel is in an over-temperature condition. SOFTSTART, REVERSE BLOCKING AND DISCHARGE OUTPUT The power MOSFET driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionality. The TPS20xxC dual power switch will block current from OUT to IN when turned off by the UVLO or disabled. The TPS20xxC dual includes an output discharge function on each channel. A 470 (typ.) discharge resistor will dissipate stored charge and leakage current on OUTx when the device is in UVLO or disabled. However as this circuit is biased from IN, the output discharge will not be active when IN voltage is close to 0 V. Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C 13 TPS2062C, TPS2066C TPS2060C, TPS2064C TPS2002C, TPS2003C SLVSAX6B - OCTOBER 2011 - REVISED MARCH 2012 www.ti.com APPLICATION INFORMATION INPUT AND OUTPUT CAPACITANCE Input and output capacitance improves the performance of the device. For all applications, a 0.1 F or greater ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local noise de-coupling. The actual capacitance should be optimized for the particular application. This precaution reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the input to reduce the overshoot voltage from exceeding the absolute maximum voltage of the device during heavy transients. A 120 F minimum output capacitance is required when implementing USB standard applications. Typically this uses a 150 F electrolytic capacitor. If the application does not require 120 F of output capacitance, a minimum of 10 F ceramic capacitor on the output is recommended in order to reduce the transient negative voltage on OUTx pin caused by load inductance during a short circuit. The transient negative voltage should be less than 1.5 V for 10 s. POWER DISSIPATION AND JUNCTION TEMPERATURE It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS20xxC dual. The system designer can control choices of package, proximity to other power dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors such as airflow and maximum ambient temperature are often determined by system considerations. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. The following procedure requires iteration because power loss is due to the two internal MOSFETs 2 x I2 x rDS(on), and rDS(on) is a function of the junction temperature. As an initial estimate, use the rDS(on) at 125C from the typical characteristics, and the preferred package thermal resistance for the preferred board construction from the thermal parameters section. TJ = TA + [(2 x IOUT2 x rDS(on) x JA] Where: IOUT = rated OUT pin current (A) rDS(on) = Power switch on-resistance at an assumed TJ () TA = Maximum ambient temperature (C) TJ = Maximum junction temperature (C) JA = Thermal resistance (C/W) If the calculated TJ is substantially different from the original assumption, look up a new value of rDS(on) and recalculate. If the resulting TJ is not less than 125C, try a PCB construction and/or package with lower JA. Spacer REVISION HISTORY Changes from Original (October 2011) to Revision A Page * Changed devices TPS2062C and TPS2066C MSOP-8 package From: Preview to Active ................................................. 1 * Changed the IOS current limit values for TPS2062C/66C (1 A). ........................................................................................... 3 * Changed the IOS current limit values for TPS2062C/66C (1 A). ........................................................................................... 4 Changes from Revision A (March 2012) to Revision B * 14 Page Changed device TPS2060C MSOP-8 package From: Preview to Active ............................................................................ 1 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C PACKAGE OPTION ADDENDUM www.ti.com 3-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty TPS2002CDRCR PREVIEW SON DRC 10 3000 TBD Call TI Call TI TPS2002CDRCT PREVIEW SON DRC 10 250 TBD Call TI Call TI TPS2003CDRCR PREVIEW SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2003CDRCT PREVIEW SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2060CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TPS2060CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TPS2062CD PREVIEW SOIC D 8 75 TBD TPS2062CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TPS2062CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TPS2062CDR PREVIEW SOIC D 8 2500 TBD TPS2064CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TPS2064CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TPS2066CD PREVIEW SOIC D 8 75 TBD TPS2066CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TPS2066CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TPS2066CDR PREVIEW SOIC D 8 2500 TBD Eco Plan (1) (2) Lead/ Ball Finish Call TI Call TI Call TI Call TI MSL Peak Temp Samples (Requires Login) Call TI Call TI Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 (3) PACKAGE OPTION ADDENDUM www.ti.com 3-May-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Apr-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2060CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS2062CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS2064CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS2066CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Apr-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2060CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TPS2062CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TPS2064CDGNR MSOP-PowerPAD DGN 8 2500 360.0 162.0 98.0 TPS2066CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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