1
2
3
4 5
6
7
81
2
3
4
6
7
8
PAD
9
10
5
GND
IN
EN 1 or EN 1
EN 2 or EN 2
FLT 1
FLT 2
OUT 1
OUT 2
EN 1 or EN 1
EN 2 or EN 2
IN
IN
GND
OUT 1
OUT 2
FLT 1
FLT 2 NC
D
(Top View)
DRC
(Top View)
1
2
3
4 5
6
7
8
PAD
GND
IN
EN 1 or EN 1
EN 2 or EN 2
OUT 1
OUT 2
FLT 1
FLT 2
DGN
(Top View)
VIN
RFLT1 RFLT2
10 kW
10 kW
0.1 Fm
Fault Signals
Control Signals
IN
FLT1
FLT2
EN1 or EN1
EN2 or EN2
OUT 1
OUT 2
GND
Pad
VOUT1
VOUT2
150 F x 2m
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
Dual Channel, Current-Limited, Power-Distribution Switches
Check for Samples: TPS2062C,TPS2066C,TPS2060C,TPS2064C,TPS2002C,TPS2003C
1FEATURES
2• Dual Power Switch Family • Built-in Softstart
• Rated Currents of 1 A / 1.5 A / 2 A • Pin for Pin with Existing TI Switch Portfolio
• Accurate ±20% Current-limit Tolerance • Ambient Temperature Range: –40°C to 85°C
• Fast Overcurrent Response – 2 µs (Typical) APPLICATIONS
• 70-mΩ(Typical) High-Side N-Channel MOSFET • USB Ports/Hubs, Laptops, Desktops
• Operating Range: 4.5 V to 5.5 V • High-Definition Digital TVs
• Deglitched Fault Reporting (FLTx) • Set Top Boxes
• Output Discharge When Disabled • Short-Circuit Protection
• Reverse Current Blocking
DESCRIPTION
The TPS20xxC dual power-distribution switch family is intended for applications such as USB where heavy
capacitive loads and short-circuits may be encountered. This family offers multiple devices with fixed current-limit
thresholds for applications between 1 A and 2 A.
The TPS20xxC dual family limits the output current to a safe level by operating in a constant-current mode when
the output load exceeds the current-limit threshold. This provides a predictable fault current under all conditions.
The fast overcurrent response time eases the burden on the main 5 V supply to provide regulated power when
the output is shorted. The power-switch rise and fall times are controlled to minimize current surges during turn-
on and turn-off.
Figure 1. TYPICAL APPLICATION
Table 1. Devices (1)
STATUS
RATED CURRENT DEVICES MSOP-8 (PowerPad™) SON -10 SOIC-8
1 A TPS2062C/66C Active / Active - Preview / Preview
1.5 A TPS2060C/64C Active / Active - -
2 A TPS2002C/03C - Preview / Preview -
(1) For more details, see the DEVICE INFORMATION table
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains Copyright © 2011–2012, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION(1)(2)
PACKAGE DEVICES(3)
MAXIMUM OUTPUT BASE PART MSOP-8
OPERATING ENABLE MARKING
SOIC-8 SON-10
DISCHARGE NUMBER (DGN)
CURRENT (D) (DRC)
PowerPAD™
1 Low Y TPS2062C √ √ – VRBQ
1 High Y TPS2066C √ √ – VRDQ
1.5 Low Y TPS2060C – √– VRAQ
1.5 High Y TPS2064C – √– VRCQ
2 Low Y TPS2002C – – √VREQ
2 High Y TPS2003C – – √VRFQ
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package code for MSOP-8 is “DGN” and for SON is “DRC”.
(3) “–” indicates the device is not available in this package.
ABSOLUTE MAXIMUM RATINGS(1)(2)
VALUE UNIT
MIN MAX
Voltage range on IN, OUTx, ENx or ENx, FLTx(3) –0.3 6 V
Voltage range from IN to OUT –6 6 V
Maximum junction temperature, TJInternally Limited °C
Human Body Model 2 kV
ESD Charged Device Model 500 V
IEC 61000-4-2, Contact / Air(4) 8 / 15 kV
(1) Absolute maximum ratings apply over recommended junction temperature range.
(2) All voltages are with respect to GND unless otherwise noted.
(3) See INPUT AND OUTPUT CAPACITANCE section.
(4) VOUT was surged on a PCB with input and output bypassing per Figure 1 (except input capacitor was 22 µF) with no device failure.
THERMAL INFORMATION D DGN DRC
THERMAL METRIC(1)(2) UNITS
8 PINS 8 PINS 10 PINS
θJA Junction-to-ambient thermal resistance 129.9 57.2 45.4
θJCtop Junction-to-case (top) thermal resistance 83.5 110.5 58
θJB Junction-to-board thermal resistance 70.4 60.7 21.1 °C/W
ψJT Junction-to-top characterization parameter 36.6 7.8 1.9
ψJB Junction-to-board characterization parameter 66.9 24 21.3
θJCbot Junction-to-case (bottom) thermal resistance n/a 14.3 9.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
2Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VIN Input voltage, IN 4.5 5.5 V
VEnable Input voltage, ENx or ENx 0 5.5
TPS2062C/66C 1
IOUTx Continuous ouput current, OUTx TPS2060C/64C 1.5 A
TPS2002C/03C 2
TJOperating junction temperature –40 125 °C
IFLTx Sink current into FLTx 0 5 mA
ELECTRICAL CHARACTERISTICS(1)(2)
TJ= TA= 25°C，VIN = 5 V, VENx = VIN or VENx = 0V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SWITCH
TPS2062C/66C (1 A) DGN 70 84
TPS2062C/66C (1 A), –40°C ≤(TJ, TA)≤DGN 70 95
85°C
TPS2062C/66C (1 A) D 84
TPS2062C/66C (1 A), –40°C ≤(TJ, TA)≤D 84
rDS(on) On-resistance mΩ
85°C
TPS2060C/64C (1.5 A) 70 84
TPS2060C/64C (1.5 A), –40°C ≤(TJ, TA)≤85°C 70 95
TPS2002C/03C (2 A) 70 84
TPS2002C/03C (2 A), –40°C ≤(TJ, TA)≤85°C 70 95
CURRENT LIMIT
TPS2062C/66C (1 A) 1.28 1.61 1.94
IOS Current limit, See Figure 7 TPS2060C/64C (1.5 A) 1.83 2.29 2.75 A
TPS2002C/03C (2 A) 2.43 2.96 3.49
VIN = 5 V (see Figure 6),
One-half full load →R(SHORT) = 50 mΩ, Measure from
tIOS Short-circuit response time 2 µs
application to when current falls below 120% of final
value
SUPPLY CURRENT
ISD Supply current, device disabled I(OUTx) = 0 mA 0.01 1
IS1E Supply current, single switch enabled I(OUTx) = 0 mA 60 75 µA
Supply current, both switches
IS2E I(OUTx) = 0 mA 100 120
enabled
ILKG Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured IOUTx 0.15 1
OUTPUT DISCHARGE
RPD Output pull-down resistance(2) VIN = V(OUTx) = 5 V, disabled 400 470 600 Ω
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
–40°C ≤(TJ= TA)≤125°C, 4.5 V ≤VIN ≤5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A, typical values are at 5 V and 25°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
POWER SWITCH
DGN 70 112
TPS2062C/66C (1 A) D 84 135
rDS(on) On-resistance mΩ
TPS2060C/64C (1.5 A) 70 112
TPS2002C/03C (2 A) 70 112
ENABLE INPUT (ENx or ENx)
ENx (ENx), High-level input
VIH 4.5 V ≤VIN ≤5.5 V 2
voltage
ENx (ENx), Low-level input V
VIL 0.8
Voltage
Hysteresis VIN = 5 V 0.14
Leakage current VENx = 5.5 V or 0 V, VENx = 0 V or 5.5 V -1 0 1 µA
VIN = 5 V, CL= 1 µF, RL= 100 Ω, ENx ↑or
ENx ↓, See Figure 4,Figure 5, and Figure 2
ton Turn-on time ms
1 A / 1.5 A / 2 A Rated 1.4 1.9 2.4
VIN = 5 V, CL= 1 µF, RL= 100 Ω, ENx ↑or
EN ↓, See Figure 4,Figure 5, and Figure 2
toff Turn-off time ms
1 A / 1.5 A / 2 A Rated 1.95 2.60 3.25
CL= 1 µF, RL= 100 Ω, see Figure 3
trRise time, output ms
1A / 1.5 A / 2 A Rated 0.58 0.82 1.15
CL= 1 µF, RL= 100 Ω, see Figure 3
tfFall time, output ms
1A / 1.5A / 2A Rated 0.33 0.47 0.66
CURRENT LIMIT
TPS2062C/66C (1 A) 1.12 1.61 2.10
IOS Current-limit, See Figure 7 TPS2060C/64C (1.5 A) 1.72 2.29 2.86 A
TPS2002C/03C (2 A) 2.22 2.96 3.7
VIN = 5 V (see Figure 6), One-half full load →R(SHORT) =
tIOS Short-circuit response time(2) 50 mΩ, measure from application to when current falls 2 µs
below 120% of final value
SUPPLY CURRENT
ISD Supply current, switch disabled Standard conditions, I(OUTx) = 0 mA 0.01 10
Supply current, single switch
IS1E Standard conditions, I(OUTx) = 0 mA 90
enabled µA
Supply current, both switches
IS2E Standard conditions, I(OUTx) = 0 mA 150
enabled
ILKG Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured I(OUTx) 0.20
UNDERVOLTAGE LOCKOUT
UVLO Low-level input voltage, IN VIN rising 3.4 4.0 V
Hysteresis, IN(2) 0.14 V
FLTx
Output low voltage, FLTx I(FLTx) = 1 mA 0.2 V
Off-state leakage V(FLTx) = 5.5 V 1 µA
FLTx deglitch FLTx overcurrent assertion/deassertion 7 10 13 ms
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
4Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
CL
RL
OUTx
tr
10%
90%
VOUT
tf
VEN
VOUT
ton toff
50% 50%
10%
90%
VEN
VOUT
ton
toff
50% 50%
10%
90%
IOUT
IOS
120% x IOS
tIOS
0A
Decreasing
Load
Resistance
VIN
VOUT
0 A
0 V IOUT
IOS
Slope = -rDS(on)
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (continued)
–40°C ≤(TJ= TA)≤125°C, 4.5 V ≤VIN ≤5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A, typical values are at 5 V and 25°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
OUTPUT DISCHARGE
VIN = 5 V, VOUT = 5 V, disabled 300 470 800
RPD Output pull-down resistance(3) Ω
VIN = 4 V, VOUT = 5 V, disabled 350 560 1200
THERMAL SHUTDOWN
In current limit 135
Junction thermal shutdown °C
threshold Not in current limit 155
Hysteresis(3) 20 °C
(3) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
Figure 2. Output Rise / Fall Test Load Figure 3. Power-On and Off Timing
SPACER
Figure 4. Enable Timing, Active High Enable Figure 5. Enable Timing, Active Low Enable
SPACER
Figure 6. Output Short Circuit Parameters Figure 7. Output Characteristic Showing Current
SPACER Limit
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
6Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
DEVICE INFORMATION
PIN FUNCTIONS – MSOP-8 PACKAGES
NAME TPS2066C/64C TPS2062C/60C I/O DESCRIPTION
GND 1 1 Pwr Ground connection
IN 2 2 I Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1 3 - I Enable input channel 1, logic high turns on power switch
EN1 - 3 I Enable input channel 1, logic low turns on power switch
EN2 4 - I Enable input channel 2, logic high turns on power switch
EN2 - 4 I Enable input channel 2, logic low turns on power switch
FLT2 5 5 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
OUT2 6 6 O Power-switch output channel 2, connected to load
OUT1 7 7 O Power-switch output channel 1, connected to load
FLT1 8 8 O Active-low open-drain output, asserted during over-current, or overtemperature conditions on
channel 1
PowerPAD™ PAD PAD Pwr Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect
PAD to GND plane as a heatsink.
PIN FUNCTIONS – SOIC-8 PACKAGES
NAME TPS2066C TPS2062C I/O DESCRIPTION
GND 1 1 Pwr Ground connection
IN 2 2 I Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1 3 - I Enable input channel 1, logic high turns on power switch
EN1 - 3 I Enable input channel 1, logic low turns on power switch
EN2 4 - I Enable input channel 2, logic high turns on power switch
EN2 - 4 I Enable input channel 2, logic low turns on power switch
FLT2 5 5 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
OUT2 6 6 O Power-switch output channel 2, connected to load
OUT1 7 7 O Power-switch output channel 1, connected to load
FLT1 8 8 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 1
PIN FUNCTIONS – SON-10 PACKAGES
NAME TPS2003C TPS2002C I/O DESCRIPTION
GND 1 1 Pwr Ground connection
IN 2, 3 2, 3 I Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1 4 – I Enable input channel 1, logic high turns on power switch
EN1 – 4 I Enable input channel 1, logic low turns on power switch
EN2 5 – I Enable input channel 2, logic high turns on power switch
EN2 – 5 I Enable input channel 2, logic low turns on power switch
FLT2 6 6 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
NC 7 7 No connect – leave floating.
OUT2 8 8 O Power-switch output channel 2, connect to load
OUT1 9 9 O Power-switch output channel 1, connect to load
FLT1 10 10 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 1
PowerPAD™ PAD PAD Pwr Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect
PAD to GND plane as a heatsink.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
OUT1
IN
GND
FLT1 CL1
3.01k
Control Signals
VIN
0.1 F
Fault Signals Pad
VOUT1
EN1 or EN1
FLT2
EN2 or EN2
CL2
VOUT2
OUT2
R
Load2
R
Load1
IOUT1 IOUT2
3.01k
−2
0
2
4
6
8
−3m −2m −1m 0 1m 2m 3m 4m 5m
ENx OUTx
Time (s)
ENx (V)
VIN = 5 V, CLx = 1 µF, RLoadx = 5 Ω, TPS2062C
−2
0
2
4
6
8
−3m −2m −1m 0 1m 2m 3m 4m 5m
ENx
OUTx
Time (s)
ENx (V)
VIN = 5 V, CLx = 1 µF, RLoadx = 5 Ω, TPS2062C
−2
0
2
4
6
8
−3m −2m −1m 0 1m 2m 3m 4m 5m
ENx OUTx
Time (s)
ENx (V)
VIN = 5 V, CLx = 150 µF, RLoadx = 5 Ω, TPS2062C
−2
0
2
4
6
8
−3m −2m −1m 0 1m 2m 3m 4m 5m
ENx
OUTx
Time (s)
ENx (V)
VIN = 5 V, CLx = 150 µF, RLoadx = 5 Ω, TPS2062C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS
Figure 8. Test Circuit for System Operation in Typical Characteristics Section
Figure 9. TPS2062C Turn on Delay and Figure 10. TPS2062C Turn off Delay and
Rise Time With 1-μF Load Fall Time With 1-μF Load
Figure 11. TPS2062C Turn on Delay and Figure 12. TPS2062C Turn off Delay and
Rise Time With 150-μF Load Fall Time With 150-μF Load
8Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
−10m 0 10m 20m 30m 40m 50m
−6
−4
−2
0
2
4
6
8
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
ENx
OUTx
FLTx
Time (s)
ENx ,OUTx , FLTx (V)
OUTx Current (A)
OUTx Current
VIN = 5 V, CLx = 150 µF, RLoadx = 0 Ω, TPS2062C
−2m 0 2m 4m 6m 8m 10m
−9
−7
−5
−3
−1
1
3
5
7
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
ENx
OUTx FLTx
Time (s)
ENx ,OUTx , FLTx (V)
OUTx Current (A)
150 µF
220 µF
680 µF
1000 µF
VIN = 5 V, RLoadx = 5.0 Ω, TPS2062C
−8m −4m 0 4m 8m 12m
−6
−4
−2
0
2
4
6
8
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VIN
OUTx FLTx
Time (s)
FLTx, OUTx, VIN (V)
OUTx Current (A)
IOUTx
VIN = 5 V, CLx = 150 µF, RLoadx = 5 Ω, TPS2062C
−4m 0 4m 8m 12m 16m
−6
−4
−2
0
2
4
6
8
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VIN
OUTx
FLTx
Time (s)
FLTx, OUTx, VIN (V)
OUTx Current (A)
IOUTx
VIN = 5 V, CLx = 150 µF, RLoadx = 5 Ω, TPS2062C
−4m −2m 0 2m 4m 6m 8m 10m 12m 14m
−8
−6
−4
−2
0
2
4
6
8
−0.6
0.0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
ENx
OUTx
FLTx
Time (s)
ENx, OUTx, FLTx (V)
IOUTx
VIN = 5 V, C = 150 F, R = 2.0 , TPS2062C
Lx Loadx
μ Ω
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
Figure 13. TPS2062C Enable Into Short Figure 14. TPS2062C Inrush Current
With Different Load Capacitance
Figure 15. TPS2062C Power Up – Enabled Figure 16. TPS2062C Power Down – Enabled
Figure 17. TPS2062C Enable With 2-ΩLoad Figure 18. TPS2062C Enable With 1-ΩLoad
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
−8m −4m 0 4m 8m 12m 16m 20m 24m 28m 32m
−8
−6
−4
−2
0
2
4
6
8
−0.6
0.0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
OUTx
ENx
FLTx
Time (s)
ENx, OUTx, FLTx (V)
IOUTx
VIN = 5 V, C = 150 F, R = 0 , TPS2062C
Lx Loadx
μ Ω
−2m 0 2m 4m 6m 8m 10m 12m 14m 16m 18m
−8
−6
−4
−2
0
2
4
6
8
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTx
ENx
FLTx
Time (s)
ENx, OUTx, FLTx (V)
IOUTx
VIN = 5 V, C = 150 F, R = 10 , TPS2062C
Lx Loadx
μ Ω
−4m −3m −2m −1m 0 1m 2m 3m 4m 5m
−8
−6
−4
−2
0
2
4
6
8
−1
0
1
2
3
4
5
6
7
OUTx
ENx
Time (s)
OUTx, ENx (V)
OUTx Current (A)
IOUTx
VIN = 5 V, CLx = 150 µF, RLoadx = 3.3 Ω, TPS2064C
−6m −4m −2m 0 2m 4m 6m 8m 10m 12m 14m
−6
−4
−2
0
2
4
6
8
−2.0
0.0
2.0
4.0
6.0
8.0
10.0
12.0
OUTx
ENx
FLTx
Time (s)
ENx, OUTx, FLTx (V)
IOUTx
VIN = 5 V, C = 150 F, R = 0 , TPS2064C
Lx Loadx
μ Ω
−3μ−2μ−1μ0 3μ2μ1μ
−1
1
3
5
7
−6
0
6
12
18
24
30
36
42
OUTx
Time (s)
OUTx (V)
IOUTx
VIN = 5 V, C = 0 F, R = 50 m , TPS2064C
Lx Loadx
μ Ω
−6m −4m −2m 0 2m 4m 6m 8m 10m 12m 14m
−6
−4
−2
0
2
4
6
8
−2.0
0.0
2.0
4.0
6.0
8.0
10.0
12.0
OUTx
ENx
FLTx
Time (s)
ENx, OUTx, FLTx (V)
IOUTx
VIN = 5 V, C = 150 F, R = 0 , TPS2003C
Lx Loadx
μ Ω
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 19. TPS2062C Enable/Disable Figure 20. TPS2062C Enable/Disable
into Output Short into 10-ΩLoad
Figure 21. TPS2064C Enable into Short Figure 22. TPS2064C Enable into 3.3 Ωand 150-μF Laod
Figure 23. TPS2064C Short Applied Figure 24. TPS2003C Enable into Short
10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
−3m −2m −1m 0 1m 2m 3m 4m 5m 6m 7m
−8
−6
−4
−2
0
2
4
6
8
−1
0
1
2
3
4
5
6
7
OUTx
ENx
Time (s)
OUTx, ENx (V)
IOUTx
VIN = 5 V, C = 150 F, R = 2.5 , TPS2003C
Lx Loadx
μ Ω
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
−40 −20 0 20 40 60 80 100 120
2.0 A rated
1.0 A rated
1.5 A rated
Junction Temperature (°C)
IOS (A)
VIN = 5.5 V
40
50
60
70
80
90
100
−40 −20 0 20 40 60 80 100 120
1 A rated
2 A rated
1.5 A rated
RDSON (mΩ)
VIN = 5 V
Junction Temperature (°C)
−0.5
0
0.5
1
1.5
2
2.5
−40 −20 0 20 40 60 80 100 120
2.0 A rated
1.0 A rated
1.5 A rated
ISD (μA)
VIN = 5 V
Junction Temperature (°C)
50
60
70
80
90
100
110
120
130
−40 −20 0 20 40 60 80 100 120
2.0 A rated(IS1E)
1.0 A rated(IS1E)
2.0 A rated(IS2E)
1.0 A rated(IS2E)
1.5 A rated(IS1E)
1.5 A rated(IS2E)
Supply Current − Device Enable ( A)μ
VIN = 5 V
Junction Temperature (°C)
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
Figure 25. TPS2003C Enable into 2.5 Ωand 150-μF Laod Figure 26. Current Limit (IOS) vs Temperature
Figure 27. Input - output Resistance (RDS(ON)) vs Figure 28. Supply Current (Device Disable) - ISD vs
Temperature Temperature
Figure 29. Supply Current (Enable) - ISE vs Temperature
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
www.ti.com
DETAILED DESCRIPTION
OVERVIEW
The TPS20xxC dual are current-limited, power-distribution switches providing between 1 A and 2 A of continuous
load current in 5-V circuits. These parts use N-channel MOSFETs for low resistance, maintaining output voltage
load regulation. They are designed for applications where short circuits or heavy capacitive loads will be
encountered. Device features include UVLO, ON/OFF control (Enable), reverse blocking when disabled, output
discharge when disabled, overcurrent protection, over-temperature protection, and deglitched fault reporting.
They are pin for pin with existing TI Switch Portfolio.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch when the input voltage is below the UVLO
threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current
surges. FLTx is high impedance when the TPS20xxC dual is in UVLO.
ENABLE (ENx or ENx)
The logic input of ENx or ENx disables all of the internal circuitry while maintaining the power switch OFF. The
supply current of the device can be reduced to less than 1 µA when both switches are disabled. A logic low input
on ENx or a logic high input on ENx enables the driver, control circuits, and power switch of corresponding
channel.
The ENx or ENx input voltage is compatible with both TTL and CMOS logic levels. The FLTx is immediately
cleared and the output discharge circuit is enabled when the device is disabled.
DEGLITCHED FAULT REPORTING
FLTx is an open-drain output that asserts (active low) during an overcurrent or overtemperature condition on
each corresponding channel. The FLTx output remains asserted until the fault condition is removed or the
channel is disabled. The TPS20xxC dual eliminates false FLTx reporting by using internal delay circuitry after
entering or leaving an overcurrent condition. The “deglitch” time is typically 10 ms. This ensures that FLTx is not
accidentally asserted under overcurrent conditions with a short time, such as starting into a heavy capacitive
load. Over temperature conditions are not deglitched. The FLTx pin is high impedance when the device is
disabled and in undervoltage lockout (UVLO). The fault circuits are independent so that another channel
continues to operate when one channel is in a fault condition.
OVERCURRENT PROTECTION
The TPS20xxC dual responds to overloads by limiting each channel output current to the static IOS levels shown
in the Electrical Characteristics table. When an overload condition is present, the device maintains a constant
current (IOS) and reduces the output voltage accordingly, with the output voltage falling to (IOS x RSHORT). Three
possible overload conditions can occur. In the first condition, the output has been shorted before the device is
enabled or before voltage is applied to IN. The device senses over-current and immediately switches into a
constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At
the instant a short -circuit occurs, high currents may flow for several microseconds (tIOS) before the current-limit
circuit reacts. The device operates in constant-current mode after the current-limit circuit has responded. In the
third condition, the load is increased gradually beyond the recommended operating current. The current is
permitted to rise until the current-limit threshold is reached. The devices are capable of delivering current up to
the current-limit threshold without damage. Once the threshold is reached, the device switches into constant-
current mode. For all of the above three conditions, the device may begin thermal cycling if the overcurrent
condition persists.
12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
OVERTEMPERATURE PROTECTION
The TPS20xxC dual includes per channel overtemperature protection circuitry, which activates at 135°C (min)
junction temperature while in current limit. There is an overall thermal shutdown of 155°C (min) junction
temperature when the TPS20xxC dual is not in current limit. The device remains off until the junction temperature
cools 20°C and then restarts. Thermal shutdown may occur during an overload due to the relatively large power
dissipation [(VIN – VOUT) × IOS] driving the junction temperature up. The power switch cycles on and off until the
fault is removed. This topology allows one channel to continue normal operation even if the other channel is in an
over-temperature condition.
SOFTSTART, REVERSE BLOCKING AND DISCHARGE OUTPUT
The power MOSFET driver incorporates circuitry that controls the rise and fall times of the output voltage to limit
large current and voltage surges on the input supply, and provides built-in soft-start functionality.
The TPS20xxC dual power switch will block current from OUT to IN when turned off by the UVLO or disabled.
The TPS20xxC dual includes an output discharge function on each channel. A 470Ω(typ.) discharge resistor will
dissipate stored charge and leakage current on OUTx when the device is in UVLO or disabled. However as this
circuit is biased from IN, the output discharge will not be active when IN voltage is close to 0 V.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6B –OCTOBER 2011–REVISED MARCH 2012
www.ti.com
APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITANCE
Input and output capacitance improves the performance of the device. For all applications, a 0.1 µF or greater
ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local
noise de-coupling. The actual capacitance should be optimized for the particular application. This precaution
reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the
input to reduce the overshoot voltage from exceeding the absolute maximum voltage of the device during heavy
transients.
A 120 µF minimum output capacitance is required when implementing USB standard applications. Typically this
uses a 150 µF electrolytic capacitor. If the application does not require 120 µF of output capacitance, a minimum
of 10 µF ceramic capacitor on the output is recommended in order to reduce the transient negative voltage on
OUTx pin caused by load inductance during a short circuit. The transient negative voltage should be less than
1.5 V for 10 µs.
POWER DISSIPATION AND JUNCTION TEMPERATURE
It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPS20xxC dual. The system designer can control choices of package, proximity to other power dissipating
devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on
maximum junction temperature. Other factors such as airflow and maximum ambient temperature are often
determined by system considerations.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical.
The following procedure requires iteration because power loss is due to the two internal MOSFETs 2 × I2×
rDS(on), and rDS(on) is a function of the junction temperature. As an initial estimate, use the rDS(on) at 125°C from the
typical characteristics, and the preferred package thermal resistance for the preferred board construction from
the thermal parameters section.
TJ= TA+ [(2 × IOUT2× rDS(on) ×θJA]
Where:
IOUT = rated OUT pin current (A)
rDS(on) = Power switch on-resistance at an assumed TJ(Ω)
TA= Maximum ambient temperature (°C)
TJ= Maximum junction temperature (°C)
θJA = Thermal resistance (°C/W)
If the calculated TJis substantially different from the original assumption, look up a new value of rDS(on) and
recalculate.
If the resulting TJis not less than 125°C, try a PCB construction and/or package with lower θJA.
Spacer REVISION HISTORY
Changes from Original (October 2011) to Revision A Page
• Changed devices TPS2062C and TPS2066C MSOP-8 package From: Preview to Active ................................................. 1
• Changed the IOS current limit values for TPS2062C/66C (1 A). ........................................................................................... 3
• Changed the IOS current limit values for TPS2062C/66C (1 A). ........................................................................................... 4
Changes from Revision A (March 2012) to Revision B Page
• Changed device TPS2060C MSOP-8 package From: Preview to Active ............................................................................ 1
14 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2002CDRCR PREVIEW SON DRC 10 3000 TBD Call TI Call TI
TPS2002CDRCT PREVIEW SON DRC 10 250 TBD Call TI Call TI
TPS2003CDRCR PREVIEW SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2003CDRCT PREVIEW SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2060CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TPS2060CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TPS2062CD PREVIEW SOIC D 8 75 TBD Call TI Call TI
TPS2062CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TPS2062CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TPS2062CDR PREVIEW SOIC D 8 2500 TBD Call TI Call TI
TPS2064CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TPS2064CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TPS2066CD PREVIEW SOIC D 8 75 TBD Call TI Call TI
TPS2066CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TPS2066CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TPS2066CDR PREVIEW SOIC D 8 2500 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2060CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS2062CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS2064CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS2066CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Apr-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2060CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
TPS2062CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
TPS2064CDGNR MSOP-PowerPAD DGN 8 2500 360.0 162.0 98.0
TPS2066CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Apr-2012
Pack Materials-Page 2
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