DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Features n Alternate Military/Aerospace device (54LS109) is available. Contact a Fairchild Semiconductor Sales Office/Distributor for specifications Connection Diagram Dual-In-Line Package DS006368-1 Order Number 54LS109DMQB, 54LS109FMQB, DM54LS109AJ, DM54LS109AW, DM74LS109AM or DM74LS109AN See Package Number J16A, M16A, N16E or W16A Function Table Inputs Outputs PR CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H H L L H H H L H H L H Q0 H H H H H L H H L X X Q0 Q0 Q0 = The output logic level of Q before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each active transition of the clock pulse. Note 1: This configuration is nonstable; that is, it will not persist when preset and/or clear inputs return to their inactive (high) state. H (Note 1) H (Note 1) L H Toggle Q0 H = High Logic Level L = Low Logic Level X = Either Low or High Logic Level = Rising Edge of Pulse (c) 1998 Fairchild Semiconductor Corporation DS006368 www.fairchildsemi.com DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs March 1998 Absolute Maximum Ratings (Note 2) Supply Voltage Input Voltage Operating Free Air Temperature Range DM54LS and 54LS DM74LS Storage Temperature Range 7V 7V -55C to +125C 0C to +70C -65C to +150C Recommended Operating Conditions Symbol Parameter DM54LS109A DM74LS109A Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage 0.7 0.8 V IOH High Level Output Current -0.4 -0.4 mA IOL Low Level Output Current fCLK Clock Frequency (Note 4) fCLK tW tW tSU tSU 2 2 4 8 mA 0 25 MHz 0 20 MHz 0 25 Clock Frequency (Note 5) 0 20 Pulse Width Clock High 18 (Note 4) Preset Low 15 15 Clear Low 15 15 25 18 Pulse Width Clock High 25 (Note 5) Preset Low 20 20 Clear Low 20 20 Setup Time Data High 30 30 (Notes 3, 4) Data Low 20 20 Setup Time Data High 35 35 (Notes 3, 5) Data Low 25 25 tH Hold Time (Note 6) 0 TA Free Air Operating Temperature -55 V V ns ns ns ns 0 125 ns 0 70 C Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: The symbol () indicates the rising edge of the clock pulse is used for reference. Note 4: CL = 15 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 5: CL = 50 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 6: TA = 25C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units (Note 7) VI Input Clamp Voltage VOH High Level Output Voltage VOL Low Level Output Voltage II Input Current @ Max Input Voltage www.fairchildsemi.com VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V 2 -1.5 DM54 2.5 DM74 2.7 3.4 V V 3.4 DM54 0.25 DM74 0.35 0.4 0.5 DM74 0.25 0.4 J, K 0.1 Clock 0.1 Preset 0.2 Clear 0.2 V mA Electrical Characteristics (Continued) over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units (Note 7) IIH High Level Input Current VCC = Max VI = 2.7V 20 J,K Clock 20 Preset 40 Clear IIL Low Level Input Current VCC = Max VI = 0.4V 40 J, K -0.4 Clock -0.4 Preset -0.8 Clear IOS ICC mA -0.8 Short Circuit VCC = Max DM54 -20 -100 Output Current (Note 8) VCC = Max (Note 9) DM74 -20 -100 Supply Current A 4 8 mA mA Switching Characteristics at VCC = 5V and TA = 25C RL = 2 k From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Max 25 CL = 50 pF Min Units Max 20 MHz Frequency tPLH tPHL tPLH tPHL tPLH Propagation Delay Time Clock to Low to High Level Output Q or Q Propagation Delay Time Clock to High to Low Level Output Q or Q Propagation Delay Time Clear Low to High Level Output to Q Propagation Delay Time Clear High to Low Level Output to Q Propagation Delay Time Low to High Level Output tPHL Propagation Delay Time High to Low Level Output Preset 25 35 ns 30 35 ns 25 35 ns 30 35 ns 25 35 ns 30 35 ns to Q Preset to Q Note 7: All typicals are at VCC = 5V, TA = 25C. Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.25V and 2.125V for DM54 and DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 9: ICC is measured with all outputs open, with CLOCK grounded after setting the Q and Q outputs high in turn. 3 www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS109DMQB or DM54LS109AJ Package Number J16A 16-Lead Small Outline Molded Package (M) Order Number DM74LS109AM Package Number M16A www.fairchildsemi.com 4 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS109AN Package Number N16E 16-Lead Ceramic Flat Package Order Number 54LS109FMQB or DM54LS109AW Package Number W16A 5 www.fairchildsemi.com DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and (c) whose device or system, or to affect its safety or effectiveness. failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Corporation Americas Customer Response Center Tel: 1-888-522-5372 www.fairchildsemi.com Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 8 141-35-0 English Tel: +44 (0) 1 793-85-68-56 Italy Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.