DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset,
Clear, and Complementary Outputs
General Description
This device contains two independent
positive-edge-triggered J-K flip-flops with complementary
outputs. The J and K data is accepted by the flip-flop on the
rising edge of the clock pulse. The triggering occurs at a volt-
age level and is not directly related to the transition time of
the rising edge of the clock. The data on the J and K inputs
may be changed while the clock is high or low as long as
setup and hold times are not violated.Alow logic level on the
preset or clear inputs will set or reset the outputs regardless
of the logic levels of the other inputs.
Features
nAlternate Military/Aerospace device (54LS109) is
available. Contact a Fairchild Semiconductor Sales
Office/Distributor for specifications
Connection Diagram
Function Table
Inputs Outputs
PR CLR CLK J K QQ
LHXXX H L
HLXXX L H
L L X X X H (Note 1) H (Note 1)
HH ↑LL L H
HH ↑H L Toggle
HH ↑LH Q
0
Q
0
HH ↑HH H L
HH LXX Q
0
Q
0
H
=
High Logic Level
L=Low Logic Level
X=Either Low or High Logic Level
↑=Rising Edge of Pulse
Q0=The output logic level of Q before the indicated input conditions were
established.
Toggle =Each output changes to the complement of its previous level on
each active transition of the clock pulse.
Note 1: This configuration is nonstable; that is, it will not persist when preset
and/or clear inputs return to their inactive (high) state.
Dual-In-Line Package
DS006368-1
Order Number 54LS109DMQB, 54LS109FMQB, DM54LS109AJ,
DM54LS109AW, DM74LS109AM or DM74LS109AN
See Package Number J16A, M16A, N16E or W16A
March 1998
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary
Outputs
© 1998 Fairchild Semiconductor Corporation DS006368 www.fairchildsemi.com
Absolute Maximum Ratings (Note 2)
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
DM54LS and 54LS −55˚C to +125˚C
DM74LS 0˚C to +70˚C
Storage Temperature Range −65˚C to +150˚C
Recommended Operating Conditions
Symbol Parameter DM54LS109A DM74LS109A Units
Min Nom Max Min Nom Max
V
CC
Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
V
IH
High Level Input Voltage 2 2 V
V
IL
Low Level Input Voltage 0.7 0.8 V
I
OH
High Level Output Current −0.4 −0.4 mA
I
OL
Low Level Output Current 4 8 mA
f
CLK
Clock Frequency (Note 4) 0 25 0 25 MHz
f
CLK
Clock Frequency (Note 5) 0 20 0 20 MHz
t
W
Pulse Width Clock High 18 18
(Note 4) Preset Low 15 15 ns
Clear Low 15 15
t
W
Pulse Width Clock High 25 25
(Note 5) Preset Low 20 20 ns
Clear Low 20 20
t
SU
Setup Time Data High 30↑30↑ns
(Notes 3, 4) Data Low 20↑20↑
t
SU
Setup Time Data High 35↑35↑ns
(Notes 3, 5) Data Low 25↑25↑
t
H
Hold Time (Note 6) 0↑0↑ns
T
A
Free Air Operating Temperature −55 125 0 70 ˚C
Note 2:
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these
limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating
Conditions” table will define the conditions for actual device operation.
Note 3: The symbol (↑) indicates the rising edge of the clock pulse is used for reference.
Note 4: CL=15 pF, RL=2kΩ,T
A=25˚C and VCC =5V.
Note 5: CL=50 pF, RL=2kΩ,T
A=25˚C and VCC =5V.
Note 6: TA=25˚C and VCC =5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 7)
V
I
Input Clamp Voltage V
CC
=Min, I
I
=−18 mA −1.5 V
V
OH
High Level Output V
CC
=Min, I
OH
=Max DM54 2.5 3.4 V
Voltage V
IL
=Max, V
IH
=Min DM74 2.7 3.4
V
OL
Low Level Output V
CC
=Min, I
OL
=Max DM54 0.25 0.4
Voltage V
IL
=Max, V
IH
=Min DM74 0.35 0.5 V
I
OL
=4 mA, V
CC
=Min DM74 0.25 0.4
I
I
Input Current @Max V
CC
=Max J, K 0.1
Input Voltage V
I
=7V Clock 0.1 mA
Preset 0.2
Clear 0.2
www.fairchildsemi.com 2
Electrical Characteristics (Continued)
over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 7)
I
IH
High Level Input V
CC
=Max J,K 20
Current V
I
=2.7V Clock 20 µA
Preset 40
Clear 40
I
IL
Low Level Input V
CC
=Max J, K −0.4
Current V
I
=0.4V Clock −0.4 mA
Preset −0.8
Clear −0.8
I
OS
Short Circuit V
CC
=Max DM54 −20 −100 mA
Output Current (Note 8) DM74 −20 −100
I
CC
Supply Current V
CC
=Max (Note 9) 4 8 mA
Switching Characteristics
at V
CC
=5V and T
A
=25˚C
From (Input) R
L
=2kΩ
Symbol Parameter To (Output) C
L
=15 pF C
L
=50 pF Units
Min Max Min Max
f
MAX
Maximum Clock 25 20 MHz
Frequency
t
PLH
Propagation Delay Time Clock to 25 35 ns
Low to High Level Output Q or Q
t
PHL
Propagation Delay Time Clock to 30 35 ns
High to Low Level Output Q or Q
t
PLH
Propagation Delay Time Clear 25 35 ns
Low to High Level Output to Q
t
PHL
Propagation Delay Time Clear 30 35 ns
High to Low Level Output to Q
t
PLH
Propagation Delay Time Preset 25 35 ns
Low to High Level Output to Q
t
PHL
Propagation Delay Time Preset 30 35 ns
High to Low Level Output to Q
Note 7: All typicals are at VCC =5V, TA=25˚C.
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO=2.25V and 2.125V for DM54 and DM74
series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 9: ICC is measured with all outputs open, with CLOCK grounded after setting the Q and Q outputs high in turn.
3 www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54LS109DMQB or DM54LS109AJ
Package Number J16A
16-Lead Small Outline Molded Package (M)
Order Number DM74LS109AM
Package Number M16A
www.fairchildsemi.com 4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS109AN
Package Number N16E
16-Lead Ceramic Flat Package
Order Number 54LS109FMQB or DM54LS109AW
Package Number W16A
5 www.fairchildsemi.com
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor
Corporation
Americas
Customer Response Center
Tel: 1-888-522-5372
www.fairchildsemi.com
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Europe Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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Tel: +852 2737-7200
Fax: +852 2314-0061
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary
Outputs
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
