APW7080 4A, 26V, 380kHz, Asynchronous Step-Down Converter General Description Features * * * * * * * * * * * * Wide Input Voltage from 4.5V to 26V Output Current up to 4A The APW7080 is a 4A, asynchronous, step-down converter with integrated 80m P-channel MOSFET. The Adjustable Output Voltage from 0.8V to 90% VIN - 0.8V Reference Voltage device, with current-mode control scheme, can convert 4.5~26V input voltage to the output voltage adjustable - 2.5% System Accuracy 80m Integrated P-Channel Power MOSFET from 0.8 to 90% VIN to provide excellent output voltage regulation. High Efficiency up to 91% - Pulse-Skipping Mode (PSM) / PWM Mode Op- The APW7080 regulates the output voltage in automatic PSM/PWM mode operation, depending on the output eration Current-Mode Operation current, for high efficiency operation over light to full load current. The APW7080 is also equipped with power-on- - Stable with Ceramic Output Capacitors - Fast Transient Response reset, soft-start, and whole protections (under-voltage, over-temperature, and current-limit) into a single package. Power-On-Reset Monitoring Fixed 380kHz Switching Frequency in PWM Mode In shutdown mode, the supply current drops below 5A. This device, available in a 8-pin SOP-8P package, pro- Built-in Digital Soft-Start Output Current-Limit Protection with Frequency vides a very compact system solution with minimal external components and good thermal conductance. Foldback 70% Under-Voltage Protection 100 Over-Temperature Protection <5A Quiescent Current During Shutdown 90 Thermal-Enhanced SOP-8P Package Lead Free and Green Devices Available 70 80 Efficiency (%) * * * (RoHS Compliant) Applications * * * * * * * VOUT =5V VOUT =3.3V 60 50 40 30 20 LCD Monitor / TV 10 Set-Top Box Portable DVD 0.001 0.01 0.1 1 10 Output Current, IOUT (A) Wireless LAN ADSL, Switch HUB Notebook Computer Step-Down Converters Requiring High Efficiency and 4A Output Current ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 1 www.anpec.com.tw APW7080 Ordering and Marking Information Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7080 Assembly Material Handling Code Temperature Range Package Code APW7080 XXXXX APW7080 KA : XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration Simplified Application Circuit C1 10F VIN EN UGND VCC 8 1 2 3 9 LX 4 7 6 5 C3 SOP-8P LX R4 C6 The Pin 5 must be connected to the Exposed Pad C5 VIN Supply Voltage (VIN to GND) VLX LX to GND Voltage VCC VCC Supply Voltage (VCC to GND) R1 1% FB R2 1% C4 22F C7 (Optional) (Note 1) Parameter VIN GND VOUT +3.3V D1 EN COMP (Top View) Symbol L1 4A U1 APW7080 VIN Absolute Maximum Ratings C2 VIN VCC UGND GND FB COMP LX VIN +12 Rating Unit -0.3 ~ 30 V > 100ns -2 ~ VIN+0.3 < 100ns -5 ~ VIN+6 VIN > 6.2V -0.3 ~ 6.5 VIN 6.2V < VIN+0.3 V V VUGND_GND UGND to GND Voltage -0.3 ~ VIN+0.3 V VVIN_UGND VIN to UGND Voltage -0.3 ~ 6.5V V -0.3 ~ 20 V EN to GND Voltage FB, COMP to GND Voltage -0.3 ~ VCC +0.3 Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds V 150 o C -65 ~ 150 o C 260 o C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 2 www.anpec.com.tw APW7080 Thermal Characteristics Symbol JA JC Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) SOP-8P Junction-to-Case Resistance in Free Air (Note 3) SOP-8P Unit 50 o 10 o C/W C/W Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package. Recommended Operating Conditions (Note 4) Symbol VIN Parameter 4.5 ~ 26 V VCC Supply Voltage 4.0 ~ 5.5 V 0.8 ~ 90% VIN V Converter Output Voltage IOUT Converter Output Current TJ Unit VIN Supply Voltage VOUT TA Range 0~4 A VCC Input Capacitor 0.22 ~ 2.2 F VIN-to-UGND Input Capacitor 0.22 ~ 2.2 F Ambient Temperature Junction Temperature -40 ~ 85 o -40 ~ 125 o C C Note 4: Refer to the typical application circuits. Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC. Symbol Parameter APW7080 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVIN IVIN_SD IVCC IVCC_SD VIN Supply Current VFB = 0.85V, VEN=3V, LX=Open - 1.0 2.0 mA VIN Shutdown Supply Current VEN = 0V, VIN=26V - - 5 A VCC Supply Current VEN = 3V, VCC = 5.0V, VFB=0.85V - 0.7 - mA VCC Shutdown Supply Current VEN = 0V, VCC = 5.0V - - 1 A VCC 4.2V LINEAR REGULATOR Output Voltage VIN = 5.2 ~ 26V, IO = 0 ~ 8mA 4.0 4.2 4.5 V Load Regulation IO = 0 ~ 8mA -60 -40 0 mV Current-Limit VCC > POR Threshold 8 - 30 mA VIN-TO-UGND 5.5V LINEAR REGULATOR Output Voltage (VVIN-UGND) VIN = 6.2 ~ 26V, IO = 0 ~ 10mA 5.3 5.5 5.7 V Load Regulation IO = 0 ~ 10mA -80 -60 0 mV Current-Limit VIN = 6.2 ~ 26V 10 - 30 mA Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 3 www.anpec.com.tw APW7080 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC. Symbol Parameter APW7080 Test Conditions Unit Min. Typ. Max. VCC rising 3.7 3.9 4.1 V - 0.15 - V VEN rising 2.3 2.5 2.7 V - 0.2 - V - 3.5 - V - 0.2 - V V POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS VCC POR Voltage Threshold VCC POR Hysteresis EN Lockout Voltage Threshold EN Lockout Hysteresis VIN-to-UGND Lockout Voltage Threshold VVIN-UGND rising VIN-to-UGND Lockout Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Output Voltage Accuracy - 0.8 - TJ = 25oC, IOUT=0A, VIN=12V -1.0 - +1.0 TJ = -40 ~ 125oC, IOUT = 0 ~ 4A, VIN = 4.5 ~ 26V -2.5 - +2.5 % Line Regulation VIN = 4.5V to 26V, IOUT = 0A - 0.36 - % Load Regulation IOUT = 0 ~ 4A - 0.4 - % 340 380 420 kHz - 80 - kHz - 93 - % - 200 - ns - 400 - A/V 60 80 - dB - 0.12 - - 80 100 m A OSCILLATOR AND DUTY FOSC Free Running Frequency VIN = 4.5 ~ 26V Foldback Frequency VFB = 0V Maximum Converter's Duty Cycle Minimum Pulse Width of LX VIN = 4.5 ~ 26V CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance Error Amplifier DC Gain COMP = Open Current-Sense Resistance P-channel Power MOSFET Resistance Between VIN and Exposed Pad, TJ=25oC PROTECTIONS ILIM P-channel Power MOSFET Current-limit Peak Current 5.0 6.5 8.0 VUV FB Under-Voltage Threshold VFB falling TOTP 66 70 74 % FB Under-Voltage Hysteresis - 40 - mV FB Under-Voltage Debounce - 2 - s Over-Temperature Trip Point - 150 - o Over-Temperature Hysteresis - 50 - o Soft-Start Interval 9 10.8 12 ms Preceding Delay before Soft-Start 9 10.8 12 ms - - 0.8 V C C SOFT-START, ENABLE, AND INPUT CURRENTS tSS EN Logic Low Voltage Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 VEN falling, VIN = 4 ~ 26V 4 www.anpec.com.tw APW7080 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC. Symbol Parameter APW7080 Test Conditions Unit Min. Typ. Max. SOFT-START, ENABLE, AND INPUT CURRENTS (CONT.) EN Logic High Voltage VEN rising, VIN = 4 ~ 26V 2.1 - - V EN Pin Clamped Voltage IEN=10mA 12 - 17 V P-channel Power MOSFET Leakage Current VEN = 0V, VLX = 0V, VIN = 26V - - 4 A IFB FB Pin Input Current VFB = 0.8V -100 - +100 nA IEN EN Pin Input Current VEN < 3V -500 - +500 nA Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 5 www.anpec.com.tw APW7080 Typical Operating Characteristics Switching Frequency vs. Junction Temperature 420 0.812 410 Switching Frequency, FOSC (kHz) Reference Voltage, VREF (V) Reference Voltage vs. Junction Temperature 0.816 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50 -25 0 25 50 75 400 390 380 370 360 350 340 -50 -25 100 125 150 Junction Temperature, TJ (oC) Output Voltage vs. Output Current 3.36 3.35 IOUT=1A Output Voltage, VOUT (V) Output Voltage, VOUT (V) Output Voltage vs. Supply Voltage 3.36 3.35 3.34 3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.24 VIN=12V 3.34 3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.24 4 6 0.0 8 10 12 14 16 18 20 22 24 26 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Output Current, IOUT (A) VIN Input Current vs. Supply Voltage Current-Limit Level (Peak Current) vs. Junction Temperature 8.0 VFB=0.85V Current-Limit Level, ILIM (A) 1.4 0.5 Supply Voltage, VIN (V) 1.6 VIN Input Current, IVIN (mA) 0 25 50 75 100 125 150 Junction Temperature, TJ (oC) 1.2 1.0 0.8 0.6 0.4 0.2 7.5 7.0 6.5 6.0 5.5 5.0 0.0 0 4 8 12 16 20 24 VIN Supply Voltage, VIN (V) Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 28 -50 -25 6 0 25 50 75 100 125 150 Junction Temperature, TJ (oC) www.anpec.com.tw APW7080 Typical Operating Characteristics (Cont.) Efficiency vs. Output Current EN Clamp Voltage vs. EN Input Current 100 18 16 90 70 EN Clamp Voltage, V EN (V) Efficiency (%) 80 VOUT=5V VOUT=3.3V 60 50 40 30 VIN=12v, L=10H (DCR=50m) C1=10F, C4=22F 20 10 0.001 14 12 TJ = -30oC 10 TJ = 25oC 8 TJ = 100oC 6 4 2 0 0.01 0.1 1 Output Current, IOUT (A) Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 10 1 7 10 100 1000 EN Input Current, IEN (A) 10000 www.anpec.com.tw APW7080 Operating Waveforms (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H) Load Transient Response Load Transient Response I OUT = 50mA -> 3A -> 50mA I OUT rise/f all time=10s I OUT = 0.5A -> 3A -> 0.5A I OUT rise/f all time=10s VOUT 1 VOUT 1 3A 3A IL1 IL1 2 2 0A Ch1: VOUT, 200mV/Div, DC, Voltage Offset = 3.3V Ch2: IL1, 1A/Div, DC Time: 50s/Div 0.5A Ch1: VOUT, 100mV/Div, DC, Voltage Offset = 3.3V Ch2: IL1, 1A/Div, DC Time: 50s/Div Power On Power Off I OUT = 3A 1 I OUT = 3A VIN VIN 1 VOUT VOUT 2 2 3 IL1 3 Ch1: VIN, 5V/Div, DC Ch2: VOUT, 2V/Div, DC Ch3: IL1, 2A/Div, DC Time: 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 IL1 Ch1: VIN, 5V/Div, DC Ch2: VOUT, 2V/Div, DC Ch3: IL1, 2A/Div, DC Time: 5ms/Div 8 www.anpec.com.tw APW7080 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H) Enable Through EN Pin Shutdown Through EN Pin I OUT = 3A I OUT = 3A 1 1 VEN VOUT VOUT 2 2 3 VEN IL1 3 Ch1: VEN, 5V/Div, DC Ch2: VOUT, 2V/Div, DC Ch3: IL1, 2A/Div, DC Time: 5ms/Div IL1 Ch1: VEN, 5V/Div, DC Ch2: VOUT, 2V/Div, DC Ch3: IL1, 2A/Div, DC Time: 5ms/Div Over Current Short Circuit I OUT = 1 -> 6A VOUT is shorted to ground by a short wire VOUT 1 VOUT 1 I L1 IL1 2 2 Ch1: VOUT, 1V/Div, DC Ch2: IL1, 2A/Div, DC Time: 50s/Div Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 Ch1: VOUT, 1V/Div, DC Ch2: IL1, 2A/Div, DC Time: 50ms/Div 9 www.anpec.com.tw APW7080 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H) Switching Waveform Switching Waveform I OUT = 0.2A 3A I OUT = 3A VLX VLX 1 1 IL1 IL1 2 2 Ch1: VLX, 5V/Div, DC Ch2: IL1, 1A/Div, DC Time: 1.25s/Div Ch1: VLX, 5V/Div, DC Ch2: IL1, 2A/Div, DC Time: 1.25s/Div Line Transient Response VOUT VIN = 12V --> 24V --> 24V VIN rise/f all time=20 s 1 VIN 24V 12V 2 Ch1: VOUT, 50mV/Div, DC, Voltage Offset = 3.3V Ch2: VIN, 5V/Div, DC, Voltage Offset = 12V Time: 50s/Div Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 10 www.anpec.com.tw APW7080 Pin Description PIN NO. FUNCTION NAME Power Input. VIN supplies the power (4.5V to 26V) to the control circuitry, gate driver and step-down converter switch. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and GND eliminates switching noise and voltage ripple on the input to the IC. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Pull up with 100k resistor for automatic start-up. 1 VIN 2 EN 3 UGND Gate driver power ground of the P-channel Power MOSFET. A linear regulator regulates a 5.5V voltage between VIN and UGND to supply power to P-channel MOSFET gate driver. Connect a ceramic capacitor (1F typ.) between VIN and UGND for noise decoupling and stability of the linear regulator. 4 VCC Bias input and 4.2V linear regulator's output. This pin supplies the bias to some control circuits. The 4.2V linear regulator converts the voltage on VIN to 4.2V to supply the bias when no external 5V power supply is connected with VCC. Connect a ceramic capacitor (1F typ.) between VCC and GND for noise decoupling and stability of the linear regulator. 5 LX 6 COMP Output of error amplifier. Connect a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required for noise decoupling. 7 FB Feedback Input. The IC senses feedback voltage via FB and regulate the voltage at 0.8V. Connecting FB with a resistor-divider from the output set the output voltage in the range from 0.8V to 90% VIN. 8 GND 9 (Exposed Pad) LX Power Switching Output. Connect this pin to the underside Exposed Pad. Power and Signal Ground. Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output. The Exposed Pad provides current with lower impedance than Pin 5. Connect the pad to output LC filter via a top-layer thermal pad on PCBs. The PCB will be a heat sink of the IC. Block Diagram VIN Current Sense Amplifier 4.2V Regulator and Power-On-Reset VCC Current -Limit VCC POR 70%VREF UVP UG Soft-Start and Fault Logic Soft-Start Gate Driver Inhibit UGND Gate Control FB VREF 0.8V Error Amplifier COMP Slope Compensation ENOK 2.5V EN LX Current Compartor Enable 0.8V Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 OverTemperature Protection FB 11 Oscillator 380kHz VIN Linear Regulator GND www.anpec.com.tw APW7080 Typical Application Circuit 1. 4.5~26V Single Power Input Step-down Converter (with Ceramic Input/Output Capacitors) C1 10F 1 VIN 4 VCC UGND C3 1F VIN 3 C2 1F VIN 4.5~26V L1 4A 9 LX LX 5 R5 100k 2 6 U1 APW7080 D1 R1 1% EN COMP R4 FB 7 R2 1% GND 8 C6 VOUT 0.8V~90%VIN/4A C4 22F C7 (Optional) C5 Recommended Feedback Compensation Network Components List: VIN (V) VOUT (V) L1 (H) C4 (F) C4 ESR (m) R1 (k) R2 (k) C7 (pF) R4 (k) C5 (pF) C6 (pF) 24 12 15 22 5 140 10 22 62 820 22 24 12 15 44 3 140 10 22 120 820 22 24 5 10 22 5 63.4 12 33 24 1500 22 24 5 10 44 3 63.4 12 33 51 1500 22 12 5 10 22 5 63.4 12 68 24 820 22 12 5 10 44 3 63.4 12 68 51 820 22 12 3.3 10 22 5 47 15 82 15 1000 22 12 3.3 10 44 3 47 15 82 33 1000 22 12 2 4.7 22 5 30 20 56 10 2200 22 12 2 4.7 44 3 30 20 56 20 2200 22 12 1.2 3.3 22 5 7.5 15 150 6.2 3300 22 12 1.2 3.3 44 3 7.5 15 150 12 3300 22 5 3.3 3.3 22 5 47 15 68 15 560 22 5 3.3 3.3 44 3 47 15 68 33 560 22 5 1.2 2.2 22 5 7.5 15 270 5.6 1500 22 5 1.2 2.2 44 3 7.5 15 270 12 1500 22 5 0.8 2.2 22 5 0 NC NC 2.7 2700 22 5 0.8 2.2 44 3 0 NC NC 6.2 2700 22 Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 12 www.anpec.com.tw APW7080 Typical Application Circuit (Cont.) 2. Dual Power Inputs Step-down Converter (VIN=4.5~26V) +5V C1 10F D2 Schottky Diode 1 4 VCC UGND C3 1F LX LX R5 100k VIN C2 1F VIN 2 6 3 L1 4A 9 5 U1 APW7080 R4 FB R1 1% 7 R2 1% GND 8 C6 VOUT 0.8V~90%VIN/4A C4 22F D1 EN COMP VIN 4.5~26V C7 (Optional) C5 3. 4.5~5.5V Single Power Input Step-down Converter C1 10F 1 VIN 4 VCC UGND C3 1F LX VIN R5 100k 2 6 3 C2 1F L1 4A 9 U1 LX 5 APW7080 D1 R1 1% EN COMP R4 C6 GND 8 FB 7 VOUT 0.8V~90%VIN/4A C4 22F R2 1% C7 (Optional) C5 Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 VIN 4.5~5.5V 13 www.anpec.com.tw APW7080 Typical Application Circuit (Cont.) 4. +12V Single Power Input Step-down Converter (with Electrolytic Input/Output Capacitors) VIN C8 +12V 470F C1 2.2F 1 C2 1F VIN 4 VCC UGND C3 1F VIN LX LX R5 100k 2 VOUT +3.3V/4A D1 R1 47k 1% EN COMP R4 56k C5 4700pF L1 10H 4A 9 5 U1 APW7080 6 C6 22pF 3 FB 7 R2 15k 1% GND 8 C4 470F (ESR=30m) C7 33pF 5. -8V Inverting Converter with 4.5~5.5V Single Power Input VIN 4.5~5.5V 1 VIN R5 100k 2 4 C3 1F C6 22pF 6 UGND EN 3 9 LX LX 5 VCC U1 APW7080 COMP R4 39k C5 560pF GND 8 FB 7 C2 1F C1 10F L1 6.8H D1 4A R1 90.9k R2 10k PGND C8 1F AGND C7 27pF C4 22F VOUT -8V/4A Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 14 www.anpec.com.tw APW7080 Function Description Main Control Loop physically close to the IC to provide good noise The APW7080 is a constant frequency current mode switching regulator. During normal operation, the internal decoupling. The linear regulator is not intended for powering up any external loads. Do not connect any P-channel power MOSFET is turned on each cycle when the oscillator sets an internal RS latch and would be turned external loads to VCC. The linear regulator is also equipped with current-limit protection to protect itself dur- off when an internal current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets ing over-load or short-circuit conditions on VCC pin. VIN-to-UGND 5.5V Linear Regulator the RS latch is controlled by the voltage on the COMP pin, which is the output of the error amplifier (EAMP). An The built-in 5.5V linear regulator regulates a 5.5V voltage between VIN and UGND pins to supply bias and gate charge for the P-channel Power MOSFET gate driver. The external resistive divider connected between VOUT and ground allows the EAMP to receive an output feedback linear regulator is designed to be stable with a low-ESR ceramic output capacitor of at least 0.22F. It is also voltage VFB at FB pin. When the load current increases, it causes a slight decrease in V FB relative to the 0.8V equipped with current-limit function to protect itself during over-load or short-circuit conditions between VIN reference, which in turn causes the COMP voltage to increase until the average inductor current matches the and UGND. new load current. The APW7080 shuts off the output of the converters when the output voltage of the linear regulator is below 3.5V VCC Power-On-Reset(POR) and EN Under-voltage Lockout The APW7080 keeps monitoring the voltage on VCC pin (typical). The IC resumes working by initiating a new softstart process when the linear regulator's output voltage to prevent wrong logic operations which may occur when VCC voltage is not high enough for the internal control is above the undervoltage lockout voltage threshold. Digital Soft-Start circuitry to operate. The VCC POR has a rising threshold of 3.9V (typical) with 0.15V of hysteresis. The APW7080 has a built-in digital soft-start to control the output voltage rise and limit the input current surge An external under-voltage lockout (UVLO) is sensed and during start-up. During soft-start, an internal ramp, connected to the one of the positive inputs of the error programmed at the EN pin. The EN UVLO has a rising threshold of 2.5V with 0.2V of hysteresis. The EN UVLO amplifier, rises up from 0V to 1V to replace the reference voltage (0.8V) until the ramp voltage reaches the reference should be programmed by connecting a resistive divider from VIN to EN to GND. voltage. After the VCC, EN, and VIN-to-UGND voltages exceed their The device is designed with a preceding delay about 10.8ms (typical) before soft-start process. respective voltage thresholds, the IC starts a start-up process and then ramps up the output voltage to the Output Under-Voltage Protection setting of output voltage. Connect a RC network from EN to GND to set a turn-on delay that can be used to sequence In the process of operation, if a short-circuit occurs, the the output voltages of multiple devices. output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the VCC 4.2V Linear Regulator required regulation range. The under-voltage continually monitors the FB voltage after soft-start is completed. If a VCC is the output terminal of the internal 4.2V linear regulator which is powered from VIN and provides power to the APW7080. The linear regulator is designed to be load step is strong enough to pull the output voltage lower than the under-voltage threshold, the IC shuts down stable with a low-ESR ceramic output capacitor powers the internal control circuitry. Bypass VCC to GND with a converter's output. ceramic capacitor of at least 0.22F. Place the capacitor The under-voltage threshold is 70% of the nominal out- Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 15 www.anpec.com.tw APW7080 Function Description (Cont.) Output Under-Voltage Protection (Cont.) put voltage. The under-voltage comparator has a built-in 2s noise filter to prevent the chips from wrong UVP shutdown caused by noise. The under-voltage protection works in a hiccup mode without latched shutdown. The IC will initiate a new soft-start process at the end of the preceeding delay. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7080. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the power MOSFET, allowing the devices to cool. The thermal sensor allows the converter to start a start-up process and regulate the output voltage again after the junction temperature is cooled by 50 oC. The OTP is designed with a 50oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the IC. Enable/Shutdown Driving EN to ground places the APW7080 in shutdown. When in shutdown, the internal power MOSFET turns off, all internal circuitry shuts down and the quiescent supply current of VIN reduces to <1A (typical). Current-Limit Protection The APW7080 monitors the output current, flowing through the P-channel power MOSFET, and limits the current peak at current-limit level to prevent loads and the IC from damages during overload or short-circuit conditions. Frequency Foldback When the output is shortened to ground, the frequency of the oscillator will be reduced to about 80kHz. This lower frequency allows the inductor current to safely discharge, thereby preventing current runaway. The oscillator's frequency will gradually increase to its designed rate when the feedback voltage on FB again approaches 0.8V. Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 16 www.anpec.com.tw APW7080 Application Information Power Sequencing VIN VIN IQ1 The APW7080 can operate with sigle or dual power input(s). In dual-power applications, the voltage (VCC) applied at CIN Q1 VCC pin must be lower than the voltage (VIN) on VIN pin. The reason is the internal parasitic diode from VCC to VIN IL LX IOUT VOUT L will conduct due to the forward-voltage between VCC and VIN. Therefore, VIN must be provided before VCC. ICOUT D1 ESR COUT Setting Output Voltage The regulated output voltage is determined by: T=1/F OSC VOUT R1 = 0.8 (1 + ) R2 (V) VLX Suggested R2 is in the range from 1K to 20k. For portable applications, a 10k resistor is suggested for DT I IOUT R2. To prevent stray pickup, locate resistors R1 and R2 close to APW7080. IL IOUT Input Capacitor Selection IQ1 It is necessary to turn on the P-channel power MOSFET I (Q1) each time when using small ceramic capacitors for high frequency decoupling and bulk capacitors to sup- ICOUT VOUT ply the surge current. Place the small ceramic capcaitors physically close to the VIN and between VIN and the anVOUT ode of the Schottky diode (D1) Figure 1. Converter Waveforms The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable Output Capacitor Selection operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and An output capacitor is required to filter the output and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than supply the load transient current. The filtering requirements are the function of the switching frequency and the ripple the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current (IRMS) current (I). The output ripple is the sum of the voltages, having phase shift, across the ESR and the ideal output capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations: of the bulk input capacitor is calculated as the following equation: IRMS = IOUT D (1- D) (A) where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be D= VOUT + VD VIN + VD ........... (1) I = VOUT *(1 - D) FOSC *L ........... (2) VESR = I *ESR ........... (3) (V) where VD is the forward voltage drop of the diode. exercised with regard to the capacitor surge current rating. The peak-to-peak voltage of the ideal output capacitor is calculated as the following equation: Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 17 www.anpec.com.tw APW7080 Application Information (Cont.) Output Capacitor Selection (Cont.) I VCOUT = (V) 8 FOSC COUT and greater core losses. A reasonable starting point for setting ripple current is I 0.4 IOUT(MAX) . Remember, the maximum ripple current occurs at the maximum input ........... (4) For the applications using bulk capacitors, the V COUT voltage. The minimum inductance of the inductor is calculated by using the following equation: is much smaller than the V ESR and can be ignored. Therefore, the AC peak-to-peak output voltage (VOUT ) is VOUT *(VIN - VOUT) 1.6 380000 *L *VIN shown as below: VOUT = I ESR (V) ........... (5) L For the applications using ceramic capacitors, the VESR is much smaller than the V COUT and can be ignored. VOUT *(VIN - VOUT) 608000 *VIN (H) ........... (6) where VIN = VIN(MAX) Therefore, the AC peak-to-peak output voltage (VOUT ) is close to VCOUT . Output Diode Selection The Schottky diode carries load current during the off- The load transient requirements are the function of the time. The average diode current is therefore dependent on the P-channel power MOSFET duty cycle. At high input slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a voltages, the diode conducts most of the time. As VIN approaches VOUT, the diode conducts only a small fraction of mix of capacitors and careful layout. High frequency capacitors initially supply the transient and slow the the time. The most stressful condition for the diode is when the output is short-circuited. Therefore, it is impor- current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR tant to adequately specify the diode peak current and average power dissipation so as not to exceed the diode (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. ratings. High frequency decoupling capacitors should be placed Under normal load conditions, the average current conducted by the diode is: as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit ID = board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic VIN - VOUT IOUT VIN + VD The APW7080 is equipped with whole protections to re- capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equiva- duce the power dissipation during short-circuit condition. Therefore, the maximum power dissipation of the diode lent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the ca- is calculated from the maximum output current as: pacitor to high slew-rate transient loading. PDIODE(MAX) = VD *ID(MAX) Inductor Value Calculation where The operating frequency and inductor selection are interrelated in that higher operating frequencies permit IOUT = IOUT(MAX) Remember to keep lead length short and observe proper grounding to avoid ringing and increased dissipation. the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances but results in higher output voltage ripple Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 18 www.anpec.com.tw APW7080 Layout Consideration In high power switching regulator, a correct layout is im- 5. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. The bulk capacitors C8 are portant to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized also placed near VIN. Use a wide power ground plane to connect the C1, C8, C4, and Schottky diode to pro- by using short, wide printed circuit traces. Signal and power grounds are to be kept separating and finally com- vide a low impedance path between the components for large and high slew rate current. bined using ground plane construction or single point grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: 8 7 6 5 D1 SOP-8P VOUT L1 VLX 1 2 3 4 C1 flow path. If possible, make all the connections on one side of the PCB with wide, copper filled areas. C4 1. Begin the layout by placing the power components first. Orient the power circuitry to achieve a clean power VIN Load 2. In Figure 2, the loops with same color bold lines conGND duct high slew rate current. These interconnecting impedances should be minimized by using wide and GND Figure 3. Recommended Layout Diagram short printed circuit traces. 3. Keep the sensitive small signal nodes (FB, COMP) away from switching nodes (LX or others) on the PCB. Thermal Consideration In Figure 4, the SOP-8P is a cost-effective package featuring a small size, like a standard SOP-8, and a bottom Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. switching noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedi- The exposed pad must be soldered to the top VLX plane. The copper of the VLX plane on the Top layer conducts cated ground trace. 4. The VCC decoupling capacitor should be right next to the VCC and GND pins. Capacitor C2 should be con- heat into the PCB and air. Please enlarge the area of VLX plan to reduces the case-to-ambient resistance (CA). nected as close to the VIN and UGND pins as possible. 102 mil 1 + VIN - C2 1 VIN LX 5 3 UGND LX 9 4 VCC C3 C6 R4 C5 Compensation Network 2 U1 APW7080 2 EN 6 COMP FB 7 GND 8 C1 C8 118 mil L1 + D1 3 8 SOP-8P 7 6 5 4 C4 Load VOUT R1 Die R2 Exposed Pad Top VLX plane C7 (Optional) Feedback Divider Ambient Air PCB Figure 2. Current Path Diagram Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 Figure 4. 19 www.anpec.com.tw APW7080 Package Information SOP-8P -T- SEATING PLANE < 4 mils D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE L VIEW A S Y M B O L A SOP-8P INCHES MILLIMETERS MAX. MIN. MIN. MAX. 1.60 0.063 0.000 0.15 0.006 A1 0.00 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 D1 2.50 3.50 0.098 0.138 0.244 0.049 E 5.80 6.20 0.228 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0o C 8o C 0oC 8o C Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 20 www.anpec.com.tw APW7080 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D W E1 F 330.02.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.00.30 1.750.10 5.50.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.00.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.400.20 5.200.20 2.10 0.20 SOP- 8P 4.00.10 8.00.10 (mm) Devices Per Unit Package Type Unit Quantity SOP- 8P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 21 www.anpec.com.tw APW7080 Taping Direction Information SOP-8P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 22 www.anpec.com.tw APW7080 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3 C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 C Volume mm 350 220 C 2.5 mm 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 23 Description 5 Sec, 245C 1000 Hrs, Bias @ Tj=125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV VMM200V 10ms, 1tr100mA www.anpec.com.tw APW7080 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.9 - Nov., 2010 24 www.anpec.com.tw