HN58V256AI Series
256k EEPROM (32-kword × 8-bit)
Wide Temperature Range version
ADE-203-616C (Z)
Rev. 3.0
Oct. 24, 1997
Description
The Hitachi HN58V256A is electrically erasable and programmable ROM organized as 32768-word × 8-
bit. It has realized high speed low power consumption and high reliability by employing advanced MNOS
memory technology and CMOS process and circuitry technology. They also have a 64-byte page
programming function to make their write operations faster.
Features
• Single 3 V supply: 2.7 to 5.5
• Access time: 120 ns max
• Power dissipation:
Active: 20 mW/MHz, (typ)
Standby: 110 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic byte write: 10 ms max
• Automatic page write (64 bytes): 10 ms max
• Data polling and Toggle bit
• Data protection circuit on power on/off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
• 105 erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Operating temperature range: –40 to 85°C
HN58V256AI Series
2
Ordering Information
Type No. Access time Package
HN58V256AFPI-12 120 ns 400 mil 28-pin plastic SOP (FP-28D)
HN58V256ATI-12 120 ns 28-pin plastic TSOP (TFP-28DB)
Pin Arrangement
HN58V256AFPI Series HN58V256ATI Series
(Top view)
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A3
A4
A5
A6
A7
A12
A14
VCC
WE
A13
A8
A9
A11
OE
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HN58V256AI Series
3
Pin Description
Pin name Function
A0 to A14 Address input
I/O0 to I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
VCC Power supply
VSS Ground
Block Diagram
V
V
OE
CE
A5
A0
A6
A14
WE
CC
SS
I/O0 I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
to
to
to
HN58V256AI Series
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Operation Table
Operation CE OE WE I/O
Read VIL VIL VIH Dout
Standby VIH ×*2×High-Z
Write VIL VIH VIL Din
Deselect VIL VIH VIH High-Z
Write inhibit ××V
IH —
×VIL ×—
Data polling VIL VIL VIH Dout (I/O7)
Notes: 1. Refer to the recommended DC operating condition.
2. × : Don’t care
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS VCC –0.6 to +7.0 V
Input voltage relative to VSS Vin –0.5*1 to +7.0*3V
Operating temperature range*2Topr –40 to +85 °C
Storage temperature range Tstg –55 to +125 °C
Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns
2. Including electrical characteristics and data retention
3. Should not exceed VCC + 1 V.
HN58V256AI Series
5
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 2.7 3.0 5.5 V
VSS 000V
Input voltage VIL –0.3*1— 0.6 V
VIH 2.4*3—V
CC + 0.3*2V
Operating temperature Topr –40 — 85 °C
Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.
2. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns.
3. VIH min: 3.0 V at VCC = 3.6 to 5.5V
DC Characteristics (Ta = –40 to +85°C, VCC = 2.7 to 5.5 V)
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI ——2 µAV
CC = 5.5 V, Vin = 5.5 V
Output leakage current ILO ——2 µAV
CC = 5.5 V, Vout = 5.5/0.4 V
VCC current (standby) ICC1 ——20µACE = VCC
ICC2 ——1 mACE = VIH
VCC current (active) ICC3 — — 8 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 µs at VCC = 3.6 V
— — 12 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 µs at VCC = 5.5 V
— — 15 mA Iout = 0 mA, Duty = 100%,
Cycle = 120 ns at VCC = 3.6 V
— — 30 mA Iout = 0 mA, Duty = 100%,
Cycle = 120 ns at VCC = 5.5 V
Output low voltage VOL — — 0.4 V IOL = 2.1 mA
Output high voltage VOH VCC × 0.8 — — V IOH = –400 µA
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*1Cin — — 6 pF Vin = 0 V
Output capacitance*1Cout — — 12 pF Vout = 0 V
Note: 1. This parameter is periodically sampled and not 100% tested.
HN58V256AI Series
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AC Characteristics (Ta = – 40 to + 85°C, VCC = 2.7 to 5.5 V)
Test Conditions
• Input pulse levels: 0.4 V to 2.4 V (VCC ≤ 3.6V), 0.4V to 3.0 V (VCC > 3.6 V)
• Input rise and fall time: ≤ 5 ns
• Input timing reference levels: 0.8, 1.8 V
• Output load: 1TTL Gate +100 pF
• Output reference levels: 1.5 V, 1.5 V
Read Cycle
HN58V256AI -12
Parameter Symbol Min Max Unit Test conditions
Address to output delay tACC — 120 ns CE = OE = VIL, WE = VIH
CE to output delay tCE — 120 ns OE = VIL, WE = VIH
OE to output delay tOE 10 60 ns CE = VIL, WE = VIH
Address to output hold tOH 0—nsCE = OE = VIL, WE = VIH
OE (CE) high to output float*1tDF 040nsCE = VIL, WE = VIH
HN58V256AI Series
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Write Cycle
Parameter Symbol Min*2Typ Max Unit Test conditions
Address setup time tAS 0 ——ns
Address hold time tAH 50——ns
CE to write setup time (WE controlled) tCS 0 ——ns
CE hold time (WE controlled) tCH 0 ——ns
WE to write setup time (CE controlled) tWS 0 ——ns
WE hold time (CE controlled) tWH 0 ——ns
OE to write setup time tOES 0 ——ns
OE hold time tOEH 0 ——ns
Data setup time tDS 70——ns
Data hold time tDH 0 ——ns
WE pulse width (WE controlled) tWP 200 — — ns
CE pulse width (CE controlled) tCW 200 — — ns
Data latch time tDL 100 — — ns
Byte load cycle tBLC 0.3 — 30 µs
Byte load window tBL 100 — — µs
Write cycle time tWC — — 10*3ms
Write start time tDW 0*4——ns
Notes: 1. tDF is defined as the time at which the outputs achieve the open circuit conditions and are no
longer driven.
2. Use this device in longer cycle than this value.
3. tWC must be longer than this value unless polling techniques is used. This device automatically
completes the internal write operation within this value.
4. Next read or write operation can be initiated after tDW if polling techniques is used.
5. A16 through A14 are page addresses and these addresses are latched at the first falling edge of
WE.
6. A16 through A14 are page addresses and these addresses are latched at the first falling edge of
CE.
7. See AC read Characteristics.
HN58V256AI Series
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Timing Waveforms
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
tACC
tCE
tOE
tOH
tDF
HN58V256AI Series
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Byte Write Timing Waveform (1) (WE Controlled)
Address
CE
WE
OE
Din
tWC
tCH
tAH
tCS
tAS tWP
tOEH
tBL
tOES
tDS tDH
Byte Write Timing Waveform (2) (CE Controlled)
Address
CE
WE
OE
Din
tWC
tAH
tWS
tAS
tOEH
tWH
tOES
tDS tDH
tCW
tBL
HN58V256AI Series
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Page Write Timing Waveform (1) (WE Controlled)
Address
A0 to A14
WE
CE
OE
Din
tAS tAH tBL
tWC
tOEH
tDH
tOES
tCH
tCS
tWP
tDL tBLC
tDS
*5
Page Write Timing Waveform (2) (CE Controlled)
Address
A0 to A14
WE
CE
OE
Din
tAS tAH tBL
tWC
tOEH
tDH
tOES
tWH
tWS
tCW
tDL tBLC
tDS
*6
HN58V256AI Series
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Data Polling Timing Waveform
tCE
tOEH
tWC
tDW
tOES
Address
CE
WE
OE
I/O7
tOE
Din X
An An
Dout XDout X
*7
*7
An
HN58V256AI Series
12
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set
to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each
read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be
accessible for next read or program.
Toggle bit Waveform
Notes: 1. I/O6 beginning state is “1”.
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any address location can be used, but the address must be fixed.
WE
tOES
OE
CE
Dout
I/O6 Dout Dout Dout
Next mode
tOE
tCE
tDW
tWC
tOEH
*1 *2 *2
Address
*3
*3
*4
Din
HN58V256AI Series
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Software Data Protection Timing Waveform (1) (in protection mode)
V
CE
WE
Address
Data 5555
AA 2AAA
55 5555
A0
tBLC tWC
CC
Write address
Write data
Software Data Protection Timing Waveform (2) (in non-protection mode)
V
CE
WE
Address
Data
tWC
CC Normal active
mode
5555
AA 2AAA
55 5555
80 5555
AA 2AAA
55 5555
20
HN58V256AI Series
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Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write
cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE.
When CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the
input data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read
mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the
EEPROM is performing a write operation.
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the
rising edge of WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte
programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is
page-programmed less than 104 cycles.
HN58V256AI Series
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Data Protection
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake.
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20
ns or less.
Be careful not to allow noise of a width of more than 20 ns on the control pins.
WE
CE
OE
V
0 V
V
0 V
20 ns max
IH
IH
2. Data Protection at VCC On/Off
When V CC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as
a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming,
the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.
Note: The EEPROM should be kept in unprogr ammable state during VCC on/off by using CPU RESET
signal.
VCC
CPU
RESET
Unprogrammable Unprogrammable
**
HN58V256AI Series
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(1) Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the table
below.
CE VCC ××
OE ×VSS ×
WE ×× V
CC
×: Don’t care.
VCC: Pull-up to VCC level.
VSS: Pull-down to VSS level.
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP
is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes
code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data.
Data
AA
↓
55
↓
A0
↓
Write data }
Address
5555
↓
2AAA
↓
5555
↓
Write address Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can not be written.
Data
AA
↓
55
↓
80
↓
AA
↓
55
↓
20
Address
5555
↓
2AAA
↓
5555
↓
5555
↓
2AAA
↓
5555
The software data protection is not enabled at the shipment.
Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence of
software data protection. If there are any questions , please contact with Hitachi sales offices.
HN58V256AI Series
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Package Dimensions
HN58V256AFPI Series (FP-28D)
0° – 8°
0.17 ± 0.05
1.0 ± 0.2
0.20 ± 0.10
2.50 Max
8.4
18.3
18.8 Max
1.12 Max
28 15
114 11.8 ± 0.3
1.7
0.20
0.15
M
1.27
0.40 ± 0.08
0.38 ± 0.06
0.15 ± 0.04
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-28D
Conforms
—
0.7 g
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58V256AI Series
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Package Dimensions (cont.)
HN58V256ATI Series (TFP-28DB)
0.10 M
0.55
8.00
0.22 ± 0.08
13.40 ± 0.30
0.17 ± 0.05
0.13
1.20 Max
11.80
0° – 5°
28
114
15
8.20 Max
0.10
+0.07
–0.08
0.50 ± 0.10
0.80
0.45 Max
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
TFP-28DB
—
—
0.23 g
0.20 ± 0.06
0.15 ± 0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58V256AI Series
19
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
HN58V256AI Series
20
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
1.0 Jul. 9, 1996 Initial issue Y. Nagai T. Wada
2.0 Mar. 18, 1997 Recommended DC Operating Conditions
VIH (min): 3.0 V to 2.4 V
Functional Description
Data Protection 3: Addition of note
Data Protection 3:
Change figures of Software data protection
Y. Nagai K. Furusawa
3.0 Oct. 24, 1997 Timing Waveforms
Read Timing Waveform: Correct error
