Arria 10 Device Overview
2013.09.04
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Altera’s Arria®FPGAs and SoCs deliver optimal performance and power efficiency in the midrange. By
using TSMC's 20-nm process technology on a high-performance architecture, Arria 10 FPGAs and SoCs
deliver higher performance than previous-generation high-end FPGAs while simultaneously reducing power
by offering a comprehensive set of power-saving technologies. Altera's Arria 10 family is reinventing the
midrange.
Altera’s Arria 10 SoCs offer a second generation SoC product that both demonstrates a long-term commitment
to the SoC product line and extends Altera’s leadership in programmable devices that feature the ARM-
based hard processor system (HPS).
Important innovations in Arria 10 devices include:
•Enhanced core architecture delivering 60% higher performance than the previous generation midrange
(15% higher performance than previous fastest high-end FPGAs)
•Integrated transceivers with short reach rates up to 28.05 Gbps and backplane capability up to 17.4 Gbps
•Hard PCI Express Gen3 intellectual property (IP) blocks
•Hard memory controllers and PHY up to 2666 Mbps
•Variable precision digital signal processing (DSP) blocks
•Fractional synthesis PLLs
•Up to 40% lower power compared to prior midrange FPGAs and up to 60% lower power compared to
prior generation high-end FPGAs due to a comprehensive set of advanced power-saving features
•2nd generation ARM®Cortex™-A9 hard processor system (HPS) for SoC variants
•Integrated 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC)
Arria 10 devices are ideally suited for high performance, power-sensitive, midrange applications in such
diverse markets as:
•Wireless—for channel and switch cards in remote radio heads and mobile backhaul
•Broadcast—for studio switches, servers and transport, videoconferencing, and pro audio/video
•Wireline—for 40G/100G muxponders and transponders, 100G line cards, bridging, and aggregation
•Compute and Storage—for flash cache, cloud computing servers, and server acceleration
•Medical—for diagnostic scanners and diagnostic imaging
•Military—for missile guidance and control, radar, electronic warfare, and secure communications
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Arria 10 Family Variants
Arria 10 devices are available in GX, GT, and SX variants.
•Arria 10 GX devices deliver over 500 MHz core fabric performance and 2666 Mbps DDR4 external
memory interface performance across the industrial temperature range, while providing over 1.1 million
logic elements and 96 general purpose transceivers. Every transceiver is capable of 17.4 Gbps for short
reach applications and 16.0 Gbps across the backplane. These devices are optimized for a broad range of
applications such as wireless remote radio heads, broadcast studio equipment, 40G/100G communication
systems, server acceleration, and medical imaging.
•Arria 10 GT devices have the same core performance and feature set as Arria 10 GX devices, with the
added capability of sixteen 28.05-Gbps short reach transceivers for chip-to-chip and chip-to-module
applications. The 28.05-Gbps transceivers are ideal for interfacing with the emerging CFP2 and CFP4
optical modules that typically require four lanes at data rates in the range of 25 to 28 Gbps. Backplane
driving capability is also increased to 17.4 Gbps in Arria 10 GT devices.
•Arria 10 SX devices have a feature set that is similar to Arria 10 GX devices plus an ARM Cortex-A9
hard processor system.
Common to all Arria 10 family variants is the enhanced logic array utilizing Altera’s adaptive logic module
(ALM) and a rich set of high performance building blocks that includes 20Kbit (M20K) internal memory
blocks, variable precision DSP blocks, fractional synthesis and integer PLLs, hard memory PHY and controllers
for external memory interfaces, and general purpose I/O cells. These building blocks are interconnected by
an updated version of Altera’s superior multi-track routing architecture and comprehensive fabric clocking
network. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic
to be added and removed from the system during operation.
All family variants also contain high speed serial transceivers, containing both the physical medium attachment
(PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard
and proprietary protocols. In addition to the hard PCS, Arria 10 devices contain multiple instantiations of
PCI Express hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8 lane configurations. The hard PCS
and hard PCI Express IP free up valuable core logic resources, save power, and increase productivity for the
user.
Improvements in Arria 10 FPGAs and SoCs
Altera has combined in-house innovations with TSMC's advanced 20-nm process technology to deliver
major improvements over Arria V FPGAs and SoCs in nearly every category.
Table 1: Key Features of Arria 10 Devices Compared to Arria V Devices
Arria 10 FPGAs and SoCsArria V FPGAs and SoCsFeature
20-nm TSMC28-nm TSMCProcess
technology
Dual ARM Cortex-A9 MPCoreDual ARM Cortex-A9 MPCore™
Processor core
1.5 GHz800 MHzProcessor
performance
500 MHz300 MHzLogic core
performance
0.6x1xPower dissipation
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Arria 10 FPGAs and SoCsArria V FPGAs and SoCsFeature
1150 KLE504 KLELogic density
53 Mbits34 MbitsEmbedded
memory
3356218618x19 multipliers
9636Maximum
transceivers
28.05 Gbps10.3125 GbpsMaximum
transceiver data
rate (chip to chip)
DDR4 SDRAM @ 1333 MHz/2666 Mbps
DDR3 SDRAM @ 1067 MHz/2133 Mbps
Hybrid Memory Cube (HMC)
DDR3 SDRAM @ 667 MHz/1333 MbpsMemory devices
supported
3 EMACs
PCI Express Gen3 x8
10GBASE-KR/40GBASE-KR4 FEC
Interlaken PCS
2 EMACs
PCI Express Gen3 x8 (Arria V GZ)
PCI Express Gen2 x4/Gen1 x8 (Arria V
GX/GT/SX/ST)
Hard protocol IP
These features result in the following improvements:
•Improved Core Logic Performance: Arria 10 devices offer over 60% improved core performance compared
to the previous generation
•Improved Processor Performance: Arria 10 SoCs provide 87% improvement in processor performance
•Improved Processor Power Efficiency: At 20 nm, the Dual Core ARM Cortex-A9 Processor provides
the best power efficiency for any GHz-class processor in the industry
•Lower Power: Arria 10 devices deliver up to 40% lower power compared to prior-generation mid-range
FPGAs and SoCs, enabled by 20-nm process technology advancements and a variety of innovative power-
management options
•Higher Density: Arria 10 devices provide a higher level of integration with up to 1150K logic elements
(LEs), up to 53 Mbits of embedded memory, and over 3350 18x19 multipliers
•Improved Transceiver Bandwidth: Arria 10 devices support chip-to-chip rates up to 28 Gbps and
backplane rates up to 17.4 Gbps
•Improved Memory Bandwidth with DDR4 Support: Arria 10 devices support DDR4 memory up to
1333 MHz/ 2666 Mbps and feature support for the emerging transceiver-based Hybrid Memory Cube
(HMC)
•Improved DSP Performance: With over 1.0 TeraFLOPs of single-precision DSP performance, Arria 10
devices deliver a 4 times increase in DSP performance
•Additional Protocol Support for Hard IP: Arria 10 devices feature an advanced transceiver architecture
with added hard IP support for PCIe Gen3, Interlaken PCS, and 10GBASE-KR/40GBASE-KR4 FEC
Target Markets for Arria 10 FPGAs and SoCs
Arria 10 devices meet the performance, power, and bandwidth requirements of next generation wireless
infrastructure, broadcast, compute and storage, networking, and medical and military equipment.
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By providing such a highly integrated device, Arria 10 FPGAs and SoCs significantly reduce BOM cost,
form factor, and power consumption. Arria 10 devices allow you to differentiate your product through
customization by implementing your intellectual property in both hardware and software.
For these applications, Arria 10 devices integrate both logic functions and processor functions in a highly
integrated single device. The integrated ARM-based SoCs provide all the functionality of traditional FPGAs,
eliminate the need for a local processor, and increase system performance by taking advantage of the tightly
coupled high bandwidth interface between the core fabric and the hard processor system.
Figure 1: Arria 10 FPGA and SoC Applications
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•For Wireless infrastructure particularly remote radio unit, the industry has standardized on ARM-based
ASSPs and SoCs for several generations. ARM is widely recognized as the industry leader in low power
solutions. At 20 nm, the Dual ARM Cortex MPCore provides the best power efficiency of any GHz class
of process. When combined with Altera’s industry leading programmable technology, this provides an
ideal platform to address the performance, power, and form factor requirements of wireless remote radio
unit and small cell base stations.
•For Wireline communication equipment such as access, metro, core, and transmission equipment where
the FPGA performs critical functions such as protocol bridging, packet framing, aggregation, and I/O
expansion, SoCs now offer all this as well as integrated intelligent control and link management, sometimes
referred to as Operations, Administration, and Maintenance (OAM). OAM typically is software that
executes when a link is established or fails during operation. The integrated ARM processor can also be
used for statistics and error monitoring and minimize system downtime when a link is compromised or
oversubscribed. Tight coupling of the processor and the data path (implemented in the core logic) saves
time and results in significant savings in terms of operating expenses associated with system downtime
and loss of quality of service.
•For Compute and storage equipment, flash cache storage, the integrated ARM processor can be used
to manage Flash sectors and improve overall life and reliability as well as offload the host processor and
provide control for search and hardware acceleration functions for cloud storage equipment. The integrated
ARM based HPS can configure the hard PCIe interfaces in PCIe root port configuration and also run
link layers for SAS and SATA interfaces.
•For Next generation Broadcast equipment, where “4K readiness”is the key technology driver, the
integrated ARM processor subsystem eliminates the need for a local GHz class processor, which is
commonly used for functions such as audio processing, video compression, video link management, and
PCIe root port.
•For Military applications, new security features such as Secure Boot, Encryption, and Authentication
have been introduced for secure wireless and wireline communications, military radar, military intelligence
equipment.
•For Test and Medical applications, combining ARM HPS with support for high speed memory devices
such as DDR4, and Hybrid Memory Cube (HMC) as well as high speed transceivers and embedded
controllers such as PCIe Gen3, Arria 10 SoCs are ideal for next generation test and medical equipment.
FPGA and SoC Features Summary
Table 2: Arria 10 FPGA and SoC Common Device Features
DescriptionFeature
•20-nm TSMC SoC process technology
•0.9 V standard VCC core voltage
Technology
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DescriptionFeature
•Continuous operating range of 611 Mbps to 17.4 Gbps for Arria 10 GX devices
•Continuous operating range of 611 Mbps to 28.05 Gbps for Arria 10 GT devices
•Backplane support up to 16.0 Gbps for Arria 10 GX devices
•Backplane support up to 17.4 Gbps for Arria 10 GT devices
•Extended range down to 125 Mbps with oversampling
•ATX transmit PLLs with user-configurable fractional synthesis capability
•Electronic Dispersion Compensation (EDC) for XFP, SFP+, QSFP, and CFP
optical module support
•Adaptive linear and decision feedback equalization
•Transmit pre-emphasis and de-emphasis
•Dynamic partial reconfiguration of individual transceiver channels
•On-chip instrumentation (EyeQ non-intrusive data eye monitoring)
Low power serial
transceivers
•1.6 Gbps LVDS—every pair can be configured as an input or output
•1333 MHz/2666 Mbps DDR4 external memory interface
•1067 MHz/2133 Mbps DDR3 external memory interface
•1.2 V to 3.0 V single-ended LVCMOS/LVTTL interfacing
•On-chip termination (OCT)
General purpose I/Os
•PCIe Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8 end point and
root port
•DDR4/DDR3/DDR3L/DDR3U/RLDRAM 3/LPDDR3 hard memory controller
(RLDRAM2/QDR II+ using soft memory controller)
•Multiple hard IP instantiations in each device
•Dual-core ARM Cortex-A9 processor (Arria 10 SX devices only)
Embedded hard IP
•10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC)
•10G Ethernet PCS
•PCI Express PIPE interface
•Interlaken PCS
•Gigabit Ethernet PCS
•Deterministic latency support for Common Public Radio Interface (CPRI) PCS
•Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS
•8B/10B, 64B/66B, 64B/67B encoders and decoders
•Custom mode support for proprietary protocols
Transceiver hard IP
•SmartVoltage ID
•VCC PowerManager
•Low static power device options
•Programmable Power Technology
•Quartus®II integrated PowerPlay power analysis
Power management
•Enhanced adaptive logic module (ALM) with 4 registers
•Improved multi-track routing architecture reduces congestion and improves
compile times
•Hierarchical core clocking architecture
•Fine-grained partial reconfiguration
High performance core
fabric
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DescriptionFeature
•M20K—20-Kbit with hard ECC support
•MLAB—640-bit distributed LUTRAM
Internal memory blocks
•Natively supports signal processing with precision ranging from 18x19 up to
54x54
•Native 27x27 multiply mode
•64-bit accumulator and cascade for systolic FIRs
•Internal coefficient memory banks
•Pre-adder/subtractor improves efficiency
•Additional pipeline register increases performance and reduces power
Variable precision DSP
blocks
•Fractional synthesis PLLs (fPLL) support both fractional and integer modes
•Fractional mode with third-order delta-sigma modulation
•Precision frequency synthesis, clock delay compensation, zero delay buffering
•Integer PLLs adjacent to general purpose I/Os, support external memory, and
LVDS interfaces
Phase locked loops
(PLL)
•800 MHz fabric clocking
•667 MHz external memory interface clocking, supports 2666 Mbps DDR4
interface
•800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface
•Global, regional, and peripheral clock networks
•Unused clock trees powered down to reduce dynamic power
Core clock networks
•Serial and parallel flash interface
•Configuration via protocol (CvP) using PCI Express Gen1/Gen2/Gen3
•Fine-grained partial reconfiguration of core fabric
•Dynamic reconfiguration of transceivers and PLLs
•256-bit AES bitstream encryption design security with authentication
•Tamper protection
Configuration
•Multiple devices with identical package footprints allows seamless migration
across different FPGA densities
•Devices with compatible package footprints allows migration to next generation
high-end Stratix®10 devices
•1.0 mm ball-pitch FBGA packaging
•Lead and lead-free package options
Packaging
•Quartus II design suite
•Transceiver toolkit
•Qsys system integration tool
•DSP Builder advanced blockset
•OpenCL™support
•SoC Embedded Design Suite (EDS)
Software and tools
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Table 3: Arria 10 SoC-Specific Device Features
DescriptionFeature
•2.5 MIPS/MHz instruction efficiency
•CPU frequency 1.2 GHz with 1.5 GHz via overdrive
•At 1.5 GHz total performance of 7500 MIPS
•ARMv7-A architecture
•Runs 32-bit ARM instructions
•16-bit and 32-bit Thumb instructions for 30% reduction in memory footprint
•Jazelle®RCT execution architecture with 8-bit Java bytecodes
•Superscalar, variable length, out-of-order pipeline with dynamic branch
prediction
•ARM NEON™media processing engine
•Single- and double-precision floating-point unit
•CoreSight™debug and trace technology
•Snoop Control Unit (SCU) and Acceleration Coherency Port (ACP)
Dual-core ARM Cortex-
A9 MPCore processor
unit
•L1 Cache
•32 KB of instruction cache
•32 KB of L1 data cache
•Parity checking
•L2 Cache
•512 KB shared
•8-way set associative
•SEU Protection with parity on TAG ram and ECC on data RAM
•Cache lockdown support
Cache
•256 KB of scratch on-chip RAM
•64 KB on-chip ROM
On-Chip Memory
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DescriptionFeature
•Hard memory controller with support for DDR4, DDR3, DDR2, LPDDR2
•40-bit (32-bit + 8-bit ECC) with select packages supporting 72-bit (64-bit +
8-bit ECC)
•Support for up to 2666 Mbps DDR4 and 2166 Mbps DDR3 frequencies
•Error correction code (ECC) support including calculation, error correction,
write-back correction, and error counters
•Software Configurable Priority Scheduling on individual SDRAM bursts
ECC
•Fully programmable timing parameter support for all JEDEC specified timing
parameters
•AXI®Quality of Service (QoS) support for interface to logic core
•Multiport front-end (MPFE) scheduler interface to hard memory controller
•Queued serial peripheral interface (QSPI) flash controller allows port sharing
of hard memory controller between CPU and logic core
•Single I/O (SIO), Dual I/O (DIO), and Quad I/O (QIO) SPI Flash support
•Support for up to 108 MHz for flash frequency
•NAND flash controller
•ONFI 1.0 or later
•Integrated descriptor based with DMA
•New command DMA to offload CPU for fast power down recovery
•Programmable hardware ECC support
•Updated to support 8 and 16 bit Flash devices
•Support for 50 MHz flash frequency
•Secure Digital SD/SDIO/MMC controller
•eMMC 4.5
•Integrated descriptor based DMA
•CE-ATA digital commands supported
•50 MHz operating frequency
•Direct memory access (DMA) controller
•8-channel
•Supports up to 32 peripheral handshake interface
External Memory
Interface for HPS
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DescriptionFeature
•Three 10/100/1000 Ethernet media access controls (MAC) with integrated DMA
•Supports RGMII and RMII external PHY Interfaces
•Option to support other PHY interfaces through FPGA logic
•GMII and SGMII
•Supports IEEE 1588-2002 and IEEE 1588-2008 standards for precision
networked clock synchronization
•Supports IEEE 802.1Q VLAN tag detection for reception frames
•Supports Ethernet AVB standard
•2 USB On-the-Go (OTG) controllers with DMA
•Dual-Role Device (device and host functions)
•High-speed (480 Mbps)
•Full-speed (12 Mbps)
•Low-speed (1.5 Mbps)
•Supports USB 1.1 (full-speed and low-speed)
•Integrated descriptor-based scatter-gather DMA
•Support for external ULPI PHY
•Up to 16 bidirectional endpoints, including control endpoint
•Up to 16 host channels
•Supports generic root hub
•Configurable to OTG 1.3 and OTG 2.0 modes
•5 I2C controllers (3 can be used by EMAC for MIO to external PHY)
•Support both 100Kbps and 400Kbps modes
•Support both 7-bit and 10-bit addressing modes
•Support Master and Slave operating mode
•2 UART 16550 compatible
•Support IrDA 1.0 SIR mode
•Programmable baud rate up to 115.2Kbaud
•4 serial peripheral interfaces (SPI) (2 Master, 2 Slaves)
•Full and Half duplex
Communication
Interface Controllers
•Timers
•7 general-purpose timers
•4 watchdog timers
•62 programmable general-purpose I/O (GPIO)
•3 modules 24, 24, and 14
•48 I/O direct share I/O allows HPS peripherals to connect directly to I/O
Timers and I/O
•Anti-tamper, secure boot, Advanced Encryption Standard (AES) and
authentication (SHA)
Security
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DescriptionFeature
•High-performance ARM AMBA®AXI bus bridges
•AMBA AXI-3 compliant
•Allows both independent and tightly coupled operation between HPS and
logic core
•Support simultaneous read and write transactions
•FPGA-to-HPS Bridge
•Allows IP bus masters in the logic core to access to HPS bus slaves
•Configurable 32-, 64-, or 128-bit AMBA AXI interface
•Up to three masters within the core fabric can share the HPS SDRAM
controller with the processor
•HPS-to-FPGA Bridge
•Allows HPS bus masters to access bus slaves in core fabric
•Configurable 32-, 6-4, or 128-bit Avalon®/AMBA AXI interface allows high-
bandwidth HPS master transactions to logic core
•Configuration Bridge
•Allows configuration manager in HPS to configure the logic core under
program control via dedicated 32-bit configuration port
•Light Weight HPS-to-FPGA Bridge
•Light weight 32-bit AXI interface suitable for low-latency register accesses
from HPS to soft peripherals in logic core
•FPGA-to-HPS SDRAM controller Bridge
•Up to three masters (command ports), 3x 64-bit read data ports, and 3x 64-
bit write data ports
Interconnect to Logic
Core
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Arria 10 Block Diagrams
Figure 2: Arria 10 FPGA Architecture Block Diagram
Core Logic Fabric
M20K Internal Memory Blocks
Transceiver Channels
Hard IP Per Transceiver: 8B/10B PCS, 64B/66B PCS, 10GBase-KRFEC, Interlaken PCS
PCI Express Gen3 Hard IP
Fractional PLLs
M20K Internal Memory Blocks
PCI Express Gen3 Hard IP
Variable Precision DSP Blocks
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
M20K Internal Memory BlocksM20K Internal Memory Blocks
Variable Precision DSP Blocks
Core Logic Fabric
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
M20K Internal Memory BlocksM20K Internal Memory Blocks
Variable Precision DSP Blocks
Transceiver Channels
Hard IP Per Transceiver: 8B/10B PCS, 64B/66B PCS, 10GBase-KRFEC, Interlaken PCS
PCI Express Gen3 Hard IP
Fractional PLLs
PCI Express Gen3 Hard IP
Hard PCS
Hard PCS
Hard PCS
Hard PCS
Hard PCS
Hard PCS
Hard PCS
Hard PCS
Hard PCS Transceiver PMA
Transceiver PMA
Transceiver PMA
Transceiver PMA
Transceiver PMA
Transceiver PMA
Transceiver PMA
Note:
(1) Unused transceiver channels can be used as additional transceiver transmit PLLs
Transceiver PMA
Transceiver PMA
(1)
Transceiver Clock Networks
fPLL
ATX (LC)
Transmit
PLL
fPLL
ATX (LC)
Transmit
PLL
fPLL
ATX (LC)
Transmit
PLL
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Figure 3: Arria 10 SoC Architecture Block Diagram
Core Logic Fabric
M20K Internal Memory Blocks
Transceiver Channels
Hard IP Per Transceiver: 8B/10B PCS, 64B/66B PCS, 10GBase-KRFEC, Interlaken PCS
PCI Express Gen3 Hard IP
Fractional PLLs
M20K Internal Memory Blocks
PCI Express Gen3 Hard IP
Variable Precision DSP Blocks
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
Hard Processor
Subsystem, Dual-Core
ARM Cortex A9
M20K Internal Memory BlocksM20K Internal Memory Blocks
Variable Precision DSP Blocks
Core Logic Fabric
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
M20K Internal Memory BlocksM20K Internal Memory Blocks
Variable Precision DSP Blocks
Transceiver Channels
Hard IP Per Transceiver: 8B/10B PCS, 64B/66B PCS, 10GBase-KRFEC, Interlaken PCS
PCI Express Gen3 Hard IP
Fractional PLLs
PCI Express Gen3 Hard IP
Arria 10 FPGA Family Plan
Table 4: Arria 10 GX and Arria 10 GT FPGA Family Plan
PCIe HIPsI/O
PLLs
fPLLsMaxi-
mum
XCVR
(17.4G,
28.05G)
Maxi-
mum
GPIOs
18x19
Multi-
pliers
(2)
MLAB
Mbits
MLAB
Counts
M20K
Mbits
M20K
Blocks
RegistersLogic
Ele-
ments
(KLE)
Device
Name (1)
16612, 028831211,6809440246,040160GX 160
(10AX016)
16612, 028838412,22711583326,040220GX 220
(10AX022)
28824, 03841,66023,96815750406,480270GX 270
(10AX027)
(1) The text in parentheses is the part number reference for this device.
(2) The number of 27x27 multipliers is one-half the number of 18x19 multipliers.
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PCIe HIPsI/O
PLLs
fPLLsMaxi-
mum
XCVR
(17.4G,
28.05G)
Maxi-
mum
GPIOs
18x19
Multi-
pliers
(2)
MLAB
Mbits
MLAB
Counts
M20K
Mbits
M20K
Blocks
RegistersLogic
Ele-
ments
(KLE)
Device
Name (1)
28824, 03841,97034,67317891478,640320GX 320
(10AX032)
2121236, 04922,73647,137281,438730,880480GX 480
(10AX048)
2161648, 05883,04658,241351,800868,320570GX 570
(10AX057)
2161648, 05883,35669,345422,1331,005,800660GX 660
(10AX066)
4163296, 07683,036915,080472,4231,358,480900GX 900
(10AX090)
4163296, 07683,0361320,814532,7131,710,8001,150GX 1150
(10AX115)
4163280, 166243,036915,080472,4231,358,480900GT 900
(10AT090)
4163280, 166243,0361320,814532,7131,710,8001,150GT 1150
(10AT115)
Table 5: Arria 10 GX and Arria 10 GT FPGA Family Package Plan, part 1
Cell legend: General Purpose I/Os, High-Voltage I/Os, LVDS Pairs, Transceivers (3) (4) (5) (6) (7) (8)
F36 (F1152)
(35x35 mm2)(9)
F35 (F1152)
(35x35 mm2)(9)
F34 (F1152)
(35x35 mm2)
F29 (F780)
(29x29 mm2)
F27 (F672)
(27x27 mm2)
U19 (U484)
(19x19 mm2)
Device (1)
———288,48,120,12240,48,96,12192,48,72,6GX 160
(10AX016)
(3) All packages are ball grid arrays with 1.0 mm pitch, except for U19 (U484), which is 0.8 mm pitch.
(4) High-Voltage I/O pins are used for 3.3 V and 2.5 V interfacing.
(5) Each LVDS pair can be configured as either a differential input or a differential output.
(6) High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count. Transceivers are counted
separately.
(7) Each package column offers pin migration (common circuit board footprint) for all devices in the column.
(8) Arria 10 GX devices are pin migratable with Arria 10 GT devices in the same package.
(9) Devices in the F35 (F1152) package are pin migratable with devices in the F36 (F1152) package
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F36 (F1152)
(35x35 mm2)(9)
F35 (F1152)
(35x35 mm2)(9)
F34 (F1152)
(35x35 mm2)
F29 (F780)
(29x29 mm2)
F27 (F672)
(27x27 mm2)
U19 (U484)
(19x19 mm2)
Device (1)
———288,48,120,12240,48,96,12192,48,72,6GX 220
(10AX022)
—384,48,168,24384,48,168,24360,48,156,12240,48,96,12—GX 270
(10AX027)
—384,48,168,24384,48,168,24360,48,156,12240,48,96,12—GX 320
(10AX032)
—396,48,174,36492,48,222,24360,48,156,12——GX 480
(10AX048)
—396,48,174,36492,48,222,24———GX 570
(10AX057)
432,48,192,36396,48,174,36492,48,222,24———GX 660
(10AX066)
—432,0,216,36528,0,264,24———GX 900
(10AX090)
—432,0,216,36528,0,264,24———GX 1150
(10AX115)
——————GT 900
(10AT090)
——————GT 1150
(10AT115)
Table 6: Arria 10 GX and Arria 10 GT FPGA Family Package Plan, part 2
Cell legend: General Purpose I/Os, High-Voltage I/Os, LVDS Pairs, Transceivers (3) (4) (5) (6) (7) (8)
F45 (F1932)
(45x45 mm2)
F45 (F1932)
(45x45 mm2)
F45 (F1932)
(45x45 mm2)
F40 (F1517)
(40x40 mm2)
F40 (F1517)
(40x40 mm2)
Device (1)
—————GX 160
(10AX016)
—————GX 220
(10AX022)
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F45 (F1932)
(45x45 mm2)
F45 (F1932)
(45x45 mm2)
F45 (F1932)
(45x45 mm2)
F40 (F1517)
(40x40 mm2)
F40 (F1517)
(40x40 mm2)
Device (1)
—————GX 270
(10AX027)
—————GX 320
(10AX032)
—————GX 480
(10AX048)
————588,48,270,48GX 570
(10AX057)
————588,48,270,48GX 660
(10AX066)
480,0,240,96624,0,312,72768,0,384,48342,0,154,66624,0,312,48GX 900
(10AX090)
480,0,240,96624,0,312,72768,0,384,48342,0,154,66624,0,312,48GX 1150
(10AX115)
480,0,240,96624,0,312,72——624,0,312,48GT 900
(10AT090)
480,0,240,96624,0,312,72——624,0,312,48GT 1150
(10AT115)
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Arria 10 SoC Family Plan
Table 7: Arria 10 SX SoC Family Features
Available in all Arria 10 SoC DevicesFeatureSoC Subsystem
Dual-core ARM Cortex-A9 MPCore processor
with ARM CoreSight debug and trace technology
Central processing unit (CPU)
core
Hard Processor
System
Vector Floating-point unit (VFPU) single and
double precision, ARM NEON media processing
engine for each processor Snoop control unit
(SCU), Acceleration coherency port (ACP)
Co-processors
32 KB L1 instruction cache, 32 KB L1 data cacheLayer 1 Cache
512 KB Shared L2 CacheLayer 2 Cache
256 KB On-Chip RAM, 64 KB On-chip ROMOn-Chip Memory
8-Channel DMADirect memory access (DMA)
controller
Three 10/100/1000 EMAC with integrated DMAEthernet media access controller
(EMAC)
2 USB OTG with integrated DMAUSB On-The-Go controller (OTG)
2 UART 16550 compatibleUART controller
4 SPISerial Peripheral Interface (SPI)
controller
5 I2C controllersI2C controller
1 SIO, DIO, QIO SPI flash supportedQSPI flash controller
1 eMMC 4.5 with DMA and CE-ATA supportSD/SDIO/MMC controller
1 ONFI 1.0 or later 8 and 16 bit supportNAND flash controller
Maximum of 62 software programmable GPIOGeneral-purpose I/O (GPIO)
7 general-purpose timers, 4 watchdog timersTimers
Secure boot, Advanced Encryption Standard
(AES) and authentication (SHA)
Security
Hard Memory Controller with DDR4 and DDR3External Memory InterfaceExternal Memory
Interface
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Table 8: Arria 10 SX SoC Family Plan
PCIe HIPsI/O
PLLs
fPLLsMaxi-
mum
XCVR
(17.4G,
28.05G)
Maxi-
mum
GPIOs
18x19
Multi-
pliers
(11)
MLAB
Mbits
MLAB
Counts
M20K
Mbits
M20K
Blocks
RegistersLogic
Ele-
ments
(KLE)
Device
Name (10)
16612, 028831211,6809440246,040160SX 160
(10AS016)
16612, 028838412,22711583326,040220SX 220
(10AS022)
28824, 03841,66023,96815750406,480270SX 270
(10AS027)
28824, 03841,97034,67317891478,640320SX 320
(10AS032)
2121236, 04922,73647,137281,438730,880480SX 480
(10AS048)
2161648, 05883,04658,241351,800868,320570SX 570
(10AS057)
2161648, 05883,35669,345422,1331,005,800660SX 660
(10AS066)
(10) The text in parentheses is the part number reference for this device.
(11) The number of 27x27 multipliers is one-half the number of 18x19 multipliers.
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Table 9: Arria 10 SX SoC Family Package Plan
Cell legend: General Purpose I/Os, High-Voltage I/Os, LVDS Pairs, Transceivers (12) (13) (14) (15) (16)
F40 (F1517)
(40x40 mm2)
F36 (F1152)
(35x35 mm2)
(17)
72-bit HPS
DDR
F35 (F1152)
(35x35 mm2)
(17)
F34 (F1152)
(35x35 mm2)
F29 (F780)
(29x29 mm2)
F27 (F672)
(27x27 mm2)
U19 (U484)
(19x19 mm2)
Device (10)
————288,48,120,12240,48,96,12192,48,72,6SX 160
(10AS016)
————288,48,120,12240,48,96,12192,48,72,6SX 220
(10AS022)
——384,48,168,24384,48,168,24360,48,156,12240,48,96,12—SX 270
(10AS027)
——384,48,168,24384,48,168,24360,48,156,12240,48,96,12—SX 320
(10AS032)
——396,48,174,36492,48,222,24360,48,156,12——SX 480
(10AS048)
588,48,270,48—396,48,174,36492,48,222,24———SX 570
(10AS057)
588,48,270,48432,48,192,36396,48,174,36492,48,222,24———SX 660
(10AS066)
Migration Between Arria 10 Devices and Stratix 10 Devices
You can start developing with Arria 10 devices and then move to Stratix 10 devices, because there is footprint
compatibility between the Arria 10 and Stratix 10 packages. Contact Altera for more details about the
migration possibilities between the two device families.
(12) All packages are ball grid arrays with 1.0 mm pitch, except for U19 (U484), which is 0.8 mm pitch.
(13) High-Voltage I/O pins are used for 3.3 V and 2.5 V interfacing.
(14) Each LVDS pair can be configured as either a differential input or a differential output.
(15) High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count. Transceivers are counted
separately.
(16) Each package column offers pin migration (common circuit board footprint) for all devices in the column.
(17) Devices in the F35 (F1152) package are pin migratable with devices in the F36 (F1152) package
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Arria 10 Low Power Serial Transceivers
Arria 10 FPGAs and SoCs provide the lowest power transceivers for applications where power efficiency is
paramount, while still delivering high bandwidth, throughput, and low latency.
Arria 10 transceivers feature data rates from 125 Mbps to 28.05 Gbps for chip-to-chip and chip-to-module
applications. In addition, for long reach and backplane applications, advanced adaptive equalization is
available for driving backplanes at data rates up to 17.4 Gbps. Lower power modes are also available at data
rates up to 11.3 Gbps for critical power sensitive designs.
The combination of 20 nm process technology and architectural advances provide a significant reduction
of die area and power consumption. Arria 10 transceivers allow for up to a 2X increase in transceiver I/O
density compared to previous generation devices while maintaining optimal signal integrity. Arria 10 devices
offer up to 96 total transceiver channels. Up to 16 of these channels can be configured to run up to 28.05
Gbps to drive next generation 100G interfaces and CFP2/CFP4 optical modules. All channels feature
continuous data rate support up to the maximum rated speed.
Figure 4: Arria 10 Transceiver Block Architecture
ATX
PLL
fPLL
fPLL
ATX
PLL
FPGA
Core
Fabric
PCS
PCS
PCS
PCS
PCS
PCS
Transceiver PMA TX/RX
Transceiver PMA TX/RX
Transceiver PMA TX/RX
Transceiver PMA TX/RX
Transceiver PMA TX/RX
Transceiver PMA TX/RX
Flexible Clock Distribution Network
All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical
Coding Sublayer (PCS).
•The PMA provides primary interfacing capabilities to physical channels.
•The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions
before transferring data to the FPGA core fabric.
Transceivers are segmented into blocks of six PMA-PCS groups. A wide variety of bonded and non-bonded
data rate configurations are possible using a highly configurable clock distribution network. Up to 80
independent transceiver data rates can be configured.
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PMA Features
PMA channels are comprised of transmitter (TX), receiver (RX), and high speed clocking resources.
Arria 10 TX features provide exceptional signal integrity at data rates up to 28.05 Gbps. Clocking options
include ultra-low jitter ATX (inductor-capacitor) PLLs, channel PLLs, clock multiplier unit (CMU) PLLs,
and fractional PLLs (fPLLs):
•ATX PLLs can be configured in integer mode, or optionally, in a new fractional frequency synthesis
mode. Each ATX PLL spans the full frequency range of the supported data rate range providing a highly
stable and flexible clock source with the lowest jitter.
•CMU PLLs have been enhanced to provide a master clock source within the transceiver bank.
•When not configured as a transceiver channel, select PMA channels can be optionally configured as ring
oscillator-based channel PLLs to provide an additional flexible clock source.
•In addition, dedicated on-chip fractional PLLs (fPLLs) are available with precision frequency synthesis
capabilities. fPLLs can be used to synthesize multiple clock frequencies from a single reference clock
source and replace multiple reference oscillators for multi-protocol and multi-rate applications.
Figure 5: Arria 10 Transmitter Features
TX
Pre-Emphasis
TX Driver
Clock Buffers
Clock
Distribution
ATX (LC) PLL
Channel PLL
CMU/fPLL
Clock Sources Serializer
On the receiver side, each PMA channel has a dedicated, independent channel PLL for the CDR to provide
the maximum number of clocking resources possible without compromising TX clocking sources. Up to 80
independent data rates can be configured on a single Arria 10 device.
Receiver side features provide unparalleled equalization capabilities to drive a wide range of transmission
media with the widest range of protocols and data rates. Each receiver channel includes:
•Continuous Time Linear Equalizers (CTLE)—to compensate for channel losses with low power
•Variable Gain Amplifiers (VGA)—to optimize the receiver's dynamic range
•Decision Feedback Equalizers (DFE)—with 7-fixed taps and 4-floating taps to provide additional
equalization capability on backplanes even in the presence of crosstalk and reflections
In addition, On-Die Instrumentation (ODI) provides on-chip eye monitoring capabilities (EyeQ). This
capability helps to both optimize link equalization parameters during board bring-up and provide in-system
link diagnostics. Combined with on-chip jitter injection capabilities, EyeQ provides powerful functionality
to do in-system link equalization margin testing.
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Figure 6: Arria 10 Receiver Block Features
∑
VGA CDR
DFE EyeQ
CTLE
Adaptive Parametric Tuning Engine
Deserializer
All link equalization parameters feature automatic adaptation using the new Altera Digital Adaptive Parametric
Tuning (ADAPT) block to dynamically set DFE tap weights, CTLE, VGA Gain, and threshold voltages.
Finally, optimal and consistent signal integrity is ensured by using the new hardened Precision Signal Integrity
Calibration Engine (PreSICE) to automatically calibrate all transceiver circuit blocks on power-up to give
the most link margin and ensure robust, reliable, and error-free operation.
Table 10: Arria 10 Transceiver PMA Features
CapabilityFeature
125 Mbps to 17.4 Gbps (Arria 10 GX devices)
125 Mbps to 28.05 Gbps (Arria 10 GT devices)
Chip-to-Chip Data
Rates
Drive backplanes at data rates up to 17.4 Gbps, including 10GBASE-KR complianceBackplane Support
SFP+/SFP, XFP, CXP, QSFP/QSFP28, CFP/CFP2/CFP4Optical Module Support
SFP+ Direct Attach, PCI Express over cable, eSATACable Driving Support
5-tap transmit pre-emphasis and de-emphasis to compensate for system channel
loss
Transmit Pre-Emphasis
Dual mode, high-gain, and high-data rate, linear receive equalization to compensate
for system channel loss
Continuous Time Linear
Equalizer (CTLE)
7-fixed and 4-floating tap DFE to equalize backplane channel loss in the presence
of crosstalk and noisy environments
Decision Feedback
Equalizer (DFE)
Fully digital adaptation engine to automatically adjust all link equalization
parameters—including CTLE, DFE, and VGA blocks—that provide optimal link
margin without intervention from user logic
Altera Digital Adaptive
Parametric Tuning
(ADAPT)
Hardened calibration controller to quickly calibrate all transceiver control
parameters on power-up, which provides the optimal signal integrity and jitter
performance
Precision Signal
Integrity Calibration
Engine (PreSICE)
Low jitter ATX (inductor-capacitor) transmit PLLs with continuous tuning range
to cover a wide range of standard and proprietary protocols
ATX Transmit PLLs
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CapabilityFeature
On-chip fractional frequency synthesizers to replace on-board crystal oscillators
and reduce system cost
Fractional PLLs
Superior jitter tolerance with fast lock timeDigitally Assisted
Analog CDR
Simplify board bring-up, debug, and diagnostics with non-intrusive, high-resolution
eye monitoring (EyeQ). Also inject jitter from transmitter to test link margin in
system.
On-Die Instrumenta-
tion—EyeQ and Jitter
Margin Tool
Allows for independent control of each transceiver channel Avalon memory-
mapped interface for the most transceiver flexibility
Dynamic Partial
Reconfiguration
(DPRIO)
8-, 10-, 16-, 20-, 32-, 40-, or 64-bit interface widths for flexibility of deserialization
width, encoding, and reduced latency
Multiple PCS-PMA and
PCS-PLD interface
widths
PCS Features
Arria 10 PMA channels interface with core logic through configurable PCS interface layers.
Multiple gearbox implementations are available to decouple PCS and PMA interface widths. This feature
provides the flexibility to implement a wide range of applications with 8-, 10-, 16-, 20-, 32-, 40-, or 64-bit
interface widths. Arria 10 FPGAs contain PCS hard IP to support a wide range of standard and proprietary
protocols.
The Standard PCS mode provides support for 8B/10B encoded applications up to 12.5 Gbps. The Enhanced
PCS mode supports applications up to 17.4 Gbps. In addition, for highly customized implementations, a
PCS Direct mode provides a fixed width interface up to 64 bits wide to core logic to allow for custom encoding
including support for standards up to 28.05 Gbps.
The enhanced PCS includes an integrated 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC)
block.
The following table lists some of the key PCS features of Arria 10 transceivers that can be used in a wide
range of standard and proprietary protocols from 125 Mbps to 28.05 Gbps.
Table 11: Arria 10 Transceiver PCS Features
Receiver Data PathTransmitter Data PathData Rate (Gbps)PCS Protocol
Support
Rate match FIFO, word-aligner,
8B/10B decoder, byte deserializer,
byte ordering
Phase compensation FIFO, byte
serializer, 8B/10B encoder, bit-slipper,
channel bonding
0.125 to 12.5Standard PCS
Same as Standard PCS plus PIPE
2.0 interface to core
Same as Standard PCS plus PIPE 2.0
interface to core
2.5 and 5.0PCI Express
Gen1/Gen2
x1, x4, x8
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Receiver Data PathTransmitter Data PathData Rate (Gbps)PCS Protocol
Support
Rate match FIFO (0-600 ppm
mode), word-aligner, decoder,
descrambler, phase compensation
FIFO, block sync, byte deserializer,
byte ordering, PIPE 3.0 interface
to core, auto speed negotiation
Phase compensation FIFO, byte
serializer, encoder, scrambler, bit-
slipper, gear box, channel bonding,
and PIPE 3.0 interface to core, auto
speed negotiation
8.0PCI Express
Gen3 x1, x4,
x8
Same as Standard PCS plus
deterministic latency deserializa-
tion
Same as Standard PCS plus
deterministic latency serialization
0.6144 to 9.8CPRI
FIFO, block sync, bit-slipper, and
gear box
FIFO, channel bonding, bit-slipper,
and gear box
2.5 to 17.4Enhanced PCS
FIFO, 64B/66B decoder, descram-
bler, block sync, FEC, and gear
box
FIFO, 64B/66B encoder, scrambler,
FEC, and gear box
10.312510GBASE-R
FIFO, CRC-32 checker, frame
sync, descrambler, disparity
checker, block sync, and gear box
FIFO, channel bonding, frame
generator, CRC-32 generator,
scrambler, disparity generator, bit-
slipper, and gear box
4.9 to 17.4Interlaken
FIFO, bit-slipper, and gear boxFIFO, channel bonding, bit-slipper,
and gear box
11.3SFI-S/SFI-5.2
FIFO (fixed latency), 64B/66B
decoder, descrambler, block sync,
and gear box
FIFO (fixed latency), 64B/66B
encoder, scrambler, and gear box
1.25 to 10.3125IEEE 1588
FIFO, bit-slipper, and gear boxFIFO and gear boxup to 11.9SDI
Same as Standard PCS plus GigE
state machine
Same as Standard PCS plus GigE state
machine
1.25GigE
CustomCustomup to 28.05PCS Direct
PCI Express Gen1/Gen2/Gen3 Hard IP
Arria 10 devices contain embedded PCI Express hard IP designed for performance, ease-of-use, and increased
functionality.
The PCI Express hard IP consists of the PHY, Data Link, and Transaction layers, and supports PCI Express
Gen1/Gen2/Gen3 end point and root port, in x1/x2/x4/x8 lane configurations. The PCI Express hard IP is
capable of operating independently from the core logic. This feature allows the link to power up and complete
link training in less than 100 ms, while the Arria 10 device completes loading the programming file for the
rest of the FPGA. The hard IP also provides added functionality, which makes it easier to support emerging
features such as Single Root I/O Virtualization (SR-IOV) and optional protocol extensions. The Arria 10
PCI Express hard IP has improved end-to-end data path protection using Error Checking and Correction
(ECC). In addition, the hard IP supports configuration of the FPGA via protocol across the PCI Express bus
at Gen1/Gen2/Gen3 rates (CvP using PCI Express).
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Interlaken PCS Hard IP
Arria 10 devices have integrated Interlaken PCS hard IP supporting rates up to 17.4 Gbps per lane.
The Interlaken PCS hard IP is based on the proven functionality of the PCS developed for Altera’s previous
generation FPGAs, which has demonstrated interoperability with Interlaken ASSP vendors and third-party
IP suppliers. The Interlaken PCS hard IP is present in every transceiver channel in Arria 10 devices.
10G Ethernet Hard IP
Arria 10 devices include IEEE 802.3 10-Gbps Ethernet (10GbE) compliant 10GBASE-R PCS and PMA hard
IP. The scalable 10GbE hard IP supports multiple independent 10GbE ports while using a single PLL for all
the 10GBASE-R PCS instantiations, which saves on core logic resources and clock networks.
The integrated 10G serial transceivers simplify multi-port 10GbE systems compared to XAUI interfaces that
require an external XAUI-to-10G PHY. Furthermore, the integrated 10G transceivers incorporate Electronic
Dispersion Compensation (EDC), which enables direct connection to standard 10G XFP and SFP+ pluggable
optical modules. The 10G transceivers also support backplane Ethernet applications and include a hard
10GBASE-KR Forward Error Correction (FEC) circuit that can be used for both 10G and 40G applications.
The integrated 10G Ethernet hard IP and 10G transceivers save external PHY cost, board space, and system
power. The 10G Ethernet PCS hard IP and 10GBASE-KR FEC are present in every transceiver channel.
External Memory and General Purpose I/O
Arria 10 devices offer massive external memory bandwidth, with up to seven 32-bit DDR4 memory interfaces
running at up to 2666 Mbps.
This bandwidth provides additional ease of design, lower power, and resource efficiencies of hardened high-
performance memory controllers. Memory interfaces can be configured up to a maximum width of 144 bits
when using either hard or soft memory controllers. Arria 10 devices also feature general purpose I/O capable
of supporting a wide range of single-ended and differential I/O interfaces. LVDS rates up to 1.6 Gbps are
supported, with each pair of pins having both a differential driver and a differential input buffer allowing
for configurable LVDS direction on each pair.
The memory interface within Arria 10 FPGAs and SoCs delivers the highest performance and ease of use.
Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller capable of
supporting many different memory types, each with different performance capabilities. The hard memory
controller is also capable of being bypassed and replaced by a soft controller implemented in the user logic.
The I/Os each have a hardened DDR read/write path (PHY) capable of performing key memory interface
functionality such as read/write leveling, FIFO buffering to lower latency and improve margin, timing
calibration, and on-chip termination. The timing calibration is aided by the inclusion of hard microcontrollers
based on Altera’s Nios®II technology, specifically tailored to control the calibration of multiple memory
interfaces. This calibration allows the Arria 10 device to compensate for any changes in process, voltage, or
temperature either within the Arria 10 device itself, or within the external memory device. The advanced
calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.
Table 12: Arria 10 External Memory Interface Performance
The listed speeds are for the 1-rank case.
PerformanceController TypeInterface
2666 MbpsHardDDR4
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PerformanceController TypeInterface
2133 MbpsHardDDR3
550 MTpsSoftQDR II+ / II+ Xtreme
2400 MbpsHardRLDRAM III
533 MbpsSoftRLDRAM II
In addition to parallel memory interfaces, Arria 10 devices support serial memory technologies such as the
Hybrid Memory Cube (HMC). The HMC is supported by the Arria 10 high-speed serial transceivers, which
connect up to four HMC links, with each link running at data rates up to 15 Gbps.
Adaptive Logic Module (ALM)
Arria 10 devices use the same adaptive logic module (ALM) as the previous generation Arria V and Stratix V
FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the
devices.
The ALM block diagram shown in the following figure has eight inputs with a fracturable look-up table
(LUT), two dedicated embedded adders, and four dedicated registers.
Figure 7: Arria 10 FPGA and SoC ALM Block Diagram
Reg
Reg
1
2
3
4
5
6
7
8
Reg
Reg
4 Registers for ALM
Full
Adder
Full
Adder
Adaptive
LUT
Key features and capabilities of the Arria 10 ALM include:
•High register count with 4 registers per 8-input fracturable LUT enables Arria 10 devices to maximize
core performance at higher core logic utilization
•6% more logic compared to the traditional 2-register per LUT architecture
•Implements select 7-input logic functions, all 6-input logic functions, and two independent functions
consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization
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The Quartus II software leverages the Arria 10 ALM logic structure to deliver the highest performance,
optimal logic utilization, and lowest compile times. The Quartus II software simplifies design reuse as it
automatically maps legacy designs into the Arria 10 ALM architecture.
Core Clocking
The Arria 10 device core clock network supports over 500 MHz fabric operation across the full industrial
temperature range, and supports the hard memory controllers up to 2666 Mbps with a quarter rate transfer.
The clock network architecture is based on Altera’s proven global, regional, and periphery clock structure,
which is supported by dedicated clock input pins, fractional clock synthesis PLLs, and integer I/O PLLs. All
unused sections of the clock network are identified by the Quartus II software and are powered down to
reduce dynamic power consumption.
Fractional Synthesis PLLs and I/O PLLs
Arria 10 devices have up to 32 fractional synthesis PLLs (fPLL) and up to 16 I/O PLLs (IOPLL) that are
available for both specific and general purpose use in the core.
The fPLLs are located in columns adjacent to the transceiver blocks. They can be used to reduce both the
number of oscillators required on the board and the number of clock pins required, by synthesizing multiple
clock frequencies from a single reference clock source. In addition to synthesizing reference clock frequencies
for the transceiver CMU and ATX (LC) transmit PLLs, the fPLLs can be used for clock network delay
compensation, zero-delay buffering, and direct transmit clocking for transceivers. Each fPLL may be
independently configured for conventional integer mode, which is equivalent to a general purpose PLL
(GPLL), or enhanced fractional mode with third-order delta-sigma modulation.
The integer mode IOPLLs are located in each bank of 48 I/Os. They can be used to simplify the design of
external memory interfaces and high-speed LVDS interfaces. The IOPLLs are adjacent to the hard memory
controllers and LVDS SERDES in each I/O bank, making it easier to close timing because these PLLs are
tightly coupled with the I/Os that need to use them. Like the fPLLs, the IOPLLs can be used for general
purpose applications in the core such as clock network delay compensation and zero-delay buffering.
Internal Embedded Memory
Arria 10 devices contain two types of embedded memory blocks: MLAB (640-bit) and M20K (20-Kbit).
The MLAB blocks are ideal for wide and shallow memories. The M20K blocks are double the size of the
M10K blocks used in the previous generation Arria V devices, and are useful for supporting larger memory
configurations and include hard ECC. Both types of embedded memory block can be configured as a single-
port or dual-port RAM, FIFO, ROM or shift register. These memory blocks are highly flexible and support
a number of memory configuration as shown in the following table.
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Table 13: Arria 10 Internal Embedded Memory Block Configurations
M20K (20 Kbits)MLAB (640 bits)
16K x 1
8K x 2
4K x 5
2K x 10
1K x 20
512 x 40
64 x 10 (supported through emulation)
32 x 20
The Quartus II software simplifies design reuse by automatically mapping memory blocks from previous
generations of devices into the Arria 10 MLAB and M20K blocks.
Variable Precision DSP Block
The Arria 10 DSP blocks are based upon the Variable Precision DSP Architecture used in Altera’s previous
generation Arria V FPGAs. The blocks can be configured to natively support signal processing with precision
ranging from 18x19 up to 54x54. A pipeline register has been added to increase the maximum operating
frequency of the DSP block and reduce power consumption.
Each DSP block can be independently configured at compile time as either dual 18x19 or a single 27x27
multiply accumulate. With a dedicated 64-bit cascade bus, multiple variable precision DSP blocks can be
cascaded to implement even higher precision DSP functions efficiently. The following table shows how
different precisions are accommodated within a DSP block, or by utilizing multiple blocks.
Table 14: Variable Precision DSP Block Configurations
Expected UsageDSP Block ResourcesMultiplier Size
Medium precision fixed point1/2 of Variable Precision DSP Block18x19 bits
High precision fixed or Single Precision
floating point
1 Variable Precision DSP Block27x27 bits
Fixed point FFTs1 Variable Precision DSP Block with external
adder
19x36 bits
Very high precision fixed point2 Variable Precision DSP Blocks with external
adder
36x36 bits
Double Precision floating point4 Variable Precision DSP Blocks with external
adder
54x54 bits
Complex multiplication is very common in DSP algorithms. One of the most popular applications of complex
multipliers is the FFT algorithm. This algorithm has the characteristic of increasing precision requirements
on only one side of the multiplier. The Variable Precision DSP block supports the FFT algorithm with
proportional increase in DSP resources as the precision grows.
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Table 15: Complex Multiplication With Variable Precision DSP Block
FFT UsageDSP Block ResourcesComplex Multiplier
Size
Resource optimized FFTs2 Variable Precision DSP Blocks18x19 bits
Highest precision FFT stages and single
precision floating point
4 Variable Precision DSP Blocks27x27 bits
For FFT applications with high dynamic range requirements, the Altera FFT MegaCore®function offers an
option of single precision floating point implementation, with resource usage and performance similar to
high precision fixed point implementations.
Other features of the DSP block include:
•Hard 18-bit and 25-bit pre-adders
•64-bit dual accumulator (for separate I, Q product accumulations)
•Cascaded output adder chains for 18- and 27-bit FIR filters
•Embedded coefficient registers for 18- and 27-bit coefficients
•Fully independent multiplier outputs
•Inferability using HDL templates supplied by the Quartus II software for most modes
The Variable Precision DSP block is ideal to support the growing trend towards higher bit precision in high
performance DSP applications. At the same time, it can efficiently support the many existing 18-bit DSP
applications, such as high definition video processing and remote radio heads. Arria 10 devices, with the
Variable Precision DSP block architecture, can efficiently support many different precision levels, up to and
including floating point implementations. This flexibility can result in increased system performance, reduced
power consumption, and reduce architecture constraints on system algorithm designers.
Hard Processor System (HPS)
The 20-nm HPS strikes a balance between enabling maximum software compatibility with 28-nm SoCs
while still improving upon the 28-nm HPS architecture. These improvements address the requirements of
the next generation target markets such as wireless and wireline communications, compute and storage
equipment, broadcast and military in terms of performance, memory bandwidth, connectivity via backplane
and security.
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Figure 8: HPS Block Diagram
Multiple Hard Memory Controllers
Widest Logic Densities Available
ECC on All Memories and L2 Cache
High-Speed Serial
Transceivers in All
Devices
PCIe Hard IP in
All Devices
Notes:
1. Integrated direct memory access (DMA)
2. Integrated ECC
3. Multi-Port front-end interface to hard
memory controller
Dual ARM Cortex-A9-Based
Hard Processor System
ARM Cortex-A9 QSPI Flash
Control
UART
(x2)
ARM Cortex-A9
512 KB L2 Cache
EMAC with
DMA (x3) (1)
JTAG Debug/
Trace
USB OTG
(x2) (1)
I2C
(x5)
Hard Processor System (HPS)
256 KB
RAM
Timers
(x11)
LW HPS to
Core Bridge
HPS to Core
Bridge
Core to HPS
Bridge MPFE (3)
32 KB L1 Cache 32 KB L1 Cache
NEON FPU NEON FPU
AXI 32 AXI 32/64/128 AXI 32/64/128 ACP
SD/SDIO/
MMC (1)
DMA
(8 Channels)
SPI
(x2)
NAND Flash
(1), (2)
The HPS has the following features:
•1.2-GHz, dual-core ARM Cortex-A9 MPCore processor with up to 1.5-GHz via overdrive
•ARMv7-A architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and
8-bit Java byte codes in Jazelle style
•Superscalar, variable length, out-of-order pipeline with dynamic branch prediction
•Instruction Efficiency 2.5 MIPS/MHz, at 1.5 GHz total performance of 7500 MIPS
•Each processor core includes:
•32 KB of L1 instruction cache, 32 KB of L1 data cache
•Single- and double-precision floating-point unit and NEON media engine
•CoreSight debug and trace technology
•Snoop Control Unit (SCU) and Acceleration Coherency Port (ACP)
•512 KB of shared L2 cache
•256 KB of scratch RAM
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•Hard memory controller with support for DDR3, DDR4 and optional error correction code (ECC) support
•Multiport Front End (MPFE) Scheduler interface to the hard memory controller
•8-channel direct memory access (DMA) controller
•QSPI flash controller with SIO, DIO, QIO SPI Flash support
•NAND flash controller (ONFI 1.0 or later) with DMA and ECC support, updated to support 8 and 16-
bit Flash devices and new command DMA to offload CPU for fast power down recovery
•Updated SD/SDIO/MMC controller to eMMC 4.5 with DMA with CE-ATA digital command support
•3 10/100/1000 Ethernet media access control (MAC) with DMA
•2 USB On-the-Go (OTG) controller with DMA
•5 I2C controller (3 can be used by EMAC for MIO to external PHY)
•2 UART 16550 Compatible
•4 serial peripheral interface (SPI) (2 Master, 2 Slaves)
•54 programmable general-purpose I/O (GPIO)
•48 I/O direct share I/O allows HPS peripherals to connect directly to I/O
•7 general-purpose timers
•4 watchdog timers
•Anti-tamper, Secure Boot, Encryption (AES) and Authentication (SHA)
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Key Features of 20-nm HPS
The following features are new in the 20-nm Hard Processor System compared to the 28-nm SoCs:
•Increased Performance and Overdrive Capability
While the nominal processor frequency is 1.2 GHz, the 20 nm HPS offers an “overdrive”feature which
enables an even higher processor operating frequency. For this a higher supply voltage value is required
that is unique to the HPS and may require a separate regulator.
•Increased Processor Memory Bandwidth and DDR4 Support
Up to 64-bit DDR4 memory @ 2666 Mbps is available for the processor. The hard memory controller
for the HPS comprises a multi-port front end that manages connections to a single port memory controller.
The multi-port front end allows logic core and the HPS share ports and thereby the available bandwidth
of the memory controller.
•Flexible I/O Sharing
An advanced I/O pin muxing scheme allows improved sharing of I/O between the HPS and the core
logic. The following types of I/O are available for SoC:
Dedicated I/O (15)—These I/Os are physically located inside the HPS block and are not accessible to
logic within the core. The 15 dedicated I/Os are used for HPS clock, resets, and interfacing with boot
devices, QSPI, and SD/MMC
Direct Shared I/O (48)—These shared I/Os are located closest to the HPS block and are ideal for high
speed HPS peripherals such as EMAC, USB, and others. There is one bank of 48 I/Os that supports direct
sharing where the 48 I/Os can be shared 12 I/Os at a time.
Standard (Shared) I/O (All other)—All standard I/Os can be shared by the HPS peripherals and any
logic within the core. For designs where more than 48 I/Os are required to fully use all the peripherals
in the HPS, these I/Os can be connected through the core logic.
•EMAC Core
A third EMAC core is available in the HPS. Three EMAC cores enable an application to support two
redundant Ethernet connections; for example, backplane, or two EMAC cores for managing IEEE 1588
time stamp information while allowing a third EMAC core for debug and configuration. All three EMACs
can potentially share the same time stamps, simplifying the 1588 time stamping implementation. A new
serial time stamp interface allows core logic to access and read the time stamp values. The integrated
EMAC controllers can be connected to external Ethernet PHY through the provided MDIO or I2C
interface.
•On-Chip Memory
The on-chip memory is updated to 256 KB support and can support larger data sets and real time
algorithms
•ECC Enhancements
Improvements in L2 Cache ECC management allow identification of errors down to the address level.
ECC enhancements also enable improved error injection and status reporting via the introduction of
new memory mapped access to syndrome and data signals.
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•HPS to FPGA Interconnect Backbone
Although the HPS and the Logic Core can operate independently, they are tightly coupled via a high-
bandwidth system interconnect built from high-performance ARM AMBA AXI bus bridges. IP bus
masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect. Similarly,
HPS bus masters have access to bus slaves in the core fabric via the HPS-to-FPGA bridge. Both bridges
are AMBA AXI-3 compliant and support simultaneous read and write transactions. Up to three masters
within the core fabric can share the HPS SDRAM controller with the processor. Additionally, the processor
can be used to configure the core fabric under program control via a dedicated 32-bit configuration port.
•HPS-to-FPGA—configurable 32-, 64-, or 128-bit Avalon/AMBA AXI interface allows high bandwidth
HPS master transactions to Logic Core
•LW HPS-to-FPGA—Light Weight 32-bit AXI interface suitable for low latency register accesses from
HPS to soft peripherals in logic core
•FPGA-to-HPS—configurable 32-, 64-, or 128-bit AMBA AXI interface
•FPGA-to-HPS SDRAM controller—up to 3 masters (command ports), 3x 64-bit read data ports and 3x
64-bit write data ports
•32-bit FPGA configuration manager
•Security
A number of new security features have been introduced for anti-tamper management, secure boot, encryption
(AES), and authentication (SHA).
Power Management
Arria 10 devices leverage the advanced 20 nm process technology, a low 0.9 V core power supply, an enhanced
core architecture, and several optional power reduction techniques to reduce total power consumption by
as much as 40% compared to Arria V devices and as much as 60% compared to Stratix V devices.
The optional power reduction techniques in Arria 10 devices include:
•SmartVoltage ID—a code is programmed into each device during manufacturing that allows a smart
regulator to operate the device at lower core VCC while maintaining performance
•Programmable Power Technology—non-critical timing paths are identified by the Quartus II software
and the logic in these paths is biased for low power instead of high performance
•VCC PowerManager—allows devices to be run at lower core voltage to trade performance for power
savings
•Low Static Power Options—devices are available with either standard static power or low static power
while maintaining performance
Furthermore, Arria 10 devices feature Altera’s industry-leading low power transceivers and include a number
of hard IP blocks that not only reduce logic resources but also deliver substantial power savings compared
to soft implementations. In general, hard IP blocks consume up to 50% less power than the equivalent soft
logic implementations.
Incremental Compilation
The Quartus II software incremental compilation feature reduces compilation time by up to 70% and preserves
performance to ease timing closure.
Incremental compilation supports top-down, bottom-up, and team-based design flows. The incremental
compilation feature facilitates modular hierarchical and team-based design flows where different designers
compile their respective sections of a design in parallel. Furthermore, different designers or IP providers
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can develop and optimize different blocks of the design independently. These blocks can then be imported
into the top level project. The incremental compilation feature enables the partial reconfiguration flow for
Arria 10 devices.
Configuration and Configuration via Protocol Using PCI Express
Arria 10 device configuration is improved for ease-of-use, speed, and cost. The devices can be configured
through a variety of techniques such as active and passive serial, fast passive parallel, JTAG, and configuration
via protocol using PCI Express including Gen3.
Configuration via protocol (CvP) using PCI Express allows the FPGA to be configured across the PCI Express
bus, simplifying the board layout and increasing system integration. Making use of the embedded PCI
Express hard IP, this technique allows the PCI Express bus to be powered up and active within the 100 ms
time allowed by the PCI Express specification. Arria 10 devices also support partial reconfiguration across
the PCI Express bus which reduces system down time by keeping the PCI Express link active while the device
is being reconfigured.
Table 16: Arria 10 Device Configuration Modes
Maximum Data
Rate (Mbps)
Maximum DCLK
Rate (MHz)
Data Width
(bits)
Remote UpdateEncryptionCompressionMode
4001001, 4YesYesYesActive
Serial
1251251—YesYesPassive
Serial
40001258, 16, 32Parallel flash
loader
YesYesPassive
Parallel
4000—1, 2, 4, 8YesYes—Configura-
tion via PCI
Express
33331———JTAG
Partial and Dynamic Reconfiguration
Partial reconfiguration allows you to reconfigure part of the FPGA while other sections continue running.
This capability is required in systems where uptime is critical, because it allows you to make updates or
adjust functionality without disrupting services.
In addition to lowering power and cost, partial reconfiguration also increases the effective logic density by
removing the necessity to place in the FPGA those functions that do not operate simultaneously. Instead,
these functions can be stored in external memory and loaded as needed. This reduces the size of the required
FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power. The
partial reconfiguration process is built on top of the proven incremental compile design flow in the Quartus II
design software.
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Partial reconfiguration in Arria 10 devices is supported through the following configuration options:
•Partial reconfiguration through the FPP x16 I/O interface
•Partial reconfiguration using PCI Express
Dynamic reconfiguration in Arria 10 devices allows transceiver data rates, protocols and analog settings to
be changed dynamically on a channel-by-channel basis while maintaining data transfer on adjacent transceiver
channels. Dynamic reconfiguration is ideal for applications that require on-the-fly multi-protocol or multi-
rate support, and both the PMA and PCS blocks within the transceiver can be reconfigured using this
technique. Dynamic reconfiguration of the transceivers can be used in conjunction with partial reconfiguration
of the FPGA to enable partial reconfiguration of both core and transceivers simultaneously.
Single Event Upset (SEU) Error Detection and Correction
Arria 10 devices offer robust and easy-to-use SEU error detection and correction circuitry.
The detection and correction circuitry includes protection for Configuration RAM (CRAM) programming
bits and user memories. The CRAM is protected by a continuously running CRC error detection circuit
with integrated ECC that automatically corrects one or two errors and detects higher order multi-bit errors.
When more than two errors occur, correction is available through reloading of the core programming file,
providing a complete design refresh while the FPGA continues to operate.
The physical layout of the Arria 10 CRAM array is optimized to make the majority of multi-bit upsets appear
as independent single-bit or double-bit errors which are automatically corrected by the integrated CRAM
ECC circuitry. In addition to the CRAM protection, the user memories also include integrated ECC circuitry
and are layout optimized for error detection and correction.
Appendix: Arria 10 SoC Developers Corner
Altera’s Arria 10 SoCs provide the combined benefits of programmable logic for high-speed data paths with
ARM processor for intelligent control functions:
•High performance programmable core logic, hard memory controllers and high speed transceivers can
be used to implement data path centric functions for 40G/100G systems including functions such
as framing, bridging, aggregation, switching, traffic management, FEC, multirate aggregation, and data
transmission.
•The integrated ARM based HPS implements intelligent control function and eliminates the need for a
local processor, thereby reducing system power, form factor, and BOM cost. By adding intelligence to
the data path, software on the ARM HPS manages and reduces system downtime and reduces the
associated operating expenses. The Dual Core ARM Cortex-A9 based HPS comes with a rich set of
embedded peripherals and associated device drivers for wide range of operating systems including Linux
and VxWorks. The resulting board support packages can be used as the basis of a number of software
applications such as:
•Operations, Administration and Maintenance (OAM)
•PCIe Root Port management
•Remote Debug and System Update
•Host offload and Algorithm acceleration
•Chassis management
•Routing and Look up management
•Error handling and system downtime management
•Rule management for deep packet inspection, packet parsing
•Audio and Video Processing
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Altera SoC: The Architecture of Choice When Productivity Matters
Productivity is the driving philosophy of Altera’s Arria 10 SoC family. By reusing hardware, software, IP,
and RTL across FPGAs and SoCs, you can reduce design effort and get products to market faster. The Dual
Core ARM Cortex-A9 MPCore-based HPS is common to both 20- and 28-nm SoCs and facilitates extensive
software code compatibility as well as tools and OS Board Support Package (BSP) reuse. The extensive tools
and OS support available as part of Altera and ARM ecosystem and the fast iteration times inherent in
software development (especially as compared to FPGA compile times) results in a highly productive
embedded and DSP development flow. In addition, Altera offers high-level automated design flows for
hardware development, such as the Altera OpenCL (a C-based hardware design flow) and DSP Builder (a
model-based hardware design flow).
Figure 9: Hardware and Software Reuse
Arria 10 Device Overview
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Altera's 20-nm SoCs and FPGAs can be reused in the following ways:
•Application Code Reuse: Because 28 nm and 20 nm SoCs share the same Dual Core ARM Cortex-A9
based HPS, any application code, board support packages, and ARM development tools developed for
one SoC family can be reused with minimal design effort.
•IP Reuse: Arria 10 SoCs share the same core logic, memory, DSP, and I/O as Arria 10 FPGAs. Hardware
intellectual property can be shared with minimal design effort. Altera also provides a fully tested and
characterized portfolio of over 200 IP cores.
•PCB Hardware Reuse: Arria 10 SoCs are also package and footprint compatible with Arria 10 FPGAs,
allowing hardware PCBs to be shared between the device categories.
•Advanced Software Development Tools:
•The ecosystem that is available on ARM and the body of software packages, middleware available for
operating systems that support ARM as well as the application development and debug tools available
for ARM provides a familiar development environment to software developers.
•Innovations such as Altera’s Virtual Target technology allow functional testing of code without the
need for hardware. By combining the most advanced multi-core debugger for ARM architectures
with FPGA-adaptivity, the ARM DS-5 Altera Edition Toolkit provides embedded software developers
an unprecedented level of full-chip visibility and control through the standard DS-5 user interface.
•Advanced Hardware Development Tools:
•Altera’s Quartus II software has faster compilation times than ever before. The Quartus II software's
support for partial reconfiguration technology allows a single PCB to support multiple protocols by
swapping protocols in the field.
•QSys System Development framework allows rapid system integration of processor and peripherals
and automates the process of generating AXI and Avalon based interconnect logic.
•DSP Builder is a plug-in to MathWorks' Simulink that allows designers to develop DSP based filters,
matrix operators and transforms using Model Based design flow and Advanced Blockset tools.
•Open Computing Language (OpenCL) programming model with Altera’s massively parallel FPGA
architecture provides a powerful solution for system acceleration. The Altera SDK for OpenCL allows
software developers to develop hardware using a C-based high-level design flow.
Single Platform of Devices that Offer Unified Control Path and Scalable Datapath
When you combine the SoC portfolio with the productivity benefits of design reuse in hardware and software,
you get a benefit that is unique to Altera’s technology. The result is an architecture that offers both unified
control path and scalable data path.
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Single Platform of Devices that Offer Unified Control Path and Scalable Datapath
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Figure 10: Unified Control Path and Scalable Data Path
SoCs and FPGAs can be used across product platforms from low cost customer premise equipment to metro
and access service provider equipment all the way to core and transmission equipment. For example, the
low-cost Cyclone®V SoC offers a fully integrated system-on-a-chip device for the low end of a product
portfolio that is ideal for customer premise, small cell routers, and enterprise routing. On the other end of
the spectrum, Arria 10 and Stratix 10 SoCs offer performance and a high level of system integration on the
high end of the product portfolio for access, networking, and transmission equipment.
Unified Control: Because all 28-nm and 20-nm SoCs feature a common Dual ARM Cortex-A9 based HPS,
there is extensive software tool reuse, operating system board support packages (BSP) reuse and a high degree
of software code compatibility across the devices and the end product portfolio.
Scalable Datapath: Altera’s SoC offers a portfolio of devices that meet the price, power, performance, logic
density, memory bandwidth, and transceiver bandwidth of an entire product portfolio. This scalability both
simplifies the system architecture and enhances productivity through design reuse and protocol IP reuse.
Differentiation through Customization
Designers today can choose between many competing technologies: off the shelf processors, ASSPs, ASICs,
and SoCs. Altera’s SoCs stand out from these competing technologies because they allow maximum
customization. Designers can implement their intellectual property in software running on the ARM or in
hardware running on the programmable logic. The high speed serial I/O and memory interfaces allow a
high degree of customization and flexibility. Designers can choose a standard protocol or memory standard
or they can implement a custom protocol or memory controller and still use the embedded PHY circuitry
to bypass the controller logic. Altera offers fully characterized turnkey IP cores for a number of communication
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interfaces, memories, and DSP functions, allowing Altera devices to offer the largest variety of interface and
feature support than any off the shelf processor or ASSP. The design cycles for Altera’s SoCs are a fraction
of ASIC design cycles and offer a much lower risk path compared to an ASIC.
Figure 11: Differentiation through Customization
ARM Cortex-A9
NEON/FPU
L1 Cache
1.5 GHz
ARM Cortex-A9
NEON/FPU
L1 Cache
1.5 GHz
512 KB Shared L2 Cache
High-Bandwidth Interconnect with Acceleration Coherent Ports
Up to 48 Transceivers
Over 250 Protocols Supported
Hard PCIe Controller IP
Hard 10G/40G KR FEC
Up to 660 KLEs
Over 42 Mbps On-Chip Memory
Over 3,350 DSP Multipliers,
Over 1 TFLOP
DDR4, DDR3, Hybrid Memory
Cube, LPDDR3, and
RLDRAM3 Support
PHY-Only Option for Custom
Memory Controllers
Multi-Port Front End Allows
Sharing of Ports
Communication Interface Custom Logic and DSP Memory Controller
Customize in
Software
Customize in
Hardware
A New, More Productive DSP Design Flow
With Altera’s SoCs, a more productive design flow for DSP design is now available. For the first time, DSP
and embedded developers who may be unfamiliar to FPGA and HDL design can develop hardware and take
advantage of the remarkable DSP performance available with Altera’s SoCs.
In this design flow, DSP and embedded developers begin by running DSP algorithms directly on the ARM
HPS. This a natural place to begin as, in many cases, C/C++ are the very languages in which these algorithms
have been conceived in the first place. The Dual Core ARM Cortex-A9 MPCore features a double precision
FPU and a NEON co-processor for 128-bit SIMD co-processor and is ideal for closed loop control, audio,
video, and multimedia processing. The inherent productivity of software design cycles and iterations as
compared to FPGA compilation times reduces system compile times drastically. When more performance
is required, these software algorithms can be then profiled to identify bottlenecks and subsequently become
candidates for hardware acceleration. Hardware accelerators can share data and computed results directly
with ARM processor’s L2 Cache via the Acceleration Coherency Port (ACP) that manages data coherency
without having to incur the penalty of a full L2 Cache flush.
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To develop these hardware accelerators, Altera offers two high-level automated design tools:
•With Altera’sOpenCL design flow, hardware accelerators are created by coding the algorithm in a C-
based high-level language. Using an automatic compiler, instruction streams are then developed and
implemented as hardware running on the SoC. In this case, the OpenCL host code is run directly on the
Dual ARM processor whereas the OpenCL kernels are implemented as hardware accelerators running
in the logic core. By having an integrated processor on chip, the need for an external host processor to
implement OpenCL host code is eliminated. For more information about OpenCL and the design flow,
refer to the OpenCL for Altera FPGAs: Accelerating Performance and Design Productivity page.
•With Altera’sDSP Builder technology, system definition and simulation is performed using the industry-
standard MathWorks Simulink tools. The DSP Builder Signal Compiler block reads Simulink Model
Files (.mdl) that are built using DSP Builder and MegaCore blocks and generates VHDL files and Tcl
scripts for synthesis, hardware implementation, and simulation. This technology allows the automatic
generation timing-optimized register transfer level (RTL) code based on high-level Simulink design
descriptions. This is a significant productivity savings compared to the hours or days required to hand-
optimize HDL code. In addition, advanced blockset DSP Builder libraries are available for commonly
used DSP operations and transforms. For more information, refer to the DSP Builder page.
Related Information
•OpenCL for Altera FPGAs: Accelerating Performance and Design Productivity
•DSP Builder
Document Revision History
Table 17: Document Revision History
ChangesVersionDate
Added product names to tables in "Arria 10 FPGA Family
Plan" and "Arria 10 SoC Family Plan" sections.
2013.07.09July 2013
Initial release.2013.06.10June 2013
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10AX066K2F35I2SGES 10AX115N1F40I2SGES 10AX066H3F34I3SGES 10AT115U2F45E2SGES
10AS066K2F35I2SGES 10AX115S1F45I2SGES 10AX115N4F40I4SGES 10AX115S2F45I2SGES
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