2ED020I12FIXT - INFINEON TECHNOLOGIES AG

2ED020I12-FI

Dual IGBT Driver IC

Power Managment & Drives

Final Datasheet, September 2007

Never stop thinking.

Edition 2007-09-10

Published by Infineon Technologies AG,

Am Campeon 1-12,

D-85579 Neubiberg

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2ED020I12-FI

Revision History: 2007-09-10 Final Datasheet

Previous Version: Preliminary Datasheet V3.2 2ED020I12-FI

Page Subjects (major changes since last revision)

12 Update Operating Range

21 Update Application Advices

Type Ordering Code Package Packaging

2ED020I12-FI SP0002-65782 PG-DSO-18-2 Tape&Reel

2ED020I12-FI

Final Data

Final Datasheet 3 September 2007

PG-DSO-18-2

Dual IGBT Driver IC

2ED020I12-FI

Product Highlights

• Fully operational to ±1.2 kV

• Power supply operating range from 14 to 18 V

• Gate drive currents of +1 A / –2 A

• Matched propagation delay for both channels

• High dV/dt immunity

• Low power consumption

• General purpose operational amplifie r

• General purpose comparator

Features

• Floating high side driver

• Undervoltage lockout for both channels

•3.3 V and 5 V TTL compatible inputs

• CMOS Schmitt-triggered inputs with pull-down

• Non-inverting inputs

• Interlocking inputs

• Dedicated shutdown input with pull-up

• RoHS compliant

High and Low Side Driver

2ED020I12-FI

Overview

Final Datasheet 4 September 2007

Final Data

1Overview

The 2ED020I12-FI is a high voltage, high speed power MOSFET and IGBT drive r with

interlocking high and l ow side referenced outputs. The floating hig h side driver may be

supplied directly or by means of a bootstrap diode and capacitor. In addition to the logic

input of each driver the 2ED020I12-FI is equipped with a d edicate d shutdown input. All

logic inputs are compatible with 3.3 V and 5 V TTL. The output drivers feature a high

pulse current buffer stage designed for minimum driver cross-conducti on. Propagation

delays are matched to simplify use in high frequency applications. Both drivers are

designed to drive an N-channel power MOSFET or IGBT which operate up to 1.2 kV. In

addition, a general purpose operational amplifier and a general purpose comparator are

provided which may be used for instance for current measurement or overcurrent

detection.

High and Low Side Driver

2ED020I12-FI

Pin Configuration and Functionality

Final Datasheet 5 September 2007

Final Data

2 Pin Configuration and Functionality

2.1 Pin Configuration

VSH

GNDH

OP+

OutL

VSL

P-DSO-18-2 (300mil)

n.c.

OP -

OPO

CP+

2ED020I12-FI

GND

OutHInL

CPO

InH

GNDH

CP -

GNDL

Figure 1 Pin Configuration (top vi ew )

2.2 Pin Definitions and Functions

Pin Symbol Function

1InH Logic input for hi gh side driver

2InL Logic input for low side driver

3SD Logic input for shutdown of both drivers

4GND Common ground

5CPO Open collector output of general purpose comparator

6CP– Inverting input of general purp ose comparator

7CP+ Non-inverting input of general purpose comparator

8OPO Output of general purpose OP

Table 1 Pin Description

High and Low Side Driver

2ED020I12-FI

Pin Configuration and Functionality

Final Datasheet 6 September 2007

Final Data

9OP– Inverting input of general purp ose OP

10 OP+ Non-inverting input of general purpose OP

11 GNDL Low side power ground 1)

12 OutL Low side gate driver output

13 VSL Low side supply voltage

14 n.c. (not connected)

15 n.e. (not existing)

16 n.e. (not existing)

17 GNDH High side (power) ground

18 VSH High side supply voltag e

19 OutH High side gate driver output

20 GNDH High side (power) ground

1) Please note : GNDL has to be connected directly to GND

Pin Symbol Function

Table 1 Pin Description (cont’d )

High and Low Side Driver

2ED020I12-FI

Block Diagram

Final Datasheet 7 September 2007

Final Data

3 Block Diagram

CPO

InH

Input

Logic

Delay

RX Logic

UVLO

Voltage

Supply

High Side

UVLO

Voltage

Supply

OPO

OP+

OP -

Low Side

CP+

CLT

CP -

InL

VCC

GND

VSH

OutH

GNDH

OutL

GNDL

VSL

Figure 2 Block Diagram

High and Low Side Driver

2ED020I12-FI

Functional Des cription

Final Datasheet 8 September 2007

Final Data

4 Functional Description

4.1 Power Supply

The power supply of both sides, “VSL” and “VSH”, is monitored by an undervoltage

lockout block (UVLO) which enables operation of the corresponding side when the

supply voltage reaches the “on” threshold. Afterwards the internal voltage reference and

the biasing circuit are enabled. When the supply voltage (VSL, VSH) drops below the

“off” threshold, the circuit is disabled.

4.2 Logic Inputs

The logic inputs InH, InL and SD are fed into Schmitt-Triggers with thresholds compatible

to 3.3V and 5V TTL. When SD is enabled (low), InH and InL are di sa bled. If InH is high

(while InL is low), OutH is enabled and vice versa. However, if both signals are high, they

are internally disabled until one of them gets low again. This is due to the interlocking

logic of the device. See Figure 3 (section 4.7).

4.3 Gate Driver

2ED020I12-FI features two hard-switching gate drivers with N-channel output stages

capable to source 1A and to sink 2A peak current. Both drivers are equipped with active-

low-clamping capabil ity. Furthermore, they feature a large ground bounce rugged ness

in order to compensate ground bounces caused by a turn-off of the driven IGBT.

4.4 General Purpose Operational Amplifier

This general purpose operational amplifier can be applied for current measurement of

the driven low-side IGBT. It is dedicated for fast operation with a gai n of at least 3. The

OP is equipped with a -0.1 to 2V input stage and a rail-to-rail output stage which is

capable to drive ± 5mA.

4.5 General Purpose Comparator

The general purpose comparator can be applied for overcurrent detection of the low side

IGBT. A dedicated offset as well as a pull-up and pull-down resistor has been introduced

to its inputs for security reasons.

4.6 Coreless Transformer (CLT)

In order to enable signal transmission across the isolation barrier between low-side and

high-side driver, a transformer based on CLT-Technology is employed. Signals, that are

to be transmitted, are specially encoded by the transmitter and correspondingly restored

by the receiver. In this way EMI due to va ri ations of GNDH (dVGNDH/dt) or the magnetic

flux density (dΗ/dt) can be suppresed.To co mpensate the additiona l propagation delay

High and Low Side Driver

2ED020I12-FI

Functional Des cription

Final Datasheet 9 September 2007

Final Data

of transmitter, level shifter and receiver, a dedicated propagation delay is introduced into

the low-side driver.

4.7 Diagrams

InH

InL

/SD

OutH

OutL

Figure 3 Input/Output Timing Diagram

High and Low Side Driver

2ED020I12-FI

Electrical Parameters

Final Datasheet 10 September 2007

Final Data

5 Electrical Parameters

5.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded

may lead to destruction of the integrated circuit. Unless otherwise noted all

parameters refer to GND.

Parameter Symbol Limit Values Unit Remarks

min. max.

High side ground GNDH – 1200 1200 V

High side supply voltage VSH – 0.3 20 V1)

High side gate dri ver output OutH – 0.3 VSH + 0.3 V1)

Low side ground GNDL – 0.3 5.3 V

Low side supply voltage VSL – 0.3 20 V2)

Low side gate driver output OutL – 0.3 VSL + 0.3 V3)

Logic input voltages

(InH, InL, SD)VIN – 0.3 5.3 V

OP input voltages

(OP–, OP+) VOP – 0.3 5.3 V4)

OP output voltage VOPO – 0.3 5.3 V

CP input voltages

(CP–, CP+) VCP – 0.3 5.3 V4)

CP output voltage VCPO – 0.3 5.3 V

CP output maximal sink

current ICPO — 5 mA

High side ground, voltage

transient dVGNDH /dt – 50 50 V/ns

ESD Capability VESD — 2 kV 5)Human

Body Model

Package power dis ipa ti o n

@TA = 25°C PD—1.4 W6)

Thermal resistance (both

chips active), junction to

ambient

RTHJA —90 K/W 7)

High and Low Side Driver

2ED020I12-FI

Electrical Parameters

Final Datasheet 11 September 2007

Final Data

5.2 Operating Range

Note: Within the operating range the IC operates as described in the functional

description. Unless otherwise noted all parameters refer to GND.

Thermal resistance (high

side chip), junction to

ambient

RTHJA(HS) —110 K/W 6)

Thermal resistance (low

side chip), junction to

ambient

RTHJA(LS) —110 K/W 6)

Junction temperature TJ—150 °C

Storage temperature TS– 55 150 °C

1) With reference to high side ground GNDH.

2) With respect to both GND and GNDL.

3) With respect to GNDL.

4) Please note the different specifications for the operating range (section 5.2).

5) According to EIA/JESD22-A 114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor).

6) Considering Rth(both chips active)=90K/W

7) Device soldered to reference PCB without cooling area

Parameter Symbol Limit Values Unit Remarks

min. max.

High side ground GNDH – 1200 1200 V

High side supply voltage VSH 14 18 V1)

Low side supply voltage VSL 14 18 V2)

Logic input voltages

(InH, InL, SD)VIN 0 5 V

OP input voltages

(OP–, OP+) VOP – 0.1 2 V

CP input voltages

(CP–, CP+) VCP – 0.1 2 V

Parameter Symbol Limit Values Unit Remarks

min. max.

High and Low Side Driver

2ED020I12-FI

Electrical Parameters

Final Datasheet 12 September 2007

Final Data

5.3 Electrical Characteristics

Note: The electrical characteristics involve the spread of values guaranteed for the

supply voltages, load and junction temperature given below. Typical values

represent the median values, which a re related to production processes. Un less

otherwise noted all voltages are given with respect to ground (GND).

VSL = VSH – GNDH = 15 V, CL = 1 nF, TA = 25 °C. Positive currents are as sumed

to be flowing into pins.

Junction temperature TJ– 40 105 °C Industrial

applications,

useful

lifetime

87600h

Junction temperature TJ– 40 125 °C Other

applications,

useful

lifetime

15000h

1) With reference to high side ground GNDH.

2) With respect to both GND and GNDL.

Voltage Supply

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

High side

leakage current IGNDH — 0 — µAGNDH = 1.2 kV

GNDL = 0 V

High side quiescent

supply current IVSH —2.4 3.2 mA VSH = 15 V1)

—2.3 3.2 mA VSH = 15 V1)

TJ = 125 °C

High side undervoltage

lockout, upper threshold VVSH1) 10.9 12.2 13.5 V

High side undervoltage

lockout, lower threshold VVSH1) —11.2 — V

High side undervoltage

lockout hysteresis ∆VVSH 0.7 11.3 V

Parameter Symbol Limit Values Unit Remarks

min. max.

High and Low Side Driver

2ED020I12-FI

Electrical Parameters

Final Datasheet 13 September 2007

Final Data

Low side quiescent

supply current IVSL —3.9 5.0 mA VSL = 15 V

3.9 5.5 mA VSL = 15 V

TJ = 125 °C

Low side undervoltage

lockout, upper threshold VVSL 10.7 12 13.3 V

Low side undervoltage

lockout, lower threshold VVSL —11 — V

Low side undervoltage

lockout hysteresis ∆VVSL 0.7 11.3 V

Logic Inputs

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

Logic “1” input voltages

(InH, InL, SD)VIN 2 — — V

Logic “0” input voltages

(InH, InL, SD)VIN — — 0.8 V

Logic “1” input currents

(InH, InL) IIN —40 55 µA VIN = 5 V

Logic “0” input currents

(InH, InL) IIN — 0 — µA VIN = 0 V

Logic “1” input currents

(SD)IIN — 0 — µA VIN = 5 V

Logic “0” input currents

(SD)IIN –60 –40 —µA VIN = 0 V

1) With reference to high side ground GNDH.

Voltage Supply (cont’d)

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

Gate Drivers

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

High side high level

output voltage VVSH –

VOutH

—1.4 1.7 V IOutH = –1mA

VInH = 5V

High side low level

output voltage V

1) With reference to high side ground GNDH.

OutH1) — — 0.1 V IOutH = 1mA

VInH = 0V

Low side high level

output voltage VVSL –

VOutL

—1.4 1.7 V IOutL = –1mA

VInL = 5V

Low side low level

output voltage VOutL — — 0.1 V IOutL = 1mA

VInL = 0V

Output high peak

current (OutL, OutH) IOut — — – 1 A VIN = 5 V

VOut = 0 V

Output low peak current

(OutL, OutH) IOut 2 — — A VIN = 0 V

VOut = 15 V

High side active low

clamping VOutH1) —2.6 3 V InH =0V, VSH open

IOutH =200mA

—2.7 3.2 VInH =0V, VSH open

IOutH =200mA

TJ = 125 °C

Low side active low

clamping VOutL —2.6 3 V InL =0V, VSL open

IOutL =200mA

—2.7 3.2 VInL =0V, VSL open

IOutL =200mA

TJ = 125 °C

High and Low Side Driver

2ED020I12-FI

Electrical Parameters

Final Datasheet 14 September 2007

Final Data

Dynamic Characteristics

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

Turn-on propagati on

delay tON —85 105 ns GNDH = 0 V

20% Vout

—95 120 ns GNDH = 0 V

20% Vout

TJ = 125 °C

High and Low Side Driver

2ED020I12-FI

Electrical Parameters

Final Datasheet 15 September 2007

Final Data

Turn-off propagation

delay tOFF —85 115 ns 80% Vout

—100 130 ns 80% Vout

TJ = 125 °C

Shutdown propagation

delay tSD —85 115 ns 80% Vout

—100 130 ns 80% Vout

TJ = 125 °C

Turn-on rise time tr—20 40 ns 20% to 80% Vout

—30 50 ns 20% to 80% Vout

TJ = 125 °C

Turn-off fall time tf—20 35 ns 80% to 20% Vout

—25 40 ns 80% to 20% Vout

TJ = 125 °C

Delay mismatch (high &

low side turn-on/off) ∆t — 15 25 ns TJ = 25°C

see Figure 6

—15 30 ns TJ = 125°C

see Figure 6

Minimum turn-on input

(InH, InL) pulse width tpON —50 75 ns 1)

—55 80 ns 1) TJ = 12 5°C

Minimum turn-off input

(InH, InL) pulse width tpOFF —50 75 ns 1)

—55 80 ns 1) TJ = 12 5 °C

1) InH-Pulses shorter than the “minimum turn-on(off) input pulse width” are prolong ed to 50ns (See Figure 7). InL-

Input doesn´t have this feature.

General Purpose Operational Amplifier OP

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

OP input offset voltage ∆VIN –10 010 mV

OP input offset voltage

drift VDrift —±15 —µV/K

OP input high currents

(OP–, OP+) IIN — 0 0.2 µA VIN = 2 V

Dynamic Characteristics (cont’d)

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

High and Low Side Driver

2ED020I12-FI

Electrical Parameters

Final Datasheet 16 September 2007

Final Data

OP input low currents

(OP–, OP+) IIN – 0.2 0 — µA VIN = 0 V

OP high output voltage VOPO 4.9 — — V VOP– = 0 V

VOP+ = 2 V

OP low output voltage VOPO — — 0.1 V VOP– = 2 V

VOP+ = 0 V

OP output source

current IOPO — — – 5 mA VOP+ = 2 V

VOP– = 0 V

VOPO = 0 V

OP output sink current IOPO 5 — — mA VOP+ = 0 V

VOP– = 2 V

VOPO = 5 V

OP open loop gain AOL —120 —dB

OP gain-bandwidth

product A x BW —20 —MHz 1)

OP phase margin 2) Φ—70 — ° 1)

1) Design value

2) Due to inevitable parasitics a minimal gain of 3 is recommended

General Purpose Comparator CP

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

CP input offset voltage ∆VIN –45 –30 –15 mV VCP+ = VCP-

CP input high current ICP– —20 35 µA VCP– = 5V

CP input low current ICP+ –35 –20 —µA VCP+ = 0 V

CP low output voltage VCPO — — 0.2 V VCP+ = 2 V

ICPO = 1 mA

CP output leakage

current ICPO — — 5 µA VCP+ = 0 V

VCP– = 2 V

VCPO = 5 V

General Purpose Operational Amplifier OP (cont’ d)

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

High and Low Side Driver

2ED020I12-FI

Electrical Parameters

Final Datasheet 17 September 2007

Final Data

CP switch-on delay td—100 —ns RCPO = 4.7kΩ

Vres = 5V

VCPO = 4V

CP switch-off delay td—300 —ns RCPO = 4.7kΩ

Vres = 5V

VCPO = 1V

General Purpose Comparator CP (cont’d)

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

High and Low Side Driver

2ED020I12-FI

Package Outline

Final Datasheet 18 September 2007

Final Data

6 Package Outline

Note: dimensions are given in mm.

6.1 Soldering Profile

The soldering profile qua lified for 2ED0 20I12 -FI (according to the standard IPC/JEDEC

J-STD-020C) is moisture sensitivity level 3. The peak reflow temperature for its package

(volume < 350 mm3) is 260 +0/-5 °C.

High and Low Side Driver

2ED020I12-FI

Diagrams

Final Datasheet 19 September 2007

Final Data

7 Diagrams

0.8V

80% 80%

20% 20%

InH/L

OutH/L

tON

tOFF

Figure 4 Switching Time Waveform Definition

/SD

OutH/L

tSD

0.8V

80%

Figure 5 Shutdown Waveform Definition

InL

InH

OutL

OutH

0.8V

80% 80%

20% 20%

tOFFL

tONH

tOFFH

tONL

High and Low Side Driver

2ED020I12-FI

Diagrams

Final Datasheet 20 September 2007

Final Data

∆t = max (|tONH - tOFFL| , |tOFFH - tONL|)

Figure 6 Delay Matching Waveform Definitions

InH

OutH

50ns 50ns

Figure 7 Short InH-Pulses Prolongation

High and Low Side Driver

2ED020I12-FI

Application Advices

Final Datasheet 21 September 2007

Final Data

8 Application Advices

8.1 Operational Amplifier

To minimize the current consumption when the operational amplifier is not used, it is

necessary to connect both inputs properly, e.g connect OP+ to 5V and OP- to 0V or vice

versa.

On the other hand, the operational amplifier cannot operate with a follower configuration

, i.e OP- = OPO. A minimum gain of 3 has to be used so that its output OPO has a stable

behaviour.

8.2 Power Supply

a) The connection of a capacitor (>10nF) as close as possible to the supply pins VSH,

VSL is recommended for avoiding that possible oscillations in the supply voltage can

cause erroneous operation of the output driver stage. Total value of capacitance

connected to the supply terminals has to be determined by taking into account

gatecharge, peak current, su pply voltage and kind of power supply.

b) If a bootstrap power supply for the high side driver is applied, a resistor of 10Ω

minimum in series with the bootstrap diode is recommended.

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