HCC/HCF40102B - STMicroelectronics

HCC/HCF40102B

HCC/HCF40103B

8-STAGE PRESETTABLESYNCHRONOUS DOWN COUNTERS

DESCRIPTION

.SYNCHRONOUS OR ASYNCHRONOUS

PRESET

.MEDIUM-SPEED OPERATION : fCL = 3.6MHz

(TYP.) @ VDD = 10V

.CASCADABLE

.QUIESCENT CURRENT SPECIFIED TO 20V

FOR HCC DEVICE

.5V, 10V AND 15VPARAMETRIC RATINGS

.INPUTCURRENTOF100nAAT18VAND25°C

FOR HCC DEVICE

.100% TESTEDFOR QUIESCENT CURRENT

.MEETSALLREQUIREMENTSOFJEDECTEN-

TATIVE STANDARD No. 13 A, ”STANDARD

SPECIFICATIONS FOR DESCRIPTION OF ”B”

SERIESCMOS DEVICES”

June 1989

The HCC40102B,HCC40103B, (extended tempera-

turerange) and the HCF40102B,HCF40103B (inter-

mediatetemperature range) aremonolithic integrated

circuits,available in 16-lead dual in-line plastic orce-

ramic package. The HCC/HCF40102B,and

HCC/HCF40103B consistofan8-stagesynchronous

downcounterwithasingleoutputwhichisactivewhen

the internal count is zero. The HCC/HCF40102B is

configured as twocascaded 4-bit BCD counters, and

theHCC/HCF40103B contains a single 8-bit binary

counter. Each typehas control inputsforenabling or

disabling the clock, for clearing the counter to its

maximum count, and for presetting the counter

eithersynchronously or asynchronously. All control

inputs and the CARRY-OUT/ZERO-DETECT out-

put are active-low logic. In normal operation, the

counter is decremented by one count on each posi-

tive transition of the CLOCK. Counting is inhibited

when the CARRY-IN/COUNTER ENABLE (CI/CE)

input is high. The CARRY-OUT/ZERO-DETEC

(CO/ZD) output goes low when the count reaches

zero if the CI/CE input is low, and remains low for

one full clock period. When the SYNCHRONOUS

PRESET-ENABLE (SPE) input is low, data at the

JAM input is clocked into the counter on the next

positiveclocktransitionregardless ofthestateofthe

CI/CE input. When the ASYNCHRONOUS

PRESET-ENABLE (APE) input is low, data at the

(Plastic Package) F

(CeramicPackage)

(ChipCarrier)

ORDERCODES :

HCC401XXBF HCF401XXBEY

HCF401XXBC1

PIN CONNECTIONS

40102B 2-DECADE BCD TYPE

40103B 8-BIT BINARY TYPE

1/13

FUNCTIONAL DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VDD* Supply Voltage :HCC Types

HCF Types – 0.5 to + 20

– 0.5 to + 18 V

ViInput Voltage – 0.5 to VDD + 0.5 V

IIDC Input Current (any one input) ±10 mA

Ptot Total Power Dissipation (per package)

Dissipation per Output Transistor

for Top = Full Package-temperature Range

200

100

Top Operating Temperature : HCC Types

HCF Types –55to+125

–40to+85 °C

°C

stg Storage Temperature – 65 to + 150 °C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

VDD Supply Voltage : HCC Types

HCF Types 3to18

3to15 V

IInput Voltage 0 to VDD V

Top Operating Temperature : HCC Types

HCF Types – 55 to + 125

–40to+85 °C

°C

Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.

* All voltages are with respect to VSS (GND).

JAM inputs is asynchronously forced into the

counter regardless of the state of the SPE, CI/CE,

or CLOCK inputs. JAM inputs JO-J7represent two

4-bit BCD words for the HCC/HCF40102B and a

single 8-bit binary word for the HCC/HCF40103B.

When the CLEAR (CLR) input is low, the counter

is asynchronously cleared to its maximum count

(9910 for the HCC/HCF40102B and 25510 for

theHCC/HCF40103B) regardless of the state of

any other input. The precedence relationship be-

tween control input is indicated in the truth table. If

all control inputs are high at the tiemeof zero count,

the counters will jump to themaximum count, giving

a counting sequence of 100 or 256 clock pulses

long.TheHCC/HCF40102B andHCC/HCF40103B

may be cascaded using the CI/CE input and the

HCC/HCF40102B/40103B

2/13

LOGIC DIAGRAMS

40102B

40103B

Detail logic diagram for flip-flops, FF0-FF7 used in logic diagrams for 40102B and 40103B.

HCC/HCF40102B/40103B

3/13

LOGIC DIAGRAMS (continued)

40102B

TRUTH TABLE

Control Inputs

CLR APE SPE CI/CE Preset Mode Action

1 1 1 1 Inhibit Counter

1 1 1 0 Count Down

110X

Synchronous

Preset on Next Positive Clock Transition

1 0 X X Preset Asynchrounously

0XXX Asynchronous Clear to Maximum Count

Timing Diagram for 40102B and 40103B

Notes : 1. 0 = Low level

1 = Highlevel

X = Don’t care

2. Clock connected to clock input.

3. Synchronous operation : changes occur on negative-to-positive clock transitions..

JAM inputs : HCC/HCF010B ;MSD = J7, J6, J5, J4(J7 isMSB)

LSD = J3,J2, J1,J0 (J3is MSB)

HCC/HCF40103B Binary; MSB =J7, LSB =J0

HCC/HCF40102B/40103B

4/13

STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)

Test Conditions Value

VIVO|IO|V

DD TLow*25°CT

High*

Symbol Parameter (V) (V) (µA) (V) Min. Max. Min. Typ. Max. Min. Max.

Unit

ILQuiescent

Current HCC

Types

0/ 5 5 5 0.04 5 150

µA

0/10 10 10 0.04 10 300

0/15 15 20 0.04 20 600

0/20 20 100 0.08 100 3000

HCF

Types

0/ 5 5 20 0.04 20 150

0/10 10 40 0.04 40 300

0/15 15 80 0.04 80 600

VOH Output High

Voltage 0/ 5 < 1 5 4.95 4.95 4.95 V

0/10 < 1 10 9.95 9.95 9.95

0/15 < 1 15 14.95 14.95 14.95

VOL Output Low

Voltage 5/0 < 1 5 0.05 0.05 0.05 V

10/0 < 1 10 0.05 0.05 0.05

15/0 < 1 15 0.05 0.05 0.05

VIH Input High

Voltage 0.5/4.5 < 1 5 3.5 3.5 3.5

1/9 < 1 10 7 7 7

1.5/13.5 < 1 15 11 11 11

VIL Input Low

Voltage 4.5/0.5 < 1 5 1.5 1.5 1.5 V

9/1 < 1 10 3 3 3

13.5/1.5 < 1 15 4 4 4

IOH Output

Drive

Current HCC

Types

0/ 5 2.5 5 – 2 – 1.6 – 3.2 – 1.15

0/ 5 4.6 5 – 0.64 – 0.51 – 1 – 0.36

0/10 9.5 10 – 1.6 – 1.3 – 2.6 – 0.9

0/15 13.5 15 – 4.2 – 3.4 – 6.8 – 2.4

HCF

Types

0/ 5 2.5 5 – 1.53 – 1.36 – 3.2 – 1.1

0/ 5 4.6 5 – 0.52 – 0.44 – 1 – 0.36

0/10 9.5 10 – 1.3 – 1.1 – 2.6 – 0.9

0/15 13.5 15 – 3.6 – 3.0 – 6.8 – 2.4

IOL Output

Sink

Current HCC

Types

0/ 5 0.4 5 0.64 0.51 1 0.36

0/10 0.5 10 1.6 1.3 2.6 0.9

0/15 1.5 15 4.2 3.4 6.8 2.4

HCF

Types

0/ 5 0.4 5 0.52 0.44 1 0.36

0/10 0.5 10 1.3 1.1 2.6 0.9

0/15 1.5 15 3.6 3.0 6.8 2.4

IIH,I

IL Input

Leakage

Current

HCC

Types 0/18 Any Input 18 ±0.1 ±10–5 ±0.1 ±1µA

HCF

Types 0/15 15 ±0.3 ±10–5 ±0.3 ±1

CIInput Capacitance Any Input 5 7.5 pF

Low=–55°CforHCC device : – 40°C for HCF device.

High= + 125°C for HCC device : + 85°C for HCF device.

TheNoise Margin for both ”1” and”0” levelis : 1Vmin.with VDD = 5V, 2V min.with VDD = 10V, 2.5 V min. withVDD =15V.

HCC/HCF40102B/40103B

5/13

DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb =25°C, CL= 50pF, RL= 200kΩ,

typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall time = 20ns)

Test Conditions Value

Symbol Parameter VDD (V) Min. Typ. Max. Unit

tPHL,

tPLH

Propagation

Delay Time Clock to-out 5 300 600 ns

10 130 260

15 95 190

Carry In/Counter

Enable-to-output 5200400

10 90 180

15 65 130

Asynchronous

Preset

Enable-to-output

5 650 1300

10 300 600

15 200 400

Clear-to-output 5 375 750 ns

10 180 360

15 100 200

tTHL,t

TLH Transition Time 5 100 200

10 50 100 ns

15 40 80

tWPulse Width Clock Pulse

Width 5 300 150 ns

10 180 90

15 80 40

CLR Pulse

Width 5 320 160 ns

10 160 80

15 100 50

APE Pulse Width 5 360 180

10 160 80 ns

15 120 60

tsetup Setup Time SPE Setup Time 5 280 140 ns

10 140 70

15 100 50

JAM Setup Time 5 200 100 ns

10 80 40

15 60 30

fCL Maximum Clock Input Frequency 5 0.7 1.4

10 1.8 3.6 MHz

15 2.4 4.8

HCC/HCF40102B/40103B

6/13

Output Low (sink) Current Characteristics. Output High (source) Current Characteristics.

Typical Transition Timevs. Load Capacitance. Typical Propagation Delay Time vs. Load Capacit-

ance (clock to CO/ZD).

Typical Dynamic Power Dissipation vs. Fre-

quency.

Typical Maximum ClockInput Frequency vs.

Supply Voltage.

HCC/HCF40102B/40103B

7/13

TYPICAL APPLICATIONS

Divide-by-”N” Counter. Programmable Timer.

Microprocessor Interrupt Timer.

Synchronous Cascading.

*An output spike (160ns @ VDD = 5V) occurs whenever two or

more devices are cascaded in the parallel-clocked mode be-

cause the clock-to-carry out delay is greater than the carry-in-to-

carry out delay. This spike is eliminated by gating the out put

of the last device with the clock as shown.

HCC/HCF40102B/40103B

8/13

Input Current.

Input Voltage.

TEST CIRCUITS

Quiescent Device Current.

Maximum ClockFrequency.

Dynamic Power Dissipation.

HCC/HCF40102B/40103B

9/13

Plastic DIP16 (0.25) MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 0.050

P001C

HCC/HCF40102B/40103B

10/13

Ceramic DIP16/1 MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 20 0.787

B 7 0.276

D 3.3 0.130

E 0.38 0.015

e3 17.78 0.700

F 2.29 2.79 0.090 0.110

G 0.4 0.55 0.016 0.022

H 1.17 1.52 0.046 0.060

L 0.22 0.31 0.009 0.012

M 0.51 1.27 0.020 0.050

N 10.3 0.406

P 7.8 8.05 0.307 0.317

Q 5.08 0.200

P053D

HCC/HCF40102B/40103B

11/13

PLCC20 MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 9.78 10.03 0.385 0.395

B 8.89 9.04 0.350 0.356

D 4.2 4.57 0.165 0.180

d1 2.54 0.100

d2 0.56 0.022

E 7.37 8.38 0.290 0.330

e 1.27 0.050

e3 5.08 0.200

F 0.38 0.015

G 0.101 0.004

M 1.27 0.050

M1 1.14 0.045

P027A

HCC/HCF40102B/40103B

12/13

Information furnished is believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsability for the

consequences of use of such informationnor forany infringement of patents orother rights of third parties which mayresults from its use. No

license is granted by implication or otherwiseunder any patent or patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronicsproductsare notauthorizedforuse ascritical componentsin life supportdevices or systemswithout express

written approvalof SGS-THOMSON Microelectonics.

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HCC/HCF40102B/40103B

13/13