1.2 A, Low VIN, Low Dropout
Linear Regulator
ADP1754/ADP1755
Rev. B
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FEATURES
Maximum output current: 1.2 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: <2 µA
Very low dropout voltage: 105 mV @ 1.2 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
7 fixed output voltage options with soft start
0.75 V to 2.5 V (ADP1754)
Adjustable output voltage option with soft start
0.75 V to 3.0 V (ADP1755)
High PSRR
65 dB @ 1 kHz
65 dB @ 10 kHz
54 dB @ 100 kHz
23 V rms at 0.75 V output
Stable with small 4.7 µF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection
APPLICATIONS
Server computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems
TYPICAL APPLICATION CIRCUITS
TOP VIEW
(Not to Scale)
ADP1754
1
2
3
4
VIN
VIN
100kΩ
4.7µF 4.7µF
V
IN
= 1.8
V
V
OUT
= 1.5
V
VIN
EN
12
11
10
9
VOUT
VOUT
VOUT
SENSE
5678
PG GND SS NC
PG
16 15 14 13
VIN VIN VOUT VOUT
10nF
07722-001
Figure 1. ADP1754 with Fixed Output Voltage, 1.5 V
TOP VIEW
(Not to Scale)
ADP1755
1
2
3
4
VIN
VIN
100kΩ
4.7µF 4.7µF
V
IN
= 1.8
V
V
OUT
= 0.5V(1 + R1/R2)
VIN
EN
12
11
10
9
VOUT
VOUT
VOUT
ADJ
5678
PG GND SS NC
PG
16 15 14 13
VIN VIN VOUT VOUT
10nF
R2
R1
07722-002
Figure 2. ADP1755 with Adjustable Output Voltage, 0.75 V to 3.0 V
GENERAL DESCRIPTION
The ADP1754/ADP1755 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to
1.2 A of output current. These low VIN/VOUT LDOs are ideal for
regulation of nanometer FPGA geometries operating from 2.5 V
down to 1.8 V I/O rails, and for powering core voltages down to
0.75 V. Using an advanced proprietary architecture, the ADP1754/
ADP1755 provide high power supply rejection ratio (PSRR) and
low noise, and achieve excellent line and load transient response
with only a small 4.7 µF ceramic output capacitor.
The ADP1754 is available in seven fixed output voltage options.
The ADP1755 is the adjustable version, which allows output
voltages that range from 0.75 V to 3.0 V via an external divider.
The ADP1754/ADP1755 allow an external soft start capacitor
to be connected to program the startup. A digital power-good
output allows power system monitors to check the health of the
output voltage.
The ADP1754/ADP1755 are available in a 16-lead, 4 mm × 4 mm
LFCSP, making them not only very compact solutions, but also
providing excellent thermal performance for applications that
require up to 1.2 A of output current in a small, low profile
footprint.
ADP1754/ADP1755
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitor, Recommended Specifications .. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Soft Start Function (ADP1754/ADP1755) ............................. 11
Adjustable Output Voltage (ADP1755) ................................... 12
Enable Feature ............................................................................ 12
Power-Good Feature .................................................................. 12
Reverse Current Protection Feature ........................................ 13
Applications Information .............................................................. 14
Capacitor Selection .................................................................... 14
Undervoltage Lockout ............................................................... 15
Current-Limit and Thermal Overload Protection ................. 15
Thermal Considerations ............................................................ 15
PCB Layout Considerations ...................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
2/10—Rev. A to Rev. B
Changes to Table 4 ............................................................................ 5
Changes to Ordering Guide .......................................................... 19
4/09—Rev. 0 to Rev. A
Changes to Adjustable Output Voltage Accuracy (ADP1755)
Parameter, Table 1 ............................................................................. 3
Changes to Table 3 ............................................................................ 5
10/08—Revision 0: Initial Version
ADP1754/ADP1755
Rev. B | Page 3 of 20
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 1.6 V (whichever is greater), IOUT = 10 mA, CIN = COUT = 4.7 µF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN T
J = −40°C to +125°C 1.6 3.6 V
OPERATING SUPPLY CURRENT1 I
GND I
OUT = 500 A 90 µA
I
OUT = 100 mA 400 µA
I
OUT = 100 mA, TJ = −40°C to +125°C 800
µA
I
OUT = 1.2 A 1.1 mA
I
OUT = 1.2 A, TJ = −40°C to +125°C 1.4
mA
SHUTDOWN CURRENT IGND-SD EN = GND, VIN = 1.6 V 2 6 µA
EN = GND, VIN = 1.6 V, TJ = −40°C to +85°C 30 µA
EN = GND, VIN = 3.6 V, TJ = −40°C to +85°C 100 µA
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy
(ADP1754)
VOUT I
OUT = 10 mA −1 +1 %
I
OUT = 10 mA to 1.2 A −1.5 +1.5 %
10 mA < IOUT < 1.2 A, TJ = −40°C to +125°C −2 +2 %
Adjustable Output Voltage Accuracy
(ADP1755)2
VADJ I
OUT = 10 mA 0.495 0.5 0.505 V
I
OUT = 10 mA to 1.2 A 0.495 0.505 V
10 mA < IOUT < 1.2 A, TJ = −40°C to +125°C 0.490 0.510 V
LINE REGULATION VOUT/VIN V
IN = (VOUT + 0.4 V) to 3.6 V, TJ = −40°C to +125°C −0.3 +0.3 %/ V
LOAD REGULATION3 VOUT/IOUT I
OUT = 10 mA to 1.2 A, TJ = −40°C to +125°C 0.6 %/A
DROPOUT VOLTAGE4 V
DROPOUT I
OUT = 100 mA, VOUT ≥ 1.8 V 10 mV
I
OUT = 100 mA, VOUT ≥ 1.8 V, TJ = −40°C to +125°C 16 mV
I
OUT = 1.2 A, VOUT ≥ 1.8 V 105 mV
I
OUT = 1.2 A, VOUT ≥ 1.8 V, TJ = −40°C to +125°C 200 mV
START-UP TIME5 t
START-UP C
SS = 0 nF, IOUT = 10 mA 200 µs
C
SS = 10 nF, IOUT = 10 mA 5.2 ms
CURRENT-LIMIT THRESHOLD6 I
LIMIT 1.5 2 5 A
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD T
J rising 150 °C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
PG OUTPUT LOGIC LEVEL
PG Output Logic High PGHIGH 1.6 V ≤ VIN ≤ 3.6 V, IOH < 1 µA 1.0 V
PG Output Logic Low PGLOW 1.6 V ≤ VIN ≤ 3.6 V, IOL < 2 mA 0.4 V
PG Output Delay from EN Transition
Low to High
1.6 V ≤ VIN ≤ 3.6 V, CSS = 10 nF 5.5 ms
PG OUTPUT THRESHOLD
Output Voltage Falling PGFALL 1.6 V ≤ VIN ≤ 3.6 V −10 %
Output Voltage Rising PGRISE 1.6 V ≤ VIN ≤ 3.6 V −6.5 %
EN INPUT
EN Input Logic High VIH 1.6 V ≤ VIN ≤ 3.6 V 1.2 V
EN Input Logic Low VIL 1.6 V ≤ VIN ≤ 3.6 V 0.4 V
EN Input Leakage Current VI-LEAKAGE EN = VIN or GND 0.1 1 µA
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLORISE T
J = −40°C to +125°C 1.58 V
Input Voltage Falling UVLOFALL T
J = −40°C to +125°C 1.25 V
Hysteresis UVLOHYS T
J = 25°C 100 mV
SOFT START CURRENT ISS 1.6 V ≤ VIN ≤ 3.6 V 0.6 0.9 1.2 µA
ADJ INPUT BIAS CURRENT (ADP1755) ADJI-BIAS 1.6 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +125°C 10 150 nA
SENSE INPUT BIAS CURRENT SNSI-BIAS 1.6 V ≤ VIN ≤ 3.6 V 10 µA
ADP1754/ADP1755
Rev. B | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VOUT = 0.75 V 23 µV rms
10 Hz to 100 kHz, VOUT = 2.5 V 65 µV rms
POWER SUPPLY REJECTION RATIO PSRR VIN = VOUT + 1 V, IOUT = 10 mA
1 kHz, VOUT = 0.75 V 65 dB
1 kHz, VOUT = 2.5 V 56 dB
10 kHz, VOUT = 0.75 V 65 dB
10 kHz, VOUT = 2.5 V 56 dB
100 kHz, VOUT = 0.75 V 54 dB
100 kHz, VOUT = 2.5 V 51 dB
1 Minimum output load current is 500 A.
2 Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the
tolerances of resistors used.
3 Based on an end-point calculation using 10 mA and 1.2 A loads. See for typical load regulation performance. Figure 6
4 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.6 V.
5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 95% of its nominal value.
6 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1 CMIN TA = −40°C to +125°C 3.3 µF
CAPACITOR ESR RESR T
A = −40°C to +125°C 0.001 0.1 Ω
1 The minimum input and output capacitance should be greater than 3.3 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with this LDO.
ADP1754/ADP1755
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND −0.3 V to +3.6 V
VOUT to GND −0.3 V to +3.6 V
EN to GND −0.3 V to +3.6 V
SS to GND −0.3 V to +3.6 V
PG to GND −0.3 V to +3.6 V
SENSE/ADJ to GND −0.3 V to +3.6 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP1754/ADP1755 may be damaged if the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated. In applications with moderate power
dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits.
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). TJ is calculated using the following formula:
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in × 3 in circuit
board. Refer to JEDEC JESD51-7 for detailed information about
board construction. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12 document,
Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than through
a single path as in thermal resistance, θJB. Therefore, ΨJB thermal
paths include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful in
real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and the power
dissipation (PD) using the following formula:
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for more
detailed information about ΨJB.
THERMAL RESISTANCE
θJAand ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Ψ
JB Unit
16-Lead LFCSP with Exposed Pad (CP-16-4) 42 25.5 °C/W
ESD CAUTION
ADP1754/ADP1755
Rev. B | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1VIN
2VIN
3VIN
4EN
11 VOUT
12 VOUT
10 VOUT
9SENSE
5
PG
6
GND
7
SS
8
NC
15 VIN
16 VIN
14 VOU
T
13 VOU
T
TOP VIEW
(Not to Scale)
ADP1754
NOTES
1. NC = NO CONNECT.
2
. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
07722-003
PIN 1
INDICATOR
1VIN
2VIN
3VIN
4EN
11 VOUT
12 VOUT
10 VOUT
9ADJ
5
PG
6
GND
7
SS
8
NC
15 VIN
16 VIN
14 VOU
T
13 VOU
T
TOP VIEW
(Not to Scale)
ADP1755
NOTES
1. NC = NO CONNECT.
2
. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
07722-004
Figure 3. ADP1754 Pin Configuration Figure 4. ADP1755 Pin Configuration
Table 5. Pin Function Descriptions
ADP1754
Pin No.
ADP1755
Pin No. Mnemonic Description
1, 2, 3, 15,
16
1, 2, 3, 15,
16
VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all five
VIN pins must be connected to the source.
4 4 EN
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
5 5 PG
Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is in
shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal
output voltage, PG immediately transitions low.
6 6 GND Ground.
7 7 SS Soft Start. A capacitor connected to this pin determines the soft start time.
8 8 NC Not Connected. No internal connection.
9 N/A SENSE
Sense. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop
between the regulator output and the load.
N/A 9 ADJ Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
10, 11, 12,
13, 14
10, 11, 12,
13, 14
VOUT Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that all
five VOUT pins must be connected to the load.
17 (EPAD) 17 (EPAD) Exposed
paddle
(EPAD)
The exposed pad on the bottom of the LFCSP package enhances thermal performance and is
electrically connected to GND inside the package. It is recommended that the exposed pad be
connected to the ground plane on the board.
ADP1754/ADP1755
Rev. B | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 1.9 V, VOUT = 1.5 V, IOUT = 10 mA, CIN = 4.7 µF, COUT = 4.7 µF, TA = 25°C, unless otherwise noted.
1.520
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
–40 –5 25 85 125
OUTPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-005
Figure 5. Output Voltage vs. Junction Temperature
1.520
1.515
1.505
1.495
1.510
1.500
1.490
1.485
1.480
10 100 1k 10k
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
07722-006
Figure 6. Output Voltage vs. Load Current
1.8 3.63.43.23.02.82.62.42.22.0
INPUT VOLTAGE (V)
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
1.520
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
OUTPUT VOLTAGE (V)
07722-007
Figure 7. Output Voltage vs. Input Voltage
1200
0
200
400
600
800
1000
–40 –5 25 85 125
GROUND CURRENT (µA)
JUNCTION TEMPERATURE (°C)
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-008
Figure 8. Ground Current vs. Junction Temperature
1200
1000
800
600
400
200
0
10 100 1k 10k
GROUND CURRENT (µA)
LOAD CURRENT (mA)
07722-009
Figure 9. Ground Current vs. Load Current
1200
1000
800
600
400
200
0
1.8 3.63.43.23.02.82.62.42.22.0
GROUND CURRENT (µA)
INPUT VOLTAGE (V)
LOAD = 400mA
LOAD = 800mA
LOAD = 10mA
LOAD = 100mA
LOAD = 1.2A
07722-010
Figure 10. Ground Current vs. Input Voltage
ADP1754/ADP1755
Rev. B | Page 8 of 20
100
90
70
80
60
50
40
30
20
10
0
–40 85603510–15
SHUTDOWN CURRENT (µA)
TEMPERATURE (°C)
1.9V
2.0V
2.4V
2.6V
3.0V
3.6V
07722-011
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
1 10 100 1k 10k
LOAD CURRENT (mA)
DROPOUT VOLTAGE (V)
1.6V
2.5V
07722-012
Figure 12. Dropout Voltage vs. Load Current, VOUT = 1.6 V, 2.5 V
2.60
2.45
2.55
2.50
2.40
2.35
2.30
2.25
2.20
2.3 2.5 2.72.4 2.6 2.8
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-013
Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 2.5 V
4500
2500
4000
3500
3000
2000
1500
1000
500
0
2.3 2.5 2.72.4 2.6 2.8
GROUND CURRENT (µA)
INPUT VOLTAGE (V)
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-014
Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V
CH1 500mA Ω
BW
CH2 50mV
BW
M10µs A CH1 380mA
1
2
T 10.40%
T
I
LOAD
1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV
V
OUT
50mV/DIV
V
IN
= 3.6V
V
OUT
= 1.5V
07722-015
Figure 15. Load Transient Response, CIN = 4.7 μF, COUT = 4.7 μF
CH1 500mA Ω
BW
CH2 20mV
BW
M10µs A CH1 340mA
1
2
T 10.20%
T
I
LOAD
1mA TO 1.2A LOAD STEP, 2.5A/µs,
500mA/DIV
V
OUT
20mV/DIV
V
IN
= 3.6V
V
OUT
= 1.5V
07722-016
Figure 16. Load Transient Response, CIN = 22 μF, COUT = 22 μF
ADP1754/ADP1755
Rev. B | Page 9 of 20
1
2
T
CH1 500mV
BW
CH2 5mV
BW
M10µs A CH4 800mV
T 9.60%
V
IN
3V TO 3.5V INPUT VOLTAGE STEP, 2V/µs
V
OUT
5mV/DIV
V
OUT
= 1.5V
C
IN
= C
OUT
= 4.7µF
07722-017
Figure 17. Line Transient Response, Load Current = 1200 mA
70
0
10
20
30
40
50
60
0.0001 0.001 0.01 0.1 1 10
NOISE (µV rms)
LOAD CURRENT (A)
0.75V
1.5V
2.5V
07722-018
Figure 18. Noise vs. Load Current and Output Voltage
10
1
0.1
0.01
10 100 1k 10k 100k
NOISE SPECTRAL DENSITY (µV/ Hz)
FREQUENCY (Hz)
07081-019
0.75V
1.5V
2.5V
Figure 19. Noise Spectral Density vs. Output Voltage, ILOAD = 10 mA
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
1.2A
800mA
400mA
100mA
10mA
07722-020
Figure 20. Power Supply Rejection Ratio vs. Frequency,
VOUT = 0.75 V, VIN = 1.75 V
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
1.2A
800mA
400mA
100mA
10mA
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
07722-121
Figure 21. Power Supply Rejection Ratio vs. Frequency,
VOUT = 1.5 V, VIN = 2.5 V
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
1.2A
800mA
400mA
100mA
10mA
07722-122
Figure 22. Power Supply Rejection Ratio vs. Frequency,
VOUT = 2.5 V, VIN = 3.5 V
ADP1754/ADP1755
Rev. B | Page 10 of 20
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
1.5V/1200mA 1.5V/10mA
2.5V/1200mA 2.5V/10mA
0.75V/1200mA 0.75V/10mA
07722-123
Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage
ADP1754/ADP1755
Rev. B | Page 11 of 20
THEORY OF OPERATION
The ADP1754/ADP1755 are low dropout linear regulators that
use an advanced, proprietary architecture to provide high power
supply rejection ratio (PSRR) and excellent line and load transient
response with only a small 4.7 µF ceramic output capacitor. Both
devices operate from a 1.6 V to 3.6 V input rail and provide up
to 1.2 A of output current. Supply current in shutdown mode is
typically 2 µA.
UVLO
VOUTVIN
SENSE
SS
SHORT-CIRCUIT
AND THERMAL
PROTECTION
R1
0.5V
REF R2
SHUTDOWN
EN
PG
GND
ADP1754 REVERSE POLARITY
PROTECTION
PG
DETECT
0.9µA
0
7722-021
Figure 24. ADP1754 Internal Block Diagram
UVLO
VOUTVIN
ADJ
SS
SHORT-CIRCUIT
AND THERMAL
PROTECTION
0.5V
REF
SHUTDOWN
EN
PG
GND
ADP1755
REVERSE POLARITY
PROTECTION
PG
DETECT
0.9µA
0
7722-022
Figure 25. ADP1755 Internal Block Diagram
Internally, the ADP1754/ADP1755 consist of a reference, an
error amplifier, a feedback voltage divider, and a PMOS pass
transistor. Output current is delivered via the PMOS pass
transistor, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the
feedback voltage is lower than the reference voltage, the gate
of the PMOS device is pulled lower, allowing more current
to pass and increasing the output voltage. If the feedback
voltage is higher than the reference voltage, the gate of the
PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
The ADP1754 are available in seven fixed output voltage
options between 0.75 V and 2.5 V. The ADP1754 allows for
connection of an external soft start capacitor that controls the
output voltage ramp during startup. The ADP1755 is the
adjustable version with an output voltage that can be set to a
value between 0.75 V and 3.0 V by an external voltage divider.
Both devices are controlled by an enable pin (EN).
SOFT START FUNCTION (ADP1754/ADP1755)
For applications that require a controlled startup, the ADP1754/
ADP1755 provide a programmable soft start function. The
programmable soft start is useful for reducing inrush current
upon startup and for providing voltage sequencing. To implement
soft start, connect a small ceramic capacitor from SS to GND.
Upon startup, a 0.9 µA current source charges this capacitor.
The ADP1754/ADP1755 start-up output voltage is limited by
the voltage at SS, providing a smooth ramp-up to the nominal
output voltage. The soft start time is calculated as follows:
tSS = VREF × (CSS/ISS) (1)
where:
tSS is the soft start period.
VREF is the 0.5 V reference voltage.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (0.9 µA).
When the ADP1754/ADP1755 is disabled (using the EN pin), the
soft start capacitor is discharged to GND through an internal 100 Ω
resistor.
2.50
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
02468
VOLTAGE (V)
TIME (ms)
10
EN
1nF
4.7nF
10nF
07722-023
Figure 26. VOUT Ramp-Up with External Soft Start Capacitor
ADP1754/ADP1755
Rev. B | Page 12 of 20
CH1 2.0V
BW
CH2 500mV
BW
M40µs A CH1 920mV
1
2
T 9.8%
T
07722-024
EN
V
OUT
500mV/DIV V
OUT
= 1.5V
C
IN
= C
OUT
= 4.7µF
Figure 27. VOUT Ramp-Up with Internal Soft Start
ADJUSTABLE OUTPUT VOLTAGE (ADP1755)
The output voltage of the ADP1755 can be set over a 0.75 V to
3.0 V range. The output voltage is set by connecting a resistive
voltage divider from VOUT to ADJ. The output voltage is calcu-
lated using the following equation:
VOUT = 0.5 V × (1 + R1/R2) (2)
where:
R1 is the resistor from VOUT to ADJ.
R2 is the resistor from ADJ to GND.
The maximum bias current into ADJ is 150 nA. Therefore, to
achieve less than 0.5% error due to the bias current, use values
less than 60 kΩ for R2.
ENABLE FEATURE
The ADP1754/ADP1755 use the EN pin to enable and disable
the VOUT pins under normal operating conditions. As shown
in Figure 28, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN crosses
the inactive threshold, VOUT turns off.
2
CH1 500mV
BW
CH2 500mV
BW
M2.0ms A CH1 1.05V
1
T 29.6%
T
07722-025
EN
V
OUT
500mV/DIV V
OUT
= 1.5V
C
IN
= C
OUT
= 4.7µF
Figure 28. Typical EN Pin Operation
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
The EN pin active/inactive thresholds are derived from the VIN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 29 shows typical EN active/inactive thresholds
when the input voltage varies from 1.6 V to 3.6 V.
1.1
0.5
0.6
0.7
0.8
0.9
1.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
EN THRESHOLD (V)
INPUT VOLTAGE (V)
EN ACTIVE
EN INACTIVE
07722-026
Figure 29. Typical EN Pin Thresholds vs. Input Voltage
POWER-GOOD FEATURE
The ADP1754/ADP1755 provide a power-good pin, PG, to
indicate the status of the output. This open-drain output
requires an external pull-up resistor to VIN. If the part is in
shutdown mode, current-limit mode, thermal shutdown, or
if it falls below 90% of the nominal output voltage, PG imme-
diately transitions low. During soft start, the rising threshold of
the power-good signal is 93.5% of the nominal output voltage.
The open-drain output is held low when the ADP1754/ADP1755
have sufficient input voltage to turn on the internal PG transistor.
An optional soft start delay can be detected. The PG transistor
is terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling.
Regulator input voltage brownouts or glitches trigger a power
no-good if VOUT falls below 90%.
A normal power-down triggers a power no-good when VOUT
drops below 90%.
ADP1754/ADP1755
Rev. B | Page 13 of 20
2
2
CH1 1.0V
BW
CH3 1.0V
BW
CH2 500mV
BW
M40.0µs A CH3 900mV
1
T 50.40%
T
07722-027
V
IN
1V/DIV
V
OUT
500mV/DIV
PG
1V/DIV
V
OUT
= 1.5V
C
IN
= C
OUT
= 4.7µF
REVERSE CURRENT PROTECTION FEATURE
The ADP1754/ADP1755 have additional circuitry to protect
against reverse current flow from VOUT to VIN. For a typical
LDO with a PMOS pass device, there is an intrinsic body diode
between VIN and VOUT. When VIN is greater than VOUT, this
diode is reverse-biased. If VOUT is greater than VIN, the intrinsic
diode becomes forward-biased and conducts current from VOUT
to VIN, potentially causing destructive power dissipation. The
reverse current protection circuitry detects when VOUT is greater
than VIN and reverses the direction of the intrinsic diode connec-
tion, reverse-biasing the diode. The gate of the PMOS pass
device is also connected to VOUT, keeping the device off.
Figure 32 shows a plot of the reverse current vs. the VOUT to VIN
differential.
Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V)
4000
3500
3000
2500
2000
1500
1000
500
0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
REVERSE CURRENT (µA)
V
OUT
– V
IN
(V)
07722-132
2
2
CH1 1.0V
BW
CH3 1.0V
BW
CH2 500mV
BW
M40.0µs A CH3 900mV
1
T 50.40%
T
07722-028
V
IN
1V/DIV
V
OUT
500mV/DIV
PG
1V/DIV
V
OUT
= 1.5V
C
IN
= C
OUT
= 4.7µF
Figure 32. Reverse Current vs. VOUT − VIN
Figure 31. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.5 V)
ADP1754/ADP1755
Rev. B | Page 14 of 20
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP1754/ADP1755 are designed for operation with small,
space-saving ceramic capacitors, but they can function with most
commonly used capacitors as long as care is taken with the
effective series resistance (ESR) value. The ESR of the output
capacitor affects the stability of the LDO control loop. A mini-
mum of 3.3 µF capacitance with an ESR of 500 mΩ or less is
recommended to ensure the stability of the ADP1754/ADP1755.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP1754/ADP1755 to
large changes in load current. Figure 33 and Figure 34 show the
transient responses for output capacitance values of 4.7 µF and
22 µF, respectively.
1
2
T
CH1 500mA
BW
CH2 50mV
BW
M1µs A CH1 380mA
T 11.2%
I
LOAD
1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV
V
OUT
50mV/DIV
V
IN
= 3.6V, V
OUT
= 1.5V
C
IN
= C
OUT
= 4.7µF
07722-133
Figure 33. Output Transient Response, COUT = 4.7 μF
1
2
T
CH1 500mA
BW
CH2 20mV
BW
M1µs A CH1 340mA
T 11.0%
I
LOAD
1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV
V
OUT
20mV/DIV
V
IN
= 3.6V, V
OUT
= 1.5V
C
IN
= C
OUT
= 22µF
07722-134
Figure 34. Output Transient Response, COUT = 22 μF
Input Bypass Capacitor
Connecting a 4.7 µF capacitor from the VIN pin to GND
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance are encountered. If output capacitance greater than
4.7 µF is required, it is recommended that the input capacitor be
increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP1754, as long as they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufac-
tured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. X5R or
X7R dielectrics with a voltage rating of 6.3 V or 10 V are recom-
mended. Y5V and Z5U dielectrics are not recommended, due
to their poor temperature and dc bias characteristics.
Figure 35 shows the capacitance vs. voltage bias characteristics
of an 0805 case, 4.7 µF, 10 V, X5R capacitor. The voltage stability
of a capacitor is strongly influenced by the capacitor size and
voltage rating. In general, a capacitor in a larger package or with
a higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about ±15% over the −40°C to
+85°C temperature range and is not a function of package size
or voltage rating.
5
4
3
2
1
0
02468
CAPACITANCE (µF)
VOLTAGE BIAS (V)
10
07722-031
MURATA P/N GRM219R61A475KE34
Figure 35. Capacitance vs. Voltage Bias Characteristics
Equation 3 can be used to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
CEFF = COUT × (1 − TEMPCO) × (1 − TOL) (3)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
ADP1754/ADP1755
Rev. B | Page 15 of 20
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT = 4.46 F at 1.8 V, as shown in Figure 35.
Substituting these values in Equation 3 yields
CEFF = 4.46 F × (1 − 0.15) × (1 − 0.1) = 3.41 F
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temper-
ature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP1754/ADP1755, it is
imperative that the effects of dc bias, temperature, and toler-
ances on the behavior of the capacitors be evaluated for each
application.
UNDERVOLTAGE LOCKOUT
The ADP1754/ADP1755 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 1.58 V. This ensures that the
ADP1755/ADP1755 inputs and the output behave in a predicta-
ble manner during power-up.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1754/ADP1755 are protected against damage due to
excessive power dissipation by current-limit and thermal
overload protection circuits. The ADP1754/ADP1755 are
designed to reach current limit when the output load reaches
2 A (typical). When the output load exceeds 2 A, the output
voltage is reduced to maintain a constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature begins to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C (typical), the output is turned on again and the output
current is restored to its nominal value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP1754/ADP1755 reach current limit so
that only 2 A is conducted into the short. If self-heating of the
junction becomes great enough to cause its temperature to
rise above 150°C, thermal shutdown activates, turning off the
output and reducing the output current to zero. As the junction
temperature cools and drops below 135°C, the output turns on
and conducts 2 A into the short, again causing the junction
temperature to rise above 150°C. This thermal oscillation between
135°C and 150°C causes a current oscillation between 2A and
0 A that continues as long as the short remains at the output.
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation should be externally
limited so that junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of the
ADP1754/ADP1755 must not exceed 125°C. To ensure that the
junction temperature stays below this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient temp-
erature, power dissipation in the power device, and thermal
resistance between the junction and ambient air (θJA). The θJA
value is dependent on the package assembly compounds used
and the amount of copper to which the GND pin and the exposed
pad (EPAD) of the package are soldered on the PCB. Table 6 shows
typical θJA values for the 16-lead LFCSP for various PCB copper
sizes. Table 7 shows typical ΨJB values for the 16-lead LFCSP.
Table 6. Typical θJA Values
Copper Size (mm2) θJA (°C/W), LFCSP
01 130
100 80
500 69
1000 54
6400 42
1 Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
Copper Size (mm2) ΨJB (°C/W) @ 1 W
100 32.7
500 31.5
1000 25.5
The junction temperature of the ADP1754/ADP1755 can be
calculated from the following equation:
TJ = TA + (PD × θJA) (4)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (5)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation can
be simplified as follows:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA} (6)
As shown in Equation 6, for a given ambient temperature, input-
to-output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 36
through Figure 41 show junction temperature calculations for
different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
ADP1754/ADP1755
Rev. B | Page 16 of 20
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-032
Figure 36. 6400 mm2 of PCB Copper, TA = 25°C, LFCSP
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-033
Figure 37. 500 mm2 of PCB Copper, TA = 25°C, LFCSP
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD =
800mA
LOAD = 1.2A
07722-034
Figure 38. 0 mm2 of PCB Copper, TA = 25°C, LFCSP
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
LOAD = 100mA
07722-035
Figure 39. 6400 mm2 of PCB Copper, TA = 50°C, LFCSP
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-036
Figure 40. 500 mm2 of PCB Copper, TA = 50°C, LFCSP
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD =
800mA
LOAD = 1.2A
07722-037
Figure 41. 0 mm2 of PCB Copper, TA = 50°C, LFCSP
ADP1754/ADP1755
Rev. B | Page 17 of 20
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, can be used to estimate the
junction temperature rise. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
TJ = TB + (PD × ΨJB) (7)
Figure 42 through Figure 45 show junction temperature calcula-
tions for different board temperatures, load currents, VIN to
VOUT differentials, and areas of PCB copper.
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-038
Figure 42. 500 mm2 of PCB Copper, TB = 25°C, LFCSP
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
07722-039
Figure 43. 500 mm2 of PCB Copper, TB = 50°C, LFCSP
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
LOAD = 100mA
07722-040
Figure 44. 1000 mm2 of PCB Copper, TB = 25°C, LFCSP
140
120
100
80
60
40
20
0
0.25 0.75 1.25 1.75 2.25 2.75
VIN – VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
MAX JUNCTION
TEMPERATURE
LOAD = 10mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
LOAD = 100mA
07722-041
Figure 45. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP
ADP1754/ADP1755
Rev. B | Page 18 of 20
PCB LAYOUT CONSIDERATIONS
07722-045
Heat dissipation from the package can be improved by increas-
ing the amount of copper attached to the pins of the ADP1754/
ADP1755. However, as shown in Table 6 , a point of diminishing
returns is eventually reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
Here are a few general tips when designing PCBs:
• Place the input capacitor as close as possible to the VIN
and GND pins.
• Place the output capacitor as close as possible to the VOUT
and GND pins.
• Place the soft start capacitor as close as possible to the SS pin.
• Connect the load as close as possible to the VOUT and
SENSE pins (ADP1754) or to the VOUT and ADJ pins
(ADP1755).
Use of 0603 or 0805 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.
Figure 47. Typical Board Layout—Top Side
0
7722-046
0
7722-044
Figure 48. Typical Board Layout—Bottom Side
Figure 46. Evaluation Board
ADP1754/ADP1755
Rev. B | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
2.25
2.10 SQ
1.95
16
5
13
8
9
12 1
4
1.95 BSC
PIN 1
INDICATOR TOP
VIEW
4.00
BSC SQ
3.75
BSC SQ
COPLANARITY
0.08
(BOTTOM VIEW )
12° MAX
1.00
0.85
0.80 SEATING
PLANE
0.35
0.30
0.25
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
0.65 BSC
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
0.25 MIN
072808-A
0.75
0.60
0.50
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Output Voltage (V) Package Description Package Option
ADP1754ACPZ-0.75R7 −40°C to +125°C 0.75 16-Lead LFCSP_VQ CP-16-4
ADP1754ACPZ-1.0-R7 −40°C to +125°C 1.0 16-Lead LFCSP_VQ CP-16-4
ADP1754ACPZ-1.1-R7 −40°C to +125°C 1.1 16-Lead LFCSP_VQ CP-16-4
ADP1754ACPZ-1.2-R7 −40°C to +125°C 1.2 16-Lead LFCSP_VQ CP-16-4
ADP1754ACPZ-1.5-R7 −40°C to +125°C 1.5 16-Lead LFCSP_VQ CP-16-4
ADP1754ACPZ-1.8-R7 −40°C to +125°C 1.8 16-Lead LFCSP_VQ CP-16-4
ADP1754ACPZ-2.5-R7 −40°C to +125°C 2.5 16-Lead LFCSP_VQ CP-16-4
ADP1755ACPZ-R7 −40°C to +125°C Adjustable from 0.75 to 3.0 16-Lead LFCSP_VQ CP-16-4
ADP1755ACPZ −40°C to +125°C Adjustable from 0.75 to 3.0 16-Lead LFCSP_VQ CP-16-4
ADP1754-1.5-EVALZ 1.5 Evaluation Board
ADP1754-BL1-EVZ Blank Evaluation Board
ADP1755-EVALZ Adjustable Evaluation Board
ADP1755-BL1-EVZ Blank Evaluation Board
1 Z = RoHS Compliant Part.
ADP1754/ADP1755
Rev. B | Page 20 of 20
NOTES
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07722-0-2/10(B)
