HM5283206 Series
81
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Oct. 20, 1994 Initial issue Y. Saiki T. Kizaki
0.1 Nov. 11, 1994 Commands Operaion
Change of column block and DQ input at the block
write cycle and column mask location
Operation of HM5283206 Series
Change of col umn block and the or der of bur st oper at i on
Addition of description for read command to write or
block write command interval (3)
Change of figure for bank active command interval
AC Characteristics
tOH min: 2/2/2 ns to 3/3/3 ns
tHZ (CL = 1) max: 10/12/14 ns to 13/15/17 ns
tCKS min: 3/2/2 ns to 3/3/3 ns
tCKH min: 1/2/2 ns to 1/1/1 ns
tRC min: 90/100/125 ns to 90/108/135 ns
tRAS min: 60/70/80 ns to 60/72/90 ns
Timing Waveforms
Change of Read Cycle/Write Cycle, Color Register
Set Cycle and Block Write Cycle
Y. Saiki T. Kizaki
0.2 Nov. 20, 1995 Deletion of HM5283206TT Series
Change of Simplified State Diagram
Commands Operation
Change of description for Commands Operation
C hange of figure for C olum n address and w rite com m and BL = 2
Change of description for Graphic Commands
Change of Command Truth Table
Change of CKE Truth Table
Change of Function Truth Table
Change of notes 5
Addition of notes 6
Operation of HM5283206 Series
Addition of note for read with auto precharge,
write with auto precharge and power down mode
Change of figure for write per bit, block write,
read command to read command interval,
write command to write command interval
and write command to precharge command
AC Characteristics
Change of figure for Test load (B)
DC Characteristics
ICC1 max: TBD to 180/150/120 mA
ICC2 max: TBD to 5/5/5 mA
ICC2 max: TBD to 3/3/3 mA
ICC2 max: TBD to 75/60/50 mA
ICC3 max: TBD to 10/10/10 mA
ICC3 max: TBD to 80/65/55 mA
ICC4 (CL = 1) max: TBD to 170/140/110 mA
ICC4 (CL = 2) max: TBD to 240/200/160 mA
ICC4 (CL = 3) max: TBD to 280/240/190 mA
Y. Saiki T. Kizaki