US3010ACW - UNISEM - Datasheet.Live

US3010/3010A

4-1

Rev. 1.1

5/18/98

TYPICAL APPLICATIONTYPICAL APPLICATION

DESCRIPTIONDESCRIPTION

The US3010 family of controller ICs are specifically de-

signed to meet Intel specification for Pentium II and

Pentium Pro microprocessor applications as well as

the next generation P6 family processors. These prod-

ucts feature a patented topology that in combination

with a few external components as shown in the typical

application circuit ,will provide in excess of 16A of out-

put current for an on- board DC/DC converter while auto-

matically providing the right output voltage via the 5 bit

internal DAC .These devices also feature, loss less cur-

rent sensing by using the Rds-on of the high side

Power MOSFET as the sensing resistor, a Power Good

window comparator that switches its open collector out-

put low when the output is outside of a ±10% window

and an OVP output. Other features of the device are ;

Undervoltage lockout for both 5V and 12V supplies , an

external programmable soft start function as well as pro-

gramming the oscillator frequency by using an external

capacitor.

Dual Layout Compatible with SC1152

Designed to meet Intel specification of VRM8.2

& VRM8.3 for Pentium II

On board DAC programs the output voltage

from 1.3V to 3.5V (US3010) & 1.8V to 3.5V for

US3010A

Loss less Short Circuit Protection

Synchronous operation allows maximum effi-

ciency

Patented architecture allows fixed frequency

operation as well as 100% duty cycle during

dynamic load

Over Voltage Protection Output

Soft Start

High current totem pole driver for direct driv-

ing of the external Power MOSFET

Power Good function

PACKAGE ORDER INFORMATIONPACKAGE ORDER INFORMATION

PRELIMINARY DATASHEET

FEATURESFEATURES

5 BIT PROGRAMMABLE SYNCHRONOUS BUCK

CONTROLLER IC

APPLICATIONSAPPLICATIONS

Pentium II & Pentium Pro processor DC to DC

converter application

Low cost Pentium with AGP

Notes: Pentium II and Pentium Pro are

trade marks of Intel Corp.

Ta (°C) Device Package VID Voltage Range

0 TO 70 US3010CW 20 pin Plastic SOIC WB 1.3V to 3.5V

0 TO 70 US3010ACW 20 pin Plastic SOIC WB 1.8V to 3.5V

12V

VID0

Power Good

3010app1-1.1

OutEn

VID1

VID2

VID3

VID4

L1 L2

C5 R2

C4 C6

R3 R5

R6 C10

C11

C1 R7

R11

OVP

R4 R10

6HDrv LDrv

SS/BstH

CS+ Gnd Vfb

D3 D2D4 D1 D0

US3010

PGd

CS-V12 V5

Ct/

AGnd

NC/

PGndH OVP

R12 R13

4-2 Rev. 1.1

5/18/98

US3010/3010A

ELECTRICAL SPECIFICATIONSELECTRICAL SPECIFICATIONS

Unless otherwise specified ,these specifications apply over ,V12 = 12V, V5 = 5V and Ta=0 to 70°C. Typical values

refer to Ta =25°C. Low duty cycle pulse testing are used which keeps junction and case temperatures equal to the

ambient temperature.

ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS

V5 supply Voltage ........................................... 7V

V12 Supply Voltage ............................................ 20V

Storage Temperature Range ................................. -65 TO 150°C

Operating Junction Temperature Range .......... 0 TO 125°C

PACKAGE INFORMATIONPACKAGE INFORMATION

20 PIN WIDE BODY PLASTIC SOIC (W)

θJA =85°C/W

TOP VIEW

Vfb

V12

LDrv

OVP

PGd

CS-

CS+

HDrv

Gnd

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS

VID Section

DAC output voltage 0.99Vs Vs 1.01Vs V

(note 1)

DAC Output Line Regulation 0.1 %

DAC Output Temp Variation 0.5 %

VID Input LO 0.4 V

VID Input HI 2V

VID input internal pull-up 27 kΩ

resistor to V5

Power Good Section

Under voltage lower trip point Vout ramping down 0.89Vs 0.90Vs 0.91Vs V

Under voltage upper trip point Vout ramping up 0.92Vs V

UV Hysterises .015Vs .02Vs .025Vs V

Over voltage upper trip point Vout ramping up 1.09Vs 1.10Vs 1.11Vs V

Over voltage lower trip point Vout ramping down 1.08Vs V

OV Hysterises .015Vs .02Vs .025Vs V

Power Good Output LO RL=3mA 0.4 V

Power Good Output HI RL=5K pull up to 5V 4.8 V

Soft Start Section

Soft Start Current CS+ =0V , CS- =5V 10 uA

US3010/3010A

4-3

Rev. 1.1

5/18/98

UVLO Section

UVLO Threshold-12V Supply ramping up 9.2 10 10.8 V

UVLO Hysterises-12V 0.3 0.4 0.5 V

UVLO Threshold-5V Supply ramping up 4.1 4.3 4.5 V

UVLO Hysterises-5V 0.2 0.3 0.4 V

Error Comparator Section

Input bias current 2uA

Input Offset Voltage -2 +2 mV

Delay to Output Vdiff=10mV 100 nS

Current Limit Section

C.S Threshold Set Current 160 200 240 uA

C.S Comp Offset Voltage -5 +5 mV

Hiccup Duty Cycle Css=0.1 uF 2%

Supply Current

Operating Supply Current CL=3000pF

V5 20

V12 14 mA

Output Drivers Section

Rise Time CL=3000pF 70 100 nS

Fall Time CL=3000pF 70 130 nS

Dead band Time CL=3000pF 100 200 300 nS

Oscillator Section

Osc Frequency Ct=150pF 190 220 250 Khz

Osc Valley 0.2 V

Osc Peak V5 V

Output Enable Section

Pull up Resistor to V5 35 kΩ

HI Threshold Voltage 2 V

LO Threshold Voltage 0.8 V

Over Voltage Section

OVP Drive Current 50 mA

Note 1: Vs refers to the set point voltage given in Table 1.

D4 D3 D2 D1 D0 Vs D4 D3 D2 D1 D0 Vs

011111.30* 11111**

011101.35* 111102.1

011011.40* 111012.2

011001.45* 111002.3

010111.50* 110112.4

010101.55* 110102.5

010011.60* 110012.6

010001.65* 110002.7

001111.70* 101112.8

001101.75* 101102.9

001011.80 101013.0

001001.85 101003.1

000111.90 100113.2

000101.95 100103.3

000012.00 100013.4

000002.05 100003.5

* Output voltage is disabled for US3010A.

** Output voltage is disabled for all versions.

Table 1 - Set point voltage vs. VID codes

4-4 Rev. 1.1

5/18/98

US3010/3010A

PIN DESCRIPTIONSPIN DESCRIPTIONS

Pin Description

LSB input to the DAC that programs the output voltage. This pin can be pulled up exter-

nally by a 10k resistor to either 3.3V or 5V supply.

Input to the DAC that programs the output voltage.This pin can be pulled up externally by

a 10kΩ resistor to either 3.3V or 5V supply.

Input to the DAC that programs the output voltage.This pin can be pulled up externally by

a 10k resistor to either 3.3V or 5V supply.

MSB input to the DAC that programs the output voltage.This pin can be pulled up exter-

nally by a 10k resistor to either 3.3V or 5V supply.

This pin selects a range of output voltages for the DAC. The voltage range for both the "A"

and the none "A" versions of the device is given in table 1.

This pin is an open collector output that switches LO when the output of the converter is

not within ±10% (typ) of the nominal output voltage.When PWRGD pin switches LO the

sat voltage is less than 0.4V at 3mA.

This pin is connected directly to the output of the Core supply to provide feedback to the

Error comparator.

This pin is connected to the Drain of the power MOSFET of the Core supply and it

provides the positive sensing for the internal current sensing circuitry. An external resis-

tor programs the C.S threshold depending on the Rds of the power MOSFET. An external

capacitor is placed in parallel with the programming resistor to provide high frequency

noise filtering.

This pin is connected to the Source of the power MOSFET for the Core supply and it

provides the negative sensing for the internal current sensing circuitry.

This pin provides the soft start for the switching regulator. An internal current source

charges an external capacitor that is conected from this pin to the GND which ramps up

the outputs of the switching regulator, preventing the outputs from overshooting as wellas

limiting the input current. The second function of the Soft Start cap is to provide long off

time for the synchronous MOSFET or the Catch diode (HICCUP) during current limiting.

This pin programs the oscillator frequency in the range of 50 kHZ to 500kHZ with an

external capacitor connected from this pin to the GND.

This pin serves as the ground pin and must be conected directly to the ground plane. A

high frequency capacitor (0.1 to 1 uF) must be connected from V5 and V12 pins to this

pin for noise free operation.

Output driver for the synchronous power MOSFET.

Output driver for the high side power MOSFET.

This pin is connected to the 12 V supply and serves as the power Vcc pin for the output

drivers.A high frequency capacitor (0.1 to 1 uF) must be connected directly from this pin

to GND pin in order to supply the peak current to the power MOSFET during the transi-

tions.

5V supply voltage.

Over voltage comparator output.

This is the output enable pin.This pin is internally pulled high through a 35kΩ resistor to

5V supply. A low signal on this pin disables the output.

No connect.

PIN# PIN SYMBOL

20 D0

19 D1

18 D2

17 D3

16 D4

4PGd

15 Vfb

6CS+

5CS-

13 SS

1Ct

10 Gnd

11LDrv

8HDrv

12 V12

2V5

3OVP

14 OUTEN

7,9 NC

US3010/3010A

4-5

Rev. 1.1

5/18/98

BLOCK DIAGRAMBLOCK DIAGRAM

Figure 1 - Simplified block diagram of the US3010/3010A.

PWM

Control V12

V12

3010Ablk1-1.2

Osc

Slope

Comp

5Bit

DAC,

Ctrl

Logic

Enable

Soft

Start &

Fault

Logic 200uA

0.9Vset

1.1Vset

Vset

Enable

UVLO

Vset

Enable

V12

PGd

CS-

CS+

LDrv

HDrv

Vfb

Over

Current

Enable

Gnd

1.18Vset

OVP

4-6 Rev. 1.1

5/18/98

US3010/3010A

12V

VID0

Power Good

3010app1-1.1

OutEn

VID1

VID2

VID3

VID4

L1 L2

C5 R2

C4 C6

R3 R5

R6 C10

C11

C1 R7

R11

OVP

R4 R10

6HDrv LDrv

SS/BstH

CS+ Gnd Vfb

D3 D2D4 D1 D0

US3010

PGd

CS-V12 V5

Ct/

AGnd

NC/

PGndH OVP

R12 R13

TYPICAL APPLICATIONTYPICAL APPLICATION

SYNCHRONOUS OPERATION

(Dual Layout with SC1152)

Figure 2- Typical application of US3010/3010A in an on board DC-DC converter providing the Core supply for the

Pentium II microprocessor.

Table of components that need to be modified to make the dual layout work for US3010A* and SC1152.

Part # R1 R2 R4 R7 R8 R9 R10 R11 C2 C5 C8 C9

SC1152 SOOVV VVSOOVO

US3010A* OVSOSOOOVVOV

S - Short O - Open V - See Unisem or Semtech parts list for the value.

* Table also applies to the none "A" version of the part.

Note 1 : R8 can be replaced with shorting wire of #20 AWG or lower. This elliminates the expensive current

sense resistor that otherwise is needed with SC1152.

US3010/3010A

4-7

Rev. 1.1

5/18/98

US3010/3010A and SC1152 Dual Layout Parts List

Ref Desig Description Qty Part # Manuf

Q1 MOSFET 1IRL3103

IRL3103S (Note 1) IR

Q2 MOSFET 1IRL3103

IRL3103S (Note 1) IR

L1 Inductor 1L=1 uH

L2 Inductor 1Core

L=2.5 uH R=2 mohm Micro Metal

C10 Capacitor ,Electrolytic 56MV1500GX ,1500uF,6.3V, Sanyo

C3 Capacitor ,Electrolytic 26MV1500GX ,1500uF,6.3V, Sanyo

C1 Capacitor ,Electrolytic 1680uF,10V, EEUFA1A681L Panasonic

C2 Capacitor , Ceramic 11 uF , SMT

C5 Capacitor , Ceramic 1220 pF , SMT

C4,6 Capacitor , Ceramic 21 uF , SMT

C9 Capacitor , Ceramic 1150 pF , X7R, SMT

C7 Capacitor , Ceramic 1470pF , SMT

C11 Capacitor , Ceramic 10.01 uF , SMT

C8 Capacitor , Ceramic 1open , SMT

R2 Resistor 12.21 kΩ , 1% ,SMT

R3 Resistor 1 10Ω , 5%, SMT , 1206 size

R4 Resistor 1Short, SMT

R5 Resistor 1 10Ω , 5%, SMT , 1206 size

R6 Resistor 1 10Ω , 5%, SMT , 1206 size

R8 Resistor 1short , #20 AWG wire

R1,7,9, Resistor 5open , SMT

10,11

R12,13 Resistor 2100 kΩ , 5%, SMT

HS1 Q1 Heatsink 16270 Thermalloy

HS2 Q2 Heatsink 16270 Thermalloy

Note 1 : For the applications where it is desirable not to use the Heatsink, the IRL3103S MOSFET in the TO263

SMT package with 1″ square of pad area using top and bottom layers of the board as a minimum is required.

4-8 Rev. 1.1

5/18/98

US3010/3010A

Application InformationApplication Information

An example of how to calculate the components for the

application circuit is given below.

Assuming, two sets of output conditions that this regu-

lator must meet,

a) Vo=2.8V , Io=14.2A, ∆Vo=185mV, ∆Io=14.2A

b) Vo=2V , Io=14.2A, ∆Vo=140mV, ∆Io=14.2A

The regulator design will be done such that it meets the

worst case requirement of each condition.

Output Capacitor Selection

The first step is to select the output capacitor. This is

done primarily by selecting the maximum ESR value

that meets the transient voltage budget of the total ∆Vo

specification. Assuming that the regulators DC initial

accuracy plus the output ripple is 2% of the output volt-

age, then the maximum ESR of the output capacitor is

calculated as :

ESR≤ =

100

1427

. mΩ

The Sanyo MVGX series is a good choice to achieve

both the price and performance goals. The 6MV1500GX

, 1500uF, 6.3V has an ESR of less than 36 mΩ typ .

Selecting 6 of these capacitors in parallel has an ESR

of ≈6 mΩ which achieves our low ESR goal.

Other type of Electrolytic capacitors from other manu-

facturers to consider are the Panasonic “FA” series or

the Nichicon “PL” series.

Reducing the Output Capacitors Using Voltage Level

Shifting Technique

The trace resistance or an external resistor from the output

of the switching regulator to the Slot 1 can be used to

the circuit advantage and possibly reduce the number

of output capacitors, by level shifting the DC regu-

lation point when transitioninig from light load to

full load and vice versa. To accomplish this, the out-

put of the regulator is typically set about half the DC

drop that results from light load to full load. For example,

if the total resistance from the output capacitors to the

Slot 1 and back to the GND pin of the device is 5mΩ and

if the total ∆I, the change from light load to full load is

14A, then the output voltage measured at the top of the

resistor divider which is also connected to the output

capacitors in this case, must be set at half of the 70 mV

or 35mV higher than the DAC voltage setting.

This intentional voltage level shifting during the load tran-

sient eases the requirement for the output capacitor ESR

at the cost of load regulation. One can show that the

new ESR requirement eases up by half the total trace

resistance. For example, if the ESR requirement of the

output capacitors without voltage level shifting must be

7mΩ then after level shifting the new ESR will only need

to be 8.5mΩ if the trace resistance is 5mΩ (7+5/2=9.5).

However, one must be careful that the combined “volt-

age level shifting” and the transient response is still within

the maximum tolerance of the Intel specification. To in-

sure this, the maximum trace resistance must be less

than:

Rs≤ 2(Vspec - 0.02*Vo - ∆Vo)/∆I

Where :

Rs=Total maximum trace resistance allowed

Vspec=Intel total voltage spec

Vo=Output voltage

∆Vo=Output ripple voltage

∆I=load current step

For example, assuming:

Vspec=±140 mV=±0.1V for 2V output

Vo=2V

∆Vo=assume 10mV=0.01V

∆I=14.2A

Then the Rs is calculated to be:

Rs≤ 2(0.140 - 0.02*2 - 0.01)/14.2=12.6mΩ

However, if a resistor of this value is used, the maximum

power dissipated in the trace (or if an external resistor is

being used) must also be considered. For example if

Rs=12.6 mΩ , the power dissipated is

(Io^2)*Rs=(14.2^2)*12.6=2.54W. This is a lot of power to

be dissipated in a system. So, if the Rs=5mΩ, then the

power dissipated is about 1W which is much more ac-

ceptable. If level shifting is not implemented, then the

maximum output capacitor ESR was shown previously

to be 7mΩ which translated to ≈ 6 of the 1500uF,

6MV1500GX type Sanyo capacitors. With Rs=5mΩ, the

maximum ESR becomes 9.5mΩ which is equivalent to

≈ 4 caps. Another important consideration is that if a

trace is being used to implement the resistor, the

power dissipated by the trace increases the case

temperature of the output capacitors which could

seriously effect the life time of the output capaci-

tors.

Output Inductor Selection

The output inductance must be selected such that un-

der low line and the maximum output voltage condition,

the inductor current slope times the output capacitor

ESR is ramping up faster than the capacitor voltage is

US3010/3010A

4-9

Rev. 1.1

5/18/98

drooping during a load current step. However if the in-

ductor is too small , the output ripple current and ripple

voltage become too large. One solution to bring the ripple

current down is to increase the switching frequency ,

however that will be at the cost of reduced efficiency and

higher system cost. The following set of formulas are

derived to achieve the optimum performance without

many design iterations.

The maximum output inductance is calculated using the

following equation :

L = ESR * C * ( Vinmin - Vomax ) / ( 2* ∆I )

Where :

Vinmin = Minimum input voltage

For Vo = 2.8 V , ∆I = 14.2 A

L =0.006 * 9000 * ( 4.75 - 2.8) / (2 * 14.2) = 3.7 uH

Assuming that the programmed switching frequency is

set at 200 KHZ , an inductor is designed using the

Micrometals’ powder iron core material. The summary

of the design is outlined below :

The selected core material is Powder Iron , the

selected core is T50-52D from Micro Metal wounded

with 8 Turns of # 16 AWG wire, resulting in 3 uH

inductance with ≈ 3 mΩ of DC resistance.

Assuming L = 3 uH and the switching frequency ; Fsw =

200 KHZ , the inductor ripple current and the output

ripple voltage is calculated using the following set of

equations :

T = 1/Fsw

T ≡ Switching Period

D ≈ ( Vo + Vsync ) / ( Vin - Vsw + Vsync )

D ≡ Duty Cycle

Ton = D * T

Vsw ≡ High side Mosfet ON Voltage = Io * Rds

Rds ≡ Mosfet On Resistance

Toff = T - Ton

Vsync ≡ Synchronous MOSFET ON Voltage=Io * Rds

∆Ir = ( Vo + Vsync ) * Toff /L

∆Ir ≡ Inductor Ripple Current

∆Vo = ∆Ir * ESR

∆Vo ≡Output Ripple Voltage

In our example for Vo = 2.8V and 14.2 A load , Assum-

ing IRL3103 MOSFET for both switches with maximum

on resistance of 19 mΩ, we have :

T = 1 / 200000 = 5 uSec

Vsw =Vsync= 14.2*0.019=0.27 V

D ≈ ( 2.8 + 0.27 ) / ( 5 - 0.27 + 0.27 ) = 0.61

Ton = 0.61 * 5 = 3.1 uSec

Toff = 5 - 3.1 = 1.9 uSec

∆Ir = ( 2.8 + 0.27 ) * 1.9 / 3 = 1.94 A

∆Vo = 1.94 * .006 = .011 V = 11 mV

Power Component Selection

Assuming IRL3103 MOSFETs as power components,

we will calculate the maximum power dissipation as fol-

lows:

For high side switch the maximum power dissipation

happens at maximum Vo and maximum duty cycle.

Dmax ≈ ( 2.8 + 0.27 ) / ( 4.75 - 0.27 + 0.27 ) = 0.65

Pdh = Dmax * Io^2*Rds(max)

Pdh= 0.65*14.2^2*0.029=3.8 W

Rds(max)=Maximum Rds-on of the MOSFET at 125°C

For synch MOSFET, maximum power dissipation hap-

pens at minimum Vo and minimum duty cycle.

Dmin ≈ ( 2 + 0.27 ) / ( 5.25 - 0.27 + 0.27 ) = 0.43

Pds = (1-Dmin)*Io^2*Rds(max)

Pds=(1 - 0.43) * 14.2^2 * 0.029 = 3.33 W

Heatsink Selection

Selection of the heat sink is based on the maximum

allowable junction temperature of the MOSFETS. Since

we previously selected the maximum Rds-on at 125°C,

then we must keep the junction below this temperature.

Selecting TO220 package gives θjc=1.8°C/W ( From the

venders’ datasheet ) and assuming that the selected

heatsink is Black Anodized , the Heat sink to Case ther-

mal resistance is ; θcs=0.05°C/W , the maximum heat

sink temperature is then calculated as :

Ts = Tj - Pd * (θjc + θcs)

Ts = 125 - 3.82 * (1.8 + 0.05) = 118 °C

With the maximum heat sink temperature calculated in

the previous step, the Heat Sink to Air thermal resis-

tance (θsa) is calculated as follows :

Assuming Ta=35 °C

∆T = Ts - Ta = 118 - 35 = 83 °CTemperature Rise

Above Ambient

θsa = ∆T/Pd

θsa = 83 / 3.82 = 22 °C/W

Next , a heat sink with lower θsa than the one calcu-

lated in the previous step must be selected. One way to

do this is to simply look at the graphs of the “Heat Sink

Temp Rise Above the Ambient” vs. the “Power Dissipa-

tion” given in the heatsink manufacturers’ catalog and

select a heat sink that results in lower temperature rise

than the one calculated in previous step. The following

heat sinks from AAVID and Thermaloy meet this crite-

ria.

Co. Part #

Thermalloy 6078B

AAVID 577002

4-10 Rev. 1.1

5/18/98

US3010/3010A

Following the same procedure for the Schottcky diode

results in a heatsink with θsa = 25 °C/W. Although it is

possible to select a slightly smaller heatsink, for sim-

plicity the same heatsink as the one for the high side

MOSFET is also selected for the synchronous MOSFET.

Switcher Current Limit Protection

The IC uses the MOSFET Rds-on as the sensing resis-

tor to sense the MOSFET current and compares to a

programmed voltage which is set externally via a resis-

tor (Rcs) placed between the drain of the MOSFET and

the “CS+” terminal of the IC as shown in the application

circuit. For example, if the desired current limit point is

set to be 22A and from our previous selection, the maxi-

mum MOSFET Rds-on=19mΩ, then the current sense

resistor, Rcs is calculated as :

Vcs=IcL*Rds=22*0.019=0.418V

Rcs=Vcs/Ib=(0.418V)/(200uA)=2.1kΩ

Where: Ib=200uA is the internal current setting of the

device

Switcher Timing Capacitor Selection

The US3010A frequency can be programmed using an

external timing capacitor. The value of Ct can be ap-

proximated using the equation below:

Switcher Output Voltage Adjust

As it was discussed earlier,the trace resistance from

the output of the switching regulator to the Slot 1 can be

used to the circuit advantage and possibly reduce the

number of output capacitors, by level shifting the DC

regulation point when transitioninig from light load to full

load and vice versa. To account for the DC drop, the

output of the regulator is typically set about half the DC

drop that results from light load to full load. For example,

if the total resistance from the output capacitors to the

Where

C=Ti g Capacitor

FSwitching Frequency

SW T

≈×

−

35 10 5

min

If, F

kHz :

CpF

200

35 10

200

175

≈××=

−

Slot 1 and back to the GND pin of the device is 5mΩ and

if the total ∆I, the change from light load to full load is

14A, then the output voltage measured at the top of the

resistor divider which is also connected to the output

capacitors in this case, must be set at half of the 70 mV

or 35mV higher than the DAC voltage setting. To do this,

the top resistor of the resistor divider, Rtop is set at 100Ω,

and the bottom resistor, Rb is calculated. For example,

if DAC voltage setting is for 2.8V and the desired output

under light load is 2.835V, then Rb is calculated using

the following formula :

Rb= 100*{Vdac /(Vo - 1.004*Vdac)} [Ω]

Rb= 100*{2.8 /(2.835 - 1.004*2.800)} = 11.76 kΩ

Select 11.8 kΩ , 1%

Note: The value of the top resistor must not exceed

100ΩΩ. The bottom resistor can then be adjusted to raise

the output voltage.

Soft Start Capacitor Selection

The soft start capacitor must be selected such that dur-

ing the start up when the output capacitors are charging

up, the peak inductor current does not reach the current

limit treshold. A minimum of 1uF capacitor insures this

for most applications. An internal 10uA current source

charges the soft start capacitor which slowly ramps up

the inverting input of the PWM comparator Vfb3. This

insures the output voltage to ramp at the same rate as

the soft start cap thereby limiting the input current. For

example, with 1uF and the 10uA internal current source

the ramp up rate is (∆V/ ∆t)=I/C = 1V/100mS. Assum-

ing that the output capacitance is 9000uF, the maxi-

mum start up current will be:

I=9000uF*(1V/100mS)=0.09A

Input Filter

It is highly recommended to place an inductor between

the system 5V supply and the input capacitors of the

switching regulator to isolate the 5V supply from the

switching noise that occurs during the turn on and off of

the switching components. Typically an inductor in the

range of 1 to 3 uH will be sufficient in this type of appli-

cation.

Switcher External Shutdown

The best way to shutdown the part is to pull down on the

soft start pin using an external small signal transistor

such as 2N3904 or 2N7002 small signal MOSFET. This

allows slow ramp up of the output, the same as the power

up.

US3010/3010A

4-11

Rev. 1.1

5/18/98

Layout Considerations

Switching regulators require careful attention to the lay-

out of the components, specifically power components

since they switch large currents. These switching com-

ponents can create large amount of voltage spikes and

high frequency harmonics if some of the critical compo-

nents are far away from each other and are connected

with inductive traces. The following is a guideline of how

to place the critical components and the connections

between them in order to minimize the above issues.

Start the layout by first placing the power components:

1) Place the input capacitors C3 and the high side

mosfet ,Q1 as close to each other as possible

2) Place the synchronous mosfet,Q2 and the Q1 as

close to each other as possible with the intention that

the source of Q1 and drain of the Q2 has the shortest

length.

3) Place the snubber R4 & C7 between Q1 & Q2.

4) Place the output inductor ,L2 and the output capaci-

tors ,C10 between the mosfet and the load with output

capacitors distributed along the slot 1 and close to it.

5) Place the bypass capacitors, C4 and C6 right next to

12V and 5V pins. C4 next to the 12V, pin 12 and C6

next to the 5V, pin 2.

6) Place the IC such that the pwm output drives, pins 9

and 11 are relatively short distance from gates of Q1 and

Q2.

7) If the ouput voltage is to be adjusted, place resistor

dividers close to the feedback pin.

Note 1: Although, the device does not require resistor

dividers and the feedback pin can be directly connected

to the output, they can be used to set the outputs slightly

higher to account for any output drop at the load due to

the trace resistance. See the application note.

8) Place timing capacitor C9 close to pin1 and soft start

capacitor C2 close to pin 13

Component connections:

Note : It is extremely important that no data bus

should be passing through the switching regulator

section specifically close to the fast transition nodes

such as PWM drives or the inductor voltage.

Using 4 layer board, dedicate on layer to GND, another

layer as the power layer for the 5V, 3.3V and Vcore.

Connect all grounds to the ground plane using di-

rect vias to the ground plane.

Use large low inductance/low impedance plane to con-

nect the following connections either using component

side or the solder side.

a) C3 to Q1 Drain

b) Q1 Source to Q2 Drain

c) Q2 drain to L2

d) L2 to the output capacitors, C10

e) C10 to the slot 1

f) Input filter L1 to the C3

Connect the rest of the components using the shortest

connection possible