fax id: 2049 3 PRELIMINARY CYM1831V33 64K x 32 3.3V Static RAM Module Features ule is constructed from two 64K x 16 SRAMs in SOJ packages mounted on an epoxy laminate substrate. Four chip selects are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. * High-density 3.3V 2-megabit SRAM module * High-speed SRAMs -- Access time of 12 ns * Low active power -- 1.386W (max.) at 12 ns * 64 pins * Available in ZIP format The CYM1831V33 is designed for use with standard 64-pin ZIP sockets. The pinout is compatible with the 64-pin JEDEC ZIP module family (CYM1821, CYM1831, CYM1836, and CYM1841). Thus, a single motherboard design can be used to accommodate memory depth ranging from 16K words (CYM1821) to 256K words (CYM1841). The CYM1831V33 is offered in a vertical ZIP configuration. Functional Description Presence detect pins (PD0-PD1) are used to identify module memory density in applications where modules with alternate word depths can be interchanged. The CYM1831V33 is a high-performance 3.3V 2-megabit static RAM module organized as 64K words by 32 bits. This mod- Logic Block Diagram A0 - A15 OE Pin Configuration 16 64-pin ZIP Top View PD0 - OPEN PD1 - GND WE A[0:15] OE WE CS1 CS2 64K x 16 16 I/O0 - I/O15 BLE PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 CS3 NC GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 BHE A[0:15] OE WE CS3 BLE CS4 BHE 64K x 16 16 I/O16 - I/O31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 CS4 NC OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 Selection Guide 1831V33-12 1831V33-15 1831V33-20 1831V33-25 1831V33-35 Maximum Access Time (ns) 12 15 20 25 35 Maximum Operating Current (mA) 420 400 380 380 380 Maximum Standby Current (mA) 60 60 60 60 60 Shaded area contains advance information. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 July 1, 1998 PRELIMINARY Maximum Ratings CYM1831V33 DC Voltage Applied to Outputs in High Z State.................................................-0.5V to +VCC (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -55C to +125C DC Input Voltage ............................................-0.5V to +4.6V Operating Range Ambient Temperature with Power Applied ............................................... -10C to +85C Range Ambient Temperature Supply Voltage to Ground Potential ............... -0.5V to +4.6V Commercial 0C to +70C VCC 3.3V (+10%/-5%) Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current IOZ Output Leakage Current ICC VCC Operating Supply Current Min. Max. Unit 2.4 GND < VI < VCC GND < VO < VCC, Output Disabled V 0.4 V 2.0 VCC + 0.3 V -0.3 0.8 V -10 +10 A -10 +10 A 420 mA VCC = Max., IOUT = 0 mA, -12 CSN < VIL -15 400 -20, -25, -35 380 ISB1 Automatic CS Power-Down Current[1] Max. VCC, CS > VIH, Min. Duty Cycle = 100% -12,-15,-20,-25, -35 90 mA ISB2 Automatic CS Power-Down Current[1] Max. VCC, CS > VCC - 0.2V, VIN > VCC - 0.2V, or VIN < 0.2V -12, -15, -20, -25, -35 60 mA Shaded area contains advance information. Capacitance[2] Parameter Description CINA Input Capacitance (WE, OE, A0-19) CINB Input Capacitance (CS) COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 12 pF 6 pF 8 pF Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. 2 PRELIMINARY CYM1831V33 AC Test Loads and Waveforms R317 3.3V R317 ALL INPUT PULSES 3.0V 3.3V OUTPUT R2 351 30 pF INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE THEVENIN OUTPUT R2 351 5 pF (a) Equivalent to: 90% OUTPUT 90% 10% GND 10% < 5 ns < 5 ns 1831V33-3 (b) 1831V33-4 EQUIVALENT 167 1.73V Switching Characteristics Over the Operating Range[3] 1831V33-12 Parameter Description Min. Max. 1831V33-15 Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 15 tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid 12 15 ns tDOE OE LOW to Data Valid 7 8 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z 12 3 15 3 0 ns 8 CS LOW to Low Z tHZCS CS HIGH to High Z[4, 5] 7 8 ns CS HIGH to Power-Down 12 15 ns WRITE CYCLE 3 ns tLZCS tPD 3 ns ns 0 7 [4] ns ns [6] tWC Write Cycle Time 12 15 ns tSCS CS LOW to Write End 9 10 ns tAW Address Set-Up to Write End 9 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 1 1 ns tPWE WE Pulse Width 10 12 ns tSD Data Set-Up to Write End 7 8 ns tHD Data Hold from Write End 1 1 ns tLZWE WE HIGH to Low Z 3 tHZWE WE LOW to High Z[5] 0 Shaded area contains advance information. 3 3 7 0 ns 8 ns PRELIMINARY CYM1831V33 Switching Characteristics Over the Operating Range[3](continued) 1831V33-20 Parameter Description Min. Max. 1831V33-25 Min. Max. 1831V33-35 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid 20 25 35 ns tDOE OE LOW to Data Valid 12 15 18 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCS CS LOW to Low Z 20 25 20 3 25 3 0 3 [4, 5] ns 35 3 0 10 [4] 35 ns 0 12 3 ns ns 15 3 ns ns tHZCS CS HIGH to High Z 10 12 15 ns tPD CS HIGH to Power-Down 20 25 35 ns WRITE CYCLE[6] tWC Write Cycle Time 20 25 35 ns tSCS CS LOW to Write End 17 20 30 ns tAW Address Set-Up to Write End 17 20 30 ns tHA Address Hold from Write End 3 3 3 ns tSA Address Set-Up to Write Start 2 2 2 ns tPWE WE Pulse Width 15 20 30 ns tSD Data Set-Up to Write End 12 15 20 ns tHD Data Hold from Write End 2 2 2 ns tLZWE WE HIGH to Low Z 3 3 3 ns tHZWE WE LOW to High Z [5] 0 12 0 12 0 15 ns Switching Waveforms Read Cycle No. 1 [7,8] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1831V33-5 Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested. 5. tHZCS and tHZWE are specified with C L = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL, and OE= VIL. 4 PRELIMINARY CYM1831V33 Switching Waveforms (continued) Read Cycle No. 2 [7,9] t RC CS tACS OE tHZOE tDOE tHZCS tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT tLZCS tPD tPU ICC V CC SUPPLY CURRENT 50% 50% ISB 1831V33-6 Write Cycle No. 1 (WE Controlled) [6] tWC ADDRESS tSCS CS tAW tHA tSA tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED 1831V33-7 Note: 9. Address valid prior to or coincident with CS transition LOW. 5 PRELIMINARY CYM1831V33 Switching Waveforms (continued) Write Cycle No. 2 (CS Controlled) [6,10] tWC ADDRESS tSA tSCS CS tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED 1831V33-8 Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table CS WE OE Inputs/Output Mode H X X High Z Deselect/Power-Down L H L Data Out Read L L X Data In Write L H H High Z Deselect Ordering Information Speed (ns) Ordering Code 12 CYM1831V33PZ-12C 15 CYM1831V33PZ-15C 20 CYM1831V33PZ-20C 25 CYM1831V33PZ-25C 35 CYM1831V33PZ-35C Package Type Package Type Operating Range PZ12 64 Pin Plastic ZIP Module Commercial Shaded area contains advance information. Document #: 38-M-00087 6 PRELIMINARY CYM1831V33 Package Diagram 64-Pin Plastic ZIP Module PZ12 (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.