PRELIMINARY
64K x 32 3.3V Static RAM Module
f
ax id: 2049
CYM1831V33
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Jul
y
1
,
1998
3
Features
• High-density 3.3V 2-megabit SRAM module
• High-speed SRAMs
—Acc ess time of 12 ns
• Lo w active power
—1.386W (max.) at 12 ns
• 64 pins
• Available in ZIP format
Functional Description
The CYM1831V33 is a high- perfo rmance 3.3V 2-megabit sta t-
ic RAM module organized as 64K words by 32 bi ts. Th is mod-
ule i s cons tructed f rom tw o 6 4K x 16 SRAMs in SOJ packa ges
mounted on an epoxy laminate substrate. Four chip selects
are used to independently enable the four bytes. Reading or
writing ca n be e xecute d on indivi dual by tes or an y combina tion
of multiple b ytes through proper use of selects.
The CYM1831V33 is designed for use with standard 64-pin
ZIP sockets. The pinout is compatible with the 64-pin JEDEC
ZIP module family (CYM1821, CYM1831, CYM1836, and
CYM1841). Thu s, a singl e mothe rboard design can be use d to
accommodate memory depth ranging from 16K words
(CYM1821) to 256K words (CYM1841). The CYM1831V33 is
offered in a verti cal ZIP configuration.
Presence detect pins (PD0−PD1) are used to identify module
memory density in applications where modules with al ternat e
word depths can be interchanged.
LogicBlock Diagram Pin Configuration
A0−A15
OE
I/O0−I/O15
CS3
CS1
16
16
CS2
CS4
PD0- OPEN
PD1-GND
WE
64K x 1 6
BHE
BLE
A[0:15]
OE
WE
I/O16−I/O31
16
64K x 16
BHE
BLE
A[0:15]
OE
WE
64-pin ZI P
Top View
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
PD0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
CS2
CS4
NC
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
WE
A14
CS1
CS3
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
NC
Selec tion Guide
1831V33-12 1831V33-15 1831V33-20 1831V33-25 1831V33-35
Maximum Access Time (ns) 12 15 20 25 35
Maxim um Ope rating Current (mA) 420 400 380 380 380
Maximum Standby Current (mA) 60 60 60 60 60
Shaded area contains advance information.
CYM1831V33
PRELIMINARY
2
Maximum Ratings
(Above which the useful l ife may be impaired. For user gui de-
li nes, not tes ted.)
Sto ra g e Tem p e ra tu r e ......... ..... .... ........ ..... ..– 5 5°C to +125°C
Ambient Temperature with
Power Applied...............................................–10°C to +85°C
Supply Voltage t o Ground Potential .............. .–0.5V to +4.6V
DC Voltage Applied to Out puts
in High Z State.................................................–0.5V to +VCC
DC Input Voltage ............................................ –0.5V to +4.6V
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 3.3V
(+10%/–5%)
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Vol tage VCC = Min., IOH = −4.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 4 .0 mA 0.4 V
VIH Input HI GH Voltag e 2.0 VCC + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –10 +10 µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –10 +10 µA
ICC VCC Operating Suppl y
Current VCC = Max., IOUT = 0 mA,
CSN < VIL -12 420 mA
-15 400
-20, -25, -35 380
ISB1 Automatic CS Power-Down
Current[1] Max. VCC, CS > VIH,
Min. Duty Cycle = 100% -12,-15,-20,-25,
-35 90 mA
ISB2 Automatic CS Power-Down
Current[1] Max. VCC,
CS > VCC − 0.2V,
VIN > VCC − 0.2 V, or
VIN < 0.2V
-12, -15, -20, -25,
-35 60 mA
Shaded area contains advance information.
Capacitance[2]
Parameter Description Test Conditions Max. Unit
CINA Input Capacitance (WE, O E , A0-19) TA = 25°C, f = 1 MHz,
VCC = 5.0V 12 pF
CINB Input Capacitance (CS) 6 pF
COUT Output Capa citance 8pF
Notes:
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
2. Tested on a sample basis.
CYM1831V33
PRELIMINARY
3
AC Test Loads and Wave forms
1831V33–3
1831V33–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<5ns <5n
s
OUTPUT
R317 ΩR317 Ω
R2
351ΩR2
351Ω
167Ω
Equivalent to: THÉ VENIN EQUIVALENT
1.73V
Swi tch i ng C h ara cter i sti cs Over the Operating Range[3]
1831V33-12 1831V33-15
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Ti m e 12 15 ns
tAA Address to Data Valid 12 15 ns
tOHA Data Hold from Address Change 3 3 ns
tACS CS LOW to Data Valid 12 15 ns
tDOE OE LOW to Data Valid 7 8 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z 7 8 ns
tLZCS CS LOW t o Low Z[4] 3 3 ns
tHZCS CS HIGH to High Z[4 , 5 ] 7 8 ns
tPD CS HIGH to Power-Down 12 15 ns
WRITE CY CLE [6]
tWC Write Cycl e Time 12 15 ns
tSCS CS LOW to Write End 910 ns
tAW Address Set-Up to Write End 910 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 1 1 ns
tPWE WE Pulse W idth 10 12 ns
tSD Data Set-Up to Write End 7 8 ns
tHD Data Hold from Write End 1 1 ns
tLZWE WE HIGH to Low Z 3 3 ns
tHZWE WE LOW to High Z[5] 0 7 0 8 ns
Shaded area contains advance information.
CYM1831V33
PRELIMINARY
4
Swi tch i ng C h ara cter i sti cs Over the Operating Range[3](continued)
1831V33-20 1831V33-25 1831V33-35
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Ti m e 20 25 35 ns
tAA Address to Data Valid 20 25 35 ns
tOHA Data Hold from Address Change 333ns
tACS CS LOW to Data Valid 20 25 35 ns
tDOE OE LOW to Data Valid 12 15 18 ns
tLZOE OE LOW to Low Z 000ns
tHZOE OE HIGH to High Z 10 12 15 ns
tLZCS CS LOW to Low Z[4] 333ns
tHZCS CS HIGH to High Z[4, 5] 10 12 15 ns
tPD CS HIGH to Power-Down 20 25 35 ns
WRITE CY CLE [6]
tWC Write Cycl e Time 20 25 35 ns
tSCS CS LOW to Write End 17 20 30 ns
tAW Address Set-Up to Write End 17 20 30 ns
tHA Address Hold from Write End 333ns
tSA Address Set-Up to Write Start 222ns
tPWE WE Pulse W idth 15 20 30 ns
tSD Da ta S et -U p to Write E nd 12 15 20 ns
tHD Data Hold from Write End 222ns
tLZWE WE HIGH to Low Z 333ns
tHZWE WE LOW to High Z[5] 012 012 015 ns
Swi tch i ng Waveform s
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing reference le vels of 1.5V , input pulse lev els of 0 to 3.0V , and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
7. WE is HIGH for re ad cycle.
8. Device is continuously selected, CS = VIL, and OE= VIL.
Read Cycle No. 1
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
1831V33–
5
ADDRESS
DATA OUT
[7,8]
CYM1831V33
PRELIMINARY
5
Note:
9. Address valid prior to or coincident with CS transition LOW.
Swi tch i ng Waveform s (continued)
Read Cycle No. 2
DATA VALID
tRC
tACS
tDOE
tLZOE
tLZCS
HIGH IMPEDANCE
tHZOE
tHZCS HIGH
IMPEDANCE
1831V33–6
DATA OUT
OE
CS
VCC
SUPPLY
CURRENT
50%
50%
tPU ICC
ISB
tPD
[7,9]
WriteCycleNo.1(WEControlled)
tWC
DATA VALID
DATA UNDEFINED HIGH IMPEDANCE
tSCS
tAW
tSA tPWE
tHA
tHD
tHZWE tLZWE
tSD
CS
WE
1831V33–7
ADDRESS
DATA IN
DATA OUT
[6]
CYM1831V33
PRELIMINARY
6
Document #: 38-M-00087
Note:
10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Swi tch i ng Waveform s (continued)
Write Cycle No. 2 (CS Controlled)
tWC
DATA VALID
DATA UNDEFINED HIGH IMPEDANCE
tSCS
tAW tPWE
tHA
tHD
tHZWE
tSD
CS
WE
1831V33–8
ADDRESS
DATA IN
DATA OUT
tSA
[6,10]
Truth Table
CS WE OE Inputs/Output Mode
H X X High Z Deselect/Power-Down
L H L Data Out Read
L L X Data In Write
L H H High Z Deselect
Ordering Information
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
12 CYM1831V33PZ-12C PZ12 64 Pin Plastic ZI P Module Commer cial
15 CYM1831V33PZ-15C
20 CYM1831V33PZ-20C
25 CYM1831V33PZ-25C
35 CYM1831V33PZ-35C
Shaded area contains advance information.
CYM1831V33
PRELIMINARY
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not author ize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application i m plies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Di ag ra m
64-Pin Plastic ZIP Module PZ12
