CY7C1326F-100AXC - Cypress Semiconductor Corp.

2-Mb (128K x 18) Pipelined Sync SRAM

CY7C1326F

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05424 Rev. ** Revised January 25, 2004

Features

• Registered inputs and outputs for pipelined operation

• 128K × 18 common I/O architecture

• 3.3V core power supply

• 3.3V I/O operation

• Fast clock-to-output times

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium® interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP package

• “ZZ” Sleep Mode Option

Functional Description[1]

The CY7C1326F SRAM integrates 131,072 x18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst

Control inputs (ADSC, ADSP

, and ADV), Write Enables

(BW[A:B] and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

controlled by the Byte Write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1326F operates from a +3.3V core power supply

while all outputs also operate with a +3.3V supply. All inputs

and outputs are JEDEC-standard JESD8-5-compatible.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Logic Block Diagram

0, A1, A ADDRESS

ADV

CLK BURST

COUNTER

AND

LOGIC

CLR

ADSC

BWB

BWA

CE1

DQB,DQPB

WRITE REGISTER

DQA,DQPA

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

MODE

CE2

CE3

BWE

PIPELINED

ENABLE

DQs

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

DQA,DQPA

WRITE DRIVER

OUTPUT

BUFFERS

DQB,DQPB

WRITE DRIVER

A[1:0]

CY7C1326F

Document #: 38-05424 Rev. ** Page 2 of 15

Pin Configuration

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 4.0 4.5 ns

Maximum Operating Current 225 205 mA

Maximum CMOS Standby Current 40 40 mA

VSS

VDD

VDDQ

VSS

DQPA

DQA

VSS

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VDD

VSS

DQB

VDDQ

VSS

DQB

DQPB

VSS

VDDQ

CE1

CE2

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

BYTE A

BYTE B 100-pin TQFP

CY7C1326F

Document #: 38-05424 Rev. ** Page 3 of 15

Pin Definitions

Name TQFP I/O Description

A0, A1, A 37,36,

32,33,34,

35,44,45,

46,47,48,

49,80,81,

82,99,

100

Input-

Synchronous

Address Inputs used to select one of the 128K address locations. Sampled at

the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3

are sampled active. A[1:0] feed the 2-bit counter.

BWA, BWB93,94 Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes

to the SRAM. Sampled on the rising edge of CLK.

GW 88 Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of

CLK, a global Write is conducted (ALL bytes are written, regardless of the values on

BW[A:B] and BWE).

BWE 87 Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

signal must be asserted LOW to conduct a Byte Write.

CLK 89 Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

CE1

98 Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1

is HIGH.

CE297 Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE1 and CE3 to select/deselect the device.

CE392 Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE1 and CE2 to select/deselect the device. Not connected for BGA.

Where referenced, CE3 is assumed active throughout this document for BGA.

OE 86 Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O

pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins

are three-stated, and act as input data pins. OE is masked during the first clock of a

Read cycle when emerging from a deselected state.

ADV 83 Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK, active LOW. When

asserted, it automatically increments the address in a burst cycle.

ADSP 84 Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active

LOW. When asserted LOW, A is captured in the address registers. A[1:0] are also

loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP

is recognized. ASDP is ignored when CE1 is deasserted HIGH.

ADSC 85 Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.

When asserted LOW, A is captured in the address registers. A[1:0] are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is rec-

ognized.

ZZ 64 Input-

Asynchronous

ZZ “Sleep” Input, active HIGH. This input, when HIGH places the device in a

non-time-critical “sleep” condition with data integrity preserved. For normal operation,

this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

DQA,

DQB

DQPA,

DQPB

58,59,62,

63,68,69,

72,73

8,9,12,13,

18,19,22,

74,24

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by “A” during the previous clock rise of the Read cycle. The

direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave

as outputs. When HIGH, DQs and DQP[A:B] are placed in a three-state condition.

VDD 15,41,65,

Power Supply Power supply inputs to the core of the device.

CY7C1326F

Document #: 38-05424 Rev. ** Page 4 of 15

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

The CY7C1326F supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All Writes are simplified with on-chip

synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

CE1, CE2, CE3 are all asserted active, and (3) the Write

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if

CE1 is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the Address

corresponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within tCO if OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state

to a selected state, its outputs are always three-stated during

the first cycle of the access. After the first cycle of the access,

the outputs are controlled by the OE signal. Consecutive

single Read cycles are supported. Once the SRAM is

deselected at clock rise by the chip select and either ADSP or

ADSC signals, its output will three-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE1, CE2, CE3 are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array. The Write signals (GW, BWE, and BW[A:B]) and

ADV inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BW[A:B]

signals. The CY7C1326F provides Byte Write capability that is

described in the Write Cycle Descriptions table. Asserting the

Byte Write Enable input (BWE) with the selected Byte Write

(BW[A:B]) input, will selectively write to only the desired bytes.

Bytes not selected during a Byte Write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations.

Because the CY7C1326F is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQ inputs. Doing so will three-state the output drivers.

As a safety precaution, DQs are automatically three-stated

whenever a Write cycle is detected, regardless of the state of

OE.

VSS 5,10,17,

21,26,40,

55,60,67,

71,76,90

Ground Ground for the device.

VDDQ 4,11,20,

27,54,61,

70,77

I/O Ground Ground for the I/O circuitry.

MODE 31 Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to

VDD or left floating selects interleaved burst sequence. This is a strap pin and should

remain static during device operation. Mode pin has an internal pull-up.

NC 1,2,3,6,7,

14,16,25,

28,29,30,

38,39,42,

43,50,51,

52,53,56,

57,66,75,

78,79,95,

No Connects. Not internally connected to the die.

Pin Definitions (continued)

Name TQFP I/O Description

CY7C1326F

Document #: 38-05424 Rev. ** Page 5 of 15

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,

and (4) the appropriate combination of the Write inputs (GW,

BWE, and BW[A:B]) are asserted active to conduct a Write to

the desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded into the address register and the address

advancement logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to DQ is written into the corre-

sponding address location in the memory core. If a Byte Write

is conducted, only the selected bytes are written. Bytes not

selected during a Byte Write operation will remain unaltered.

A synchronous self-timed Write mechanism has been

provided to simplify the Write operations.

Because the CY7C1326F is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will three-state the output drivers.

As a safety precaution, DQs are automatically three-stated

whenever a Write cycle is detected, regardless of the state of

OE.

Burst Sequences

The CY7C1326F provides a two-bit wraparound counter, fed

by A[1:0], that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must

remain inactive for the duration of tZZREC after the ZZ input

returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A[1:0]

Second

Address

A[1:0]

Third

Address

A[1:0]

Fourth

Address

A[1:0]

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A[1:0]

Second

Address

A[1:0]

Third

Address

A[1:0]

Fourth

Address

A[1:0]

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Snooze mode standby current ZZ > VDD – 0.2V 40 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ Active to snooze current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit snooze current This parameter is sampled 0 ns

CY7C1326F

Document #: 38-05424 Rev. ** Page 6 of 15

Truth Table[2, 3, 4, 5, 6, 7]

Next Cycle Add. Used ZZ CE3CE2CE1ADSP ADSC ADV OE DQ Write

Unselected None L X X H X L X X Three-State X

Unselected None L H X L L X X X Three-State X

Unselected None L X L L L X X X Three-State X

Unselected None L H X L H L X X Three-State X

Unselected None L X L L H L X X Three-State X

Begin Read External L L H L L X X X Three-State X

Begin Read External L L H L H L X X Three-State Read

Continue Read Next L X X X H H L H Three-State Read

Continue Read Next L X X X H H L L DQ Read

Continue Read Next L X X H X H L H Three-State Read

Continue Read Next L X X H X H L L DQ Read

Suspend Read Current L X X X H H H H Three-State Read

Suspend Read Current L X X X H H H L DQ Read

Suspend Read Current L X X H X H H H Three-State Read

Suspend Read Current L X X H X H H L DQ Read

Begin Write Current L X X X H H H X Three-State Write

Begin Write Current L X X H X H H X Three-State Write

Begin Write External L L H L H H X X Three-State Write

Continue Write Next L X X X H H H X Three-State Write

Continue Write Next L X X H X H H X Three-State Write

Suspend Write Current L X X X H H H X Three-State Write

Suspend Write Current L X X H X H H X Three-State Write

ZZ “Sleep” None H X X X X X X X Three-State X

Truth Table for Read/Write[2, 3]

Function GW BWE BWBBWA

Read H H X X

Read H L H H

Write Byte A – (DQA and DQPA) H L H L

Write Byte B – (DQB and DQPB)HLLH

Write Bytes B, A H L L L

Write All Bytes H L L L

Write All Bytes L X X X

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE =L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals

(

BWA,BWB),BWE, GW = H.

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Three-State. OE

is a don't care for the remainder of the Write cycle

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when

OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

CY7C1326F

Document #: 38-05424 Rev. ** Page 7 of 15

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V

DC Voltage Applied to Outputs

in Three-State ..................................... –0.5V to VDDQ + 0.5V

DC Input Voltage....................................–0.5V to VDD + 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Ambient

Temperature VDD VDDQ

Commercial 0°C to +70°C 3.3V

–5%/+10%

3.3V –5%

to VDD

Electrical Characteristics Over the Operating Range[8, 9]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage 3.135 VDD V

VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V

VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V

VIH Input HIGH Voltage[8] VDDQ = 3.3V 2.0 VDD + 0.3V V

VIL Input LOW Voltage[8] VDDQ = 3.3V –0.3 0.8 V

IXInput Load Current

except ZZ and MODE

GND ≤ VI ≤ VDDQ –5 5µA

Input Current of MODE Input = VSS –30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS –5 µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5µA

IDD VDD Operating Supply

Current

VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC

7.5-ns cycle, 133 MHz 225 mA

10-ns cycle, 100 MHz 205 mA

ISB1 Automatic CS

Power-down

Current—TTL Inputs

VDD = Max, Device

Deselected, VIN ≥ VIH or

VIN ≤ VIL, f = fMAX = 1/tCYC

7.5-ns cycle, 133 MHz 90 mA

10-ns cycle, 100 MHz 80 mA

ISB2 Automatic CS

Power-down

Current—CMOS Inputs

VDD = Max, Device

Deselected, VIN ≤ 0.3V or

VIN > VDDQ – 0.3V, f = 0

All speeds 40 mA

ISB3 Automatic CS

Power-down

Current—CMOS Inputs

VDD = Max, Device

Deselected, or VIN ≤ 0.3V

or VIN > VDDQ – 0.3V

f = fMAX = 1/tCYC

7.5-ns cycle, 133 MHz 75 mA

10-ns cycle, 100 MHz 65 mA

ISB4 Automatic CS

Power-down

Current—TTL Inputs

VDD = Max, Device

Deselected, VIN ≥ VIH or

VIN ≤ VIL, f = 0

All speeds 45 mA

Notes:

8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

CY7C1326F

Document #: 38-05424 Rev. ** Page 8 of 15

Thermal Resistance[10]

Parameter Description Test Conditions

TQFP

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods

and procedures for measuring thermal imped-

ance, per EIA/JESD51

41.83 °C/W

ΘJC Thermal Resistance

(Junction to Case)

9.99 °C/W

Capacitance[10]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 3.3V

5pF

CCLK Clock Input Capacitance 5pF

CI/O Input/Output Capacitance 5pF

AC Test Loads and Waveforms

Note:

10. Tested initially and after any design or process change that may affect these parameters.

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDD

GND

90%

10%

90%

10%

≤1 ns ≤1 ns

(c)

3.3V I/O Test Load

CY7C1326F

Document #: 38-05424 Rev. ** Page 9 of 15

Switching Characteristics Over the Operating Range[11, 12]

Parameter Description

133 MHz 100 MHz

UnitMin. Max Min. Max

tPOWER VDD(Typical) to the First Access[13] 111ms

Clock

tCYC Clock Cycle Time 7.5 10 ns

tCH Clock HIGH 3.0 3.5 ns

tCL Clock LOW 3.0 3.5 ns

Output Times

tCO Data Output Valid after CLK Rise 4.0 4.5 ns

tDOH Data Output Hold after CLK Rise 2.0 2.0 ns

tCLZ Clock to Low-Z[14, 15, 16] 0 0 ns

tCHZ Clock to High-Z[14, 15, 16] 4.0 4.5 ns

tOEV OE LOW to Output Valid 4.5 4.5 ns

tOELZ OE LOW to Output Low-Z[14, 15, 16] 0 0 ns

tOEHZ OE HIGH to Output High-Z[14, 15, 16] 4.0 4.5 ns

Set-up Times

tAS Address Set-up before CLK Rise 1.5 1.5 ns

tADS ADSC, ADSP Set-up before CLK Rise 1.5 1.5 ns

tADVS ADV Set-up before CLK Rise 1.5 1.5 ns

tWES GW, BWE, BW[A:B] Set-up before CLK Rise 1.5 1.5 ns

tDS Data Input Set-up before CLK Rise 1.5 1.5 ns

tCES Chip Enable Set-Up before CLK Rise 1.5 1.5 ns

Hold Times

tAH Address Hold after CLK Rise 0.5 0.5 ns

tADH ADSP , ADSC Hold after CLK Rise 0.5 0.5 ns

tADVH ADV Hold after CLK Rise 0.5 0.5 ns

tWEH GW,BWE, BW[A:B] Hold after CLK Rise 0.5 0.5 ns

tDH Data Input Hold after CLK Rise 0.5 0.5 ns

tCEH Chip Enable Hold after CLK Rise 0.5 0.5 ns

Notes:

11. Timing reference level is 1.5V when VDDQ = 3.3V.

12. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation

can be initiated.

14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

16. This parameter is sampled and not 100% tested.

CY7C1326F

Document #: 38-05424 Rev. ** Page 10 of 15

Switching Waveforms

Read Cycle Timing[17]

Note:

17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,

[A:B]

ata Out (Q) High-Z

tCLZ tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

ADV

suspends

burst.

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1)Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

DON’T CARE UNDEFINED

CY7C1326F

Document #: 38-05424 Rev. ** Page 11 of 15

Write Cycle Timing[17, 18]

Note:

18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A : B] LOW.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

BW[A :B]

ata Out (Q)

High-Z

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are

ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

CY7C1326F

Document #: 38-05424 Rev. ** Page 12 of 15

Read/Write Cycle Timing[17, 19, 20]

Notes:

19. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP, ADSC, or ADV cycle is performed.

20. GW is HIGH.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

[A:B]

ata Out (Q)

High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

CY7C1326F

Document #: 38-05424 Rev. ** Page 13 of 15

ZZ Mode Timing[21, 22]

Notes:

21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22. I/Os are in High-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

tZZ

ISUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q) High-Z

DESELECT or READ Only

Ordering Information

Speed

(MHz) Ordering Code

Package

Name Package Type

Operating

Range

100 CY7C1326F-100AC A101 100-Lead Thin Quad Flat Pack Commercial

Please contact your local Cypress sales representative for availability of the 133-MHz speed grade option.

CY7C1326F

Document #: 38-05424 Rev. ** Page 14 of 15

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark

of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.

Package Diagrams

100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

CY7C1326F

Document #: 38-05424 Rev. ** Page 15 of 15

Document History Page

Document Title: CY7C1326F 2-Mb (128K x 18) Pipelined Sync SRAM

Document Number: 38-05424

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 200661 See ECN NJY New Data Sheet