Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
1.8 (VCC = 1.8V to 5.5V)
20MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5ms Max)
High-reliability
Endurance: 1 Million Write Cycles
Data Retention: >100 Years
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
Die Sales: Wafer Form, Waffle Pack, and Bumped Die
Description
The Atmel®AT25128B/256B provides 131,072/262,144-bits of serial electrically eras-
able programmable read only memory (EEPROM) organized as 16,384/32,768 words
of 8-bits each. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices
are available in space saving 8-lead SOIC, 8-lead TSSOP, 8-ball VFBGA and 8-lead
UDFN packages. In addition, the entire family is available in 1.8V (1.8V to 5.5V).
The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
Block Write protection is enabled by programming the status register with top ¼, top ½
or entire array of write protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware data protection is
provided via the WP pin to protect against inadvertent write attempts to the status reg-
ister. The HOLD pin may be used to suspend any serial communication without
resetting the serial sequence.
Table 0-1. Pin Configurations
Pin Function
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial Input
VCC
HOLD
SCK
SI
CS
SO
WP
GND
4
3
2
1
5
6
7
8
8-lead UDFN
Bottom View
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-ball VFBGA
Bottom View
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-lead SOIC
VCC
HOLD
SCK
SI
8-lead TSSOP
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
SPI Serial
Electrically
Erasable and
Programmable
Read-only Memory
128K (16,384 x 8)
256K (32,768 x 8)
Atmel AT25128B
Atmel AT25256B
8698C–SEEPR–8/11
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8698C–SEEPR–8/11
Atmel AT25128B/256B
1. Absolute Maximum Ratings*
Figure 1-1. Block Diagram
Operating Temperature ........................–55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification are not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.
Storage Temperature .........................–65°C to + 150°C
Voltage on Any Pin
with Respect to Ground............................... –1.0V +7.0V
Maximum Operating Voltage................................. 6.25V
DC Output Current .............................................. 5.0 mA
16384/32768 x 8
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8698C–SEEPR–8/11
Atmel AT25128B/256B
Table 1-1. Pin Capacitance (1
Notes: 1. This parameter is characterized and is not 100% tested
Table 1-2. DC Characteristics
Notes: 1. VIL min and VIH max are reference only and are not tested
Applicable over recommended operating range from TA= 25°C, f = 1.0MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT =0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN =0V
Applicable over recommended operating range from TA= −40°C to +85°C, VCC = +1.8V to +5.5V,
VCC = +1.8V to +5.5V(unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V at 20MHz, SO = Open, Read 9.0 10.0 mA
ICC2 Supply Current VCC = 5.0V at 10MHz, SO = Open, Read, Write 5.0 7.0 mA
ICC3 Supply Current VCC = 5.0V at 1MHz, SO = Open, Read, Write 2.2 3.5 mA
ISB1 Standby Current VCC = 1.8V, CS = VCC 0.2 3.0 µA
ISB2 Standby Current VCC = 2.5V, CS = VCC 0.5 3.0 µA
ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 µA
IIL Input Current VIN =0VtoV
CC –3.0 3.0 µA
IOL Output Leakage VIN =0VtoV
CC,T
AC = 0°C to 70°C –3.0 3.0 µA
VIL(1) Input Low-voltage –1.0 VCC x 0.3 V
VIH(1) Input High-voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low-voltage 3.6V VCC 5.5V IOL = 3.0mA 0.4 V
VOH1 Output High-voltage IOH =1.6mA VCC - 0.8 V
VOL2 Output Low-voltage 1.8V VCC 3.6V IOL = 0.15mA 0.2 V
VOH2 Output High-voltage IOH =100µA VCC - 0.2 V
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8698C–SEEPR–8/11
Atmel AT25128B/256B
Table 1-3. AC Characteristics
Applicable over recommended operating range from TA=40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
fSCK SCK Clock Frequency
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
20
10
5
MHz
tRI Input Rise Time
4.5–5.5
2.5–5.5
1.8–5.5
2
2
2
µs
tFI Input Fall Time
4.5–5.5
2.5–5.5
1.8–5.5
2
2
2
µs
tWH SCK High Time
4.5–5.5
2.5–5.5
1.8–5.5
20
40
80
ns
tWL SCK Low Time
4.5–5.5
2.5–5.5
1.8–5.5
20
40
80
ns
tCS CS High Time
4.5–5.5
2.5–5.5
1.8–5.5
100
100
200
ns
tCSS CS Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
100
100
200
ns
tCSH CS Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
100
100
200
ns
tSU Data In Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tHData In Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tHD HOLD Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tCD HOLD Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tVOutput Valid
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
20
40
80
ns
tHO Output Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
ns
5
8698C–SEEPR–8/11
Atmel AT25128B/256B
Notes: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information
2. Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the Atmel®AT25128B/256B always operates as a
slave.
TRANSMITTER/RECEIVER: The AT25128B/256B has separate pins designated for data transmission (SO) and
reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL-OP CODE: After the device is selected with CS going low, the first byte will be received. This byte con-
tains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128B/256B, and the
serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will
reinitialize the serial communication.
CHIP SELECT: The AT25128B/256B is selected when the CS pin is low. When the device is not selected, data will
not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the device is
selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the mas-
ter device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is
low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle
during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
tLZ HOLD to Output Low Z
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
25
50
100
ns
tHZ HOLD to Output High Z
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
ns
tDIS Output Disable Time
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
ns
tWC Write Cycle Time
4.5–5.5
2.5–5.5
1.8–5.5
5
5
5
ms
Endurance(1) 3.3V, 25°C, Page Mode 1M Write Cycles
Table 1-3. AC Characteristics (Continued)
Applicable over recommended operating range from TA=40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
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8698C–SEEPR–8/11
Atmel AT25128B/256B
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when
the WPEN bit in the status register is “0”. This will allow the user to install the Atmel®AT25128B/256B in a system
with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled
when the WPEN bit is set to “1”.
Figure 2-1. SPI Serial Interface
AT25128B/256B
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8698C–SEEPR–8/11
Atmel AT25128B/256B
3. Functional Description
The Atmel®AT25128B/256B is designed to interface directly with the synchronous serial peripheral interface (SPI)
of the 6800 type series of microcontrollers.
The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are con-
tained in Table 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-
low CS transition.
Table 3-1. Instruction Set for Atmel AT25128B/256B
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 3-2. Status Register Format
Table 3-3. Read Status Register Bit Definition
Instruction Name Instruction Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Register
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X 010 Write Data to Memory Array
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Bit Definition
Bit0(
RDY) Bit 0 = “0” (RDY) indicates the device is ready
Bit 0 = “1” indicates the write cycle is in progress
Bit 1 (WEN) Bit1=0indicates the device is not write enabled
Bit 1 = “1” indicates the device is write enabled
Bit 2 (BP0) See Table 3-4 on page 8
Bit 3 (BP1) See Table 3-4 on page 8
Bits4–6are0swhen device is not an internal write cycle
Bit 7 (WPEN) See Table 3-5 on page 8
Bits0–7are“1”s during an internal write cycle
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8698C–SEEPR–8/11
Atmel AT25128B/256B
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
The Atmel®AT25128B/256B is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the mem-
ory segments can be protected. Any of the data within any selected segment will therefore be read only. The block
write protection levels and corresponding status register control bits are shown in Table 3-4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the reg-
ular memory cells (e.g. WREN, tWC, RDSR)
Table 3-4. Block Write Protect Bits.
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the
write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is
“1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is
hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the
blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the memory which
are not block-protected.
Note: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low
Table 3-5. WPEN Operation
READ SEQUENCE (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After
the CS line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the byte
address to be read (Table 3-6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the
specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven
high after the data comes out. The read sequence can be continued since the byte address is automatically incre-
mented and data will continue to be shifted out. When the highest address is reached, the address counter will roll
over to the lowest address allowing the entire memory to be read in one continuous read cycle.
Level Status Register Bits Array Addresses Protected
BP1 BP0 Atmel AT25128B Atmel AT25256B
0 0 0 None None
1 (1/4) 0 1 3000 3FFF 6000 7FFF
2 (1/2) 1 0 2000 3FFF 4000 7FFF
3 (All) 1 1 0000 3FFF 0000 7FFF
WPEN WP WEN Protected Blocks
Unprotected
Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
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8698C–SEEPR–8/11
Atmel AT25128B/256B
WRITE SEQUENCE (WRITE): In order to program the Atmel®AT25128B/256B, two separate instructions must be
executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write instruc-
tion may be executed. Also, the address of the memory location(s) to be programmed must be outside the
protected address field location selected by the Block Write Protection Level. During an internal write cycle, all
commands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write
op-code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed (see
Table 3-6 for the address key). Programming will start after the CS pin is brought high. (The Low-to-High transition
of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If
Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register
instruction is enabled during the Write programming cycle.
The AT25128B/256B is capable of a 64-byte Page Write operation. After each byte of data is received, the six low
order address bits are internally incremented by one; the high order bits of the address will remain constant. If
more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25128B/256B is automatically returned to the write disable state at the completion of a Write
cycle.
Note: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby
state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication.
Table 3-6. Address Key
Address Atmel AT25128B Atmel AT25256B
ANA13 −A
0A14 −A
0
Don’t Care Bits A15 −A
14 A15
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8698C–SEEPR–8/11
Atmel AT25128B/256B
4. Timing Diagram (for SPI Mode 0 (0,0)
Figure 4-1. Synchronous Data Timing
Figure 4-2. WREN Timing
Figure 4-3. WRDI Timing
SO HI-Z HI-Z
tV
VALID IN
SI
tH
tSU
tDIS
SCK tWH
tCSH
CS
tCSS
tCS
tWL
tHO
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
SO
SI
SCK
CS
WREN OP-CODE
HI-Z
SO
SI
SCK
CS
WRDI OP-CODE
HI-Z
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8698C–SEEPR–8/11
Atmel AT25128B/256B
Figure 4-4. RDSR Timing
Figure 4-5. WRSR Timing
Figure 4-6. READ Timing
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
76543210
DATA OUT
HIGH IMPEDANCE
MSB
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
76543210
DATA IN
HIGH IMPEDANCE
SO
SI
SCK
CS
INSTRUCTION
BYTE ADDRESS
DATA OUT
HIGH IMPEDANCE
MSB
76543210
0 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 30
AN ... A0
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8698C–SEEPR–8/11
Atmel AT25128B/256B
Figure 4-7. WRITE Timing
Figure 4-8. HOLD Timing
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION
BYTE ADDRESS DATA IN
HIGH IMPEDANCE
7654321015 14 13 ... 3210
HOLD
SO
SCK
CS
tCD tCD
tHD
tHD
t
LZ
tHZ
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8698C–SEEPR–8/11
Atmel AT25128B/256B
5. Ordering Code Detail
Atmel Designator
Product Family
Device Density
Device Revision
Shipping Carrier Option
Operating Voltage
128 = 128k
256 = 256k
B or blank = Bulk (tubes)
T = Tape and Reel
L = 1.8V to 5.5V
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu lead finish,
Industrial Temperature range
(-40°C to +85°C)
U = Green, matte Sn lead finish,
Industrial Temperature range
(-40°C to +85°C)
11 = 11mil wafer thickness
Package Option
SS = JEDEC SOIC
X = TSSOP
MA = UDFN
C = VFBGA
WWU = Wafer unsawn
WDT = Die in Tape and Reel
AT25128B-SSHL-B
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8698C–SEEPR–8/11
Atmel AT25128B/256B
6. Part Markings
Atmel AT25128B-SSHL
Atmel AT25128B-XHL
Atmel AT25128B-MAHL
| Seal Week
| | |
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
5 D B L @
|---|---|---|---|---|---|---|---|
* LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
Top Mark Seal Year
@ = Country of Ass’y
Y = SEAL YEAR
6: 2006 0: 2010
7: 2007 1: 2011
8: 2008 2: 2012
9: 2009 3: 2013
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
52 = Week 52
PIN 1 INDICATOR (DOT)
|
* |---|---|---|---|---|---|
A T H Y W W
|---|---|---|---|---|---|
5 D B L @
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
Top Mark
@ = Country of Ass’y
Y = SEAL YEAR
8: 2008 2: 2012
9: 2009 3: 2013
0: 2010 4: 2014
1: 2011 5: 2015
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
52 = Week 52
|---|---|---|
5 D B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
Top Mark
Y = YEAR OF ASSEMBLY
@ = Country of Ass’y
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,... AX, AY, AZ)
Y = SEAL YEAR
6: 2006 0: 2010
7: 2007 1: 2011
8: 2008 2: 2012
9: 2009 3: 2013
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8698C–SEEPR–8/11
Atmel AT25128B/256B
Atmel AT25128B-CUL
Atmel AT25256B-SSHL
Atmel AT25256B-XHL
|---|---|---|---|
5 D B U
|---|---|---|---|
B Y M X X
|---|---|---|---|---|
* <-- PIN 1 INDICATOR
Top Mark
B = Country of Origin
Y = One Digit Year Code
M = One Digit Month Code
XX= TRACE CODE (ATMEL LOT NUMBER TO
COORESPOND WITH TRACE CODE LOG BOOK)
(e.g. XX = AA, AB, AC,... YZ, ZZ)
Y = ONE DIGIT YEAR CODE
4: 2004 7: 2007
5: 2005 8: 2008
6: 2006 9: 2009
M = SEAL MONTH
(USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """"""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
| Seal Week
| | |
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
5 E B L @
|---|---|---|---|---|---|---|---|
* LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
Top Mark Seal Year
@ = Country of Ass’y
Y = SEAL YEAR
6: 2006 0: 2010
7: 2007 1: 2011
8: 2008 2: 2012
9: 2009 3: 2013
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: :
50 = Week 50
52 = Week 52
PIN 1 INDICATOR (DOT)
|
* |---|---|---|---|---|---|
A T H Y W W
|---|---|---|---|---|---|
5 E B L @
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
Top Mark
@ = Country of Ass’y
Y = SEAL YEAR
8: 2008 2: 2012
9: 2009 3: 2013
0: 2010 4: 2014
1: 2011 5: 2015
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
52 = Week 52
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Atmel AT25128B/256B
Atmel AT25256B-MAHL
Atmel AT25256B-CUL
|---|---|---|
5 E B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
Top Mark
Y = YEAR OF ASSEMBLY
@ = Country of Ass’y
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,... AX, AY, AZ)
Y = SEAL YEAR
6: 2006 0: 2010
7: 2007 1: 2011
8: 2008 2: 2012
9: 2009 3: 2013
|---|---|---|---|
5 E B U
|---|---|---|---|
B Y M X X
|---|---|---|---|---|
* <-- PIN 1 INDICATOR
Top Mark
B = Country of Origin
Y = One Digit Year Code
M = One Digit Month Code
XX= TRACE CODE (ATMEL LOT NUMBER TO
COORESPOND WITH TRACE CODE LOG BOOK)
(e.g. XX = AA, AB, AC,... YZ, ZZ)
Y = ONE DIGIT YEAR CODE
4: 2004 7: 2007
5: 2005 8: 2008
6: 2006 9: 2009
M = SEAL MONTH
(USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """"""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
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Atmel AT25128B/256B
7. Ordering Codes
Atmel AT25128B Ordering Information
Notes: 1. Bulk delivery in tubes (SOIC and TSSOP 100/tube)
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN and VFBGA 5k/reel)
3. Contact Atmel Sales for Wafer sales
Ordering Code Voltage Range Package Operation Range
AT25128B-SSHL-B(1) (NiPdAu Lead Finish)
AT25128B-SSHL-T(2) (NiPdAu Lead Finish)
AT25128B-XHL-B(1) (NiPdAu Lead Finish)
AT25128B-XHL-T(2) (NiPdAu Lead Finish)
AT25128B-MAHL-T(2) (NiPdAu Lead Finish)
AT25128B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8U2-1
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT25128B-WWU11L(3) 1.8V to 5.5V Die Sale Industrial Temperature
(−40°C to 85°C)
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8MA2 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8U2-1 8-ball, die Ball Grid Array Package (VFBGA)
18
8698C–SEEPR–8/11
Atmel AT25128B/256B
Atmel AT25256B Ordering Information
Notes: 1. Bulk delivery in tubes (SOIC and TSSOP 100/tube)
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN and VFBGA 5k/reel)
3. Contact Atmel Sales for Wafer sales
Ordering Code Voltage Range Package Operation Range
AT25256B-SSHL-B(1) (NiPdAu Lead Finish)
AT25256B-SSHL-T(2) (NiPdAu Lead Finish)
AT25256B-XHL-B(1) (NiPdAu Lead Finish)
AT25256B-XHL-T(2) (NiPdAu Lead Finish)
AT25256B-MAHL-T(2) (NiPdAu Lead Finish)
AT25256B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8U2-1
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT25256B-WWU11L(3) 1.8V to 5.5V Die Sale Industrial Temperature
(−40°C to 85°C)
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8MA2 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8U2-1 8-ball, die Ball Grid Array Package (VFBGA)
19
8698C–SEEPR–8/11
Atmel AT25128B/256B
8. Packaging Information
8S1 JEDEC SOIC
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 0.25
A 1.35 1.75
b 0.31 0.51
C 0.17 0.25
D 4.80 5.05
E1 3.81 3.99
E 5.79 6.20
e 1.27 BSC
L 0.40 1.27
Ø
Ø
0° –
Ø
Ø
E
E
1
1
N
N
TOP VIEW
TOP VIEW
C
C
E1
E1
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
SIDE VIEW
8S1 F
5/19/10
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC) SWB
20
8698C–SEEPR–8/11
Atmel AT25128B/256B
8A2 TSSOP
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – 1.20
A2 0.80 1.00 1.05
b 0.19 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25mm (0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 E
5/19/10
8A2, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
21
8698C–SEEPR–8/11
Atmel AT25128B/256B
8MA2 - UDFN
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
8MA2 A
4/15/08
Notes: 1. This drawing is for general information only. Refer to
JEDEC Drawing MO-229 for proper dimensions,
tolerances, datums, etc.
2. The terminal #1 ID is a laser-marked feature.
3. Dimensions b applies to metalized terminal and is
measured between 0.15mm and 0.30mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should not
be measured in that radius area.
8MA2, 8-pad, 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
YNZ
1.40
1.20
0.50
0.00
0.30
0.18
0.20
D
E
D2
E2
A
A1
A2
C
L
e
b
K
2.00 BSC
3.00 BSC
1.50
1.30
0.55
0.02
0.152 REF
0.35
0.50 BSC
0.25
1.60
1.40
0.60
0.05
0.55
0.40
0.30
3
C
E
A
A1
A2
Pin 1 ID
D
8
7
6
5
1
2
3
4
D2
E2
e (6x)
L (8x)
b (8x)
Pin#1 ID
(R0.10) 0.35
K
1
2
3
4
8
7
6
5
22
8698C–SEEPR–8/11
Atmel AT25128B/256B
8U2-1 VFBGA
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
0.81
0.15
0.40
0.25
A
A1
A2
b
D
E
e
e1
d
d1
0.91
0.20
0.45
0.30
2.35 BSC
3.73 BSC
0.75 BSC
0.74 BSC
0.75 BSC
0.80 REF
1.00
0.25
0.50
0.35
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV.
TITLE GPC
Notes: 1. This drawing is for general information.
2. Dimension 'b' is measured at the maximum solder
ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
8U2-1 C
2/25/08
8U2-1, 8 ball, 2.35 x 3.73mm Body,
0.75mm pitch, VFBGA Package (dBGA2) GWW
Top View
A1 Ball Pad Corner DA
e
B
0.10 (4X)
Side View
// 0.10 C
0.08 C
C
CAB
C
Ø0.15 M
Ø0.08 M
A1
A2
A
Øb
Bottom View
8 SOLDER BALLS
A1 BALL PAD CORNER
e
(e1)
(d1)
d
A
B
C
D
21
23
8698C–SEEPR–8/11
Atmel AT25128B/256B
9. Revision History
Doc. Rev. Date Comments
8698C 08/2011
Update 8A2 and 8S1 package drawings
Correct page 13, Device Density from 156K to 256K
Correct page 9, table headings
Correct cross references on pages 7, 8, and 9
8698B 03/2010 Update Catalog Numbering Scheme
Update Ordering Information and package types
8698A 12/2009 Initial document release
8698C–SEEPR–8/11
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JAPAN
Tel: (+81) (3) 3523-3551
Fax: (+81) (3) 3523-7581
Product Contact
Technical Support
s_eeprom@atmel.com
Sales Contact
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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