Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3.3V CMOS
18-BIT UNIVERSAL BUS
TRANSCEIVER
WITH 3-STATE OUTPUTS
DESCRIPTION:
The FCT163601/A 18-bit registered transceiver is built
using advanced dual metal CMOS technology. These 18-bit
universal bus transceivers combine D-type latches and D-
type flip-flops to allow data flow in transparent, latched and
clocked modes.
Data flow in each direction is controlled by output-enable
(
OEAB
and
OEBA
), latch-enable (LEAB and LEBA), and clock
(CLKAB and CLKBA) inputs. The clock can be controlled by
the clock-enable (
CLKENAB
and
CLKENBA
) inputs. For A-to-
B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB is low, the
A-bus data is stored in the latch/flip-flop on the low-to-high
transition of CLKAB. Output enable
OEAB
is active low.
When
OEAB
is low, the outputs are active. When
OEAB
is
high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA
,
LEBA, CLKBA and
CLKENBA
.
The FCT163601 has series current limiting resistors. These
offer low ground bounce, minimal undershoot, and controlled
output fall times-reducing the need for external series termi-
nating resistors.
LEAB
CLKAB
LEBA
CLKBA
CLKENAB
OEAB
A1
TO 17 OTHER CHANNELS
OEBA
CE
1D
C1
CLK
CE
1D
C1
CLK
CLKENBA
1
56
55
2
28
30
29
27
354 B1
3251 drw 01
FUNCTIONAL BLOCK DIAGRAM
COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. 5.9 DSC-3251/1
1
IDT74FCT163601/A
ADVANCE INFORMATION
FEATURES:
• 0.5 MICRON CMOS Technology
•Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
•V
CC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
5.9 2
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
Capacitance VIN = 0V 3.5 6.0 pF
CI/O I/O
Capacitance VOUT = 0V 3.5 8.0 pF
NOTE:
1. This parameter is measured at characterization but not tested. 3251 lnk 04
PIN CONFIGURATIONS
3251 drw 02
CLKENAB
B
2
B
3
GND
B
4
B
5
V
CC
B
6
B
7
B
1
B
8
B
9
B
10
B
11
GND
B
12
B
13
V
CC
B
14
GND
CLKAB
B
16
B
15
B
17
GND
B
18
CLKBA
CLKENBA
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
GND
A
6
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
18
A
14
A
13
A
16
GND
A
17
LEBA
A
15
OEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SSOP
TSSOP/TVSOP
TOP VIEW
SO56-1
SO56-2
SO56-3
29
30
31
3225
26
27
28
PIN DESCRIPTION
Pin Names Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
Ax A-to-B Data Inputs or B-to-A 3-State Outputs
Bx B-to-A Data Inputs or A-to-B 3-State Outputs
CLKENAB
A to B Clock Enable Input (Active LOW)
CLKENBA
B to A Clock Enable Input (Active LOW)
3251 tbl 01
FUNCTION TABLE(1,4)
Inputs Outputs
CLKENAB
CLKENAB OEAB
OEAB
LEAB CLKAB A B
XHXXXZ
XLHXLL
XLHXHH
HLLXXB0
(2)
LLL↑LL
LLL↑HH
L LLLXB0
(2)
LLLHXB0
(3)
NOTES: 3251 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA
,
LEBA, CLKBA and
CLKENBA
.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
3251 lnk 03
Symbol Description Max. Unit
VTERM(2) Terminal Voltage with
Respect to GND –0.5 to +4.6 V
VTERM(3) Terminal Voltage with
Respect to GND –0.5 to +7.0 V
VTERM(4) Terminal Voltage with
Respect to GND –0.5 to
VCC + 0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +60 mA
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE
5.9 3
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 — 5.5 V
Input HIGH Level (I/O pins) 2.0 — VCC+0.5
VIL Input LOW Level Guaranteed Logic LOW Level –0.5 —0.8 V
(Input and I/O pins)
II H Input HIGH Current (Input pins) VCC = Max. VI = 5.5V — —±1µA
Input HIGH Current (I/O pins) VI = VCC ——±1
II L Input LOW Current (Input pins) VI = GND — —±1
Input LOW Current (I/O pins) VI = GND — —±1
IOZH High Impedance Output Current VCC = Max. VO = VCC ——±1µA
IOZL (3-State Output pins) VO = GND — —±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 –60 –110 mA
IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) 50 90 200 mA
VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VCC–0.2 — — V
VIN = VIH or VIL IOH = –3mA 2.4 3.0 —
VCC = 3.0V
VIN = VIH or VIL IOH = –8mA 2.4(5) 3.0 —
VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 V
VIN = VIH or VIL IOL = 16mA — 0.2 0.4
IOL = 24mA — 0.3 0.55
VCC = 3.0V
VIN = VIH or VIL IOL = 24mA — 0.3 0.50
IOS Short Circuit Current(4) VCC = Max., VO = GND(3) –60 –135 –240 mA
VHInput Hysteresis — — 150 —mV
ICCL
ICCH Quiescent Power Supply Current VCC = Max.,
VIN = GND or VCC — 0.1 10 µA
ICCZ
3251 lnk 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC –0.6V at rated current.
5.9 4
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply VCC = Max. — 2.0 30 µA
Current TTL Inputs HIGH VIN = VCC –0.6V(3
ICCD Dynamic Power Supply Current(4) VCC = Max., Outputs Open VIN = VCC — 60 100 µA/
OEAB
= VCC
OEBA
= GND VIN = GND MHz
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max., Outputs Open VIN = VCC — 0.6 1.0 mA
fCP = 10MHz (CLKBA) VIN = GND
50% Duty Cycle
OEAB
= VCC
OEBA
= GND
LEBA = GND VIN = VCC –0.6 — 0.6 1.0
CLKENBA
= GND VIN = GND
One Bit Toggling
fi = 5MHz
50% Duty Cycle
VCC = Max., Outputs Open VIN = VCC — 3.0 5.0(5)
fCP = 10MHz (CLKBA) VIN = GND
50% Duty Cycle
OEAB
= VCC
OEBA
= GND
LEBA = GND VIN = VCC –0.6 — 3.0 5.3(5)
CLKENBA
= GND VIN = GND
Eighteen Bits Toggling
fi = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
3251 tbl 06
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE
5.9 5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES: 3251 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
FCT163601 FCT163601A
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Unit
fMAX CLKAB or CLKBA frequency(4) CL = 50pF — 100 — 150 MHz
tPLH
tPHL Propagation Delay
Ax to Bx or Bx to Ax RL = 500Ω1.5 6.5 1.5 5.5 ns
tPLH
tPHL Propagation Delay
LEBA to Ax, LEAB to Bx 1.5 7.2 1.5 6.2 ns
tPLH
tPHL Propagation Delay
CLKBA to Ax, CLKAB to Bx 1.5 7.3 1.5 6.3 ns
tPZH
tPZL Output Enable Time
OEBA
to Ax,
OEAB
to Bx 1.5 7.5 1.5 6.5 ns
tPHZ
tPLZ Output Disable Time
OEBA
to Ax,
OEAB
to Bx 1.5 6.5 1.5 5.2 ns
tSU Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA 4.0 — 3.0 — ns
tHHold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA 0—0—ns
tSU Set-up Time
HIGH or LOW Clock
LOW 2.5 — 2.5 — ns
Ax to LEAB,
Bx to LEBA Clock
HIGH 2.0 — 2.0 — ns
tSU Set-up Time,
CLKEN
to CLK 3.0 — 2.5 — ns
tHHold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA 1.5 — 1.0 — ns
tHHold Time,
CKLEN
after CLK 0 — 0 — ns
tWLEAB or LEBA Pulse Width
HIGH(4) 3.0 — 2.5 — ns
tWCLKAB or CLKBA Pulse Width
HIGH or LOW(4) 3.0 — 3.0 — ns
tSK(o) Output Skew(3) — 0.5 — 0.5 ns
5.9 6
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE
ENABLE AND DISABLE TIMESPROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
SWITCH POSITION
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
3251 lnk 06
3251 lnk 08
3251 lnk 07
3251 lnk 05
Test Switch
Open Drain
Disable Low
Enable Low 6V
Disable High
Enable High GND
All Other tests Open
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to
exceed VCC.
3251 tbl 08
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT =Termination resistance: should be equal to ZOUT of the Pulse
Generator.
3251 lnk 04
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU tH
tREM
tSU tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
6V
SWITCH
GND
VOL
0.3V
0.3V
tPLZtPZL
tPZH tPHZ
3V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Pulse
Generator
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF 500Ω
500ΩGND
6V
←
Open
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE
5.9 7
ORDERING INFORMATION
IDT XX
Temp. Range XXXX
Device Type X
Package
74 –40
°
C to +85
°
C
PV
PA
PF
163601
163601A
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
Non-Inverting 18-Bit Registered Transceiver
FCT
