Filterless, High Efficiency, Mono 3 W Class-D Audio Amplifier SSM2319 The SSM2319 features a high efficiency, low noise modulation scheme that does not require any external LC output filters. The modulation continues to provide high efficiency even at low output power. It operates with 90% efficiency at 1.4 W into 8 or 85% efficiency at 3 W into 3 from a 5.0 V supply and has an SNR of 98 dB. Spread-spectrum pulse density modulation is used to provide lower EMI-radiated emissions compared with other Class-D architectures. FEATURES Filterless Class-D amplifier with ultraefficient spreadspectrum - modulation Internal modulator synchronization (SYNC) 3 W into 3 load and 1.4 W into 8 load at 5.0 V supply with <1% total harmonic distortion (THD) 90% efficiency at 5.0 V, 1.4 W into 8 speaker Signal-to-noise ratio (SNR): 98 dB Single-supply operation: 2.5 V to 5.5 V Ultralow shutdown current: 20 nA Short-circuit and thermal protection with autorecovery Available in 9-ball, 1.5 mm x 1.5 mm WLCSP Pop-and-click suppression Built-in resistors reduce board component count Default fixed 12 dB or user-adjustable gain setting SYNC can be activated in the event that end users are concerned about clock intermodulation (beating effect) of several amplifiers in close proximity. The SSM2319 has a micropower shutdown mode with a typical shutdown current of 20 nA. Shutdown is enabled by applying a logic low to the SD pin. APPLICATIONS The device also includes pop-and-click suppression circuitry. This minimizes voltage glitches at the output during turn-on and turn-off, reducing audible noise on activation and deactivation. Mobile phones MP3 players Portable gaming Portable electronics Educational toys The default gain of the SSM2319 is 12 dB, but users can reduce the gain by using a pair of external resistors (see the Gain section). The SSM2319 is specified over the industrial temperature range of -40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a 9-ball, 1.5 mm x 1.5 mm wafer level chip scale package (WLCSP). GENERAL DESCRIPTION The SSM2319 is a fully integrated, high efficiency Class-D audio amplifier. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a single 2.5 V to 5.5 V supply. It is capable of delivering 3 W of continuous output power with <1% THD + N driving a 3 load from a 5.0 V supply. FUNCTIONAL BLOCK DIAGRAM 0.1F 10F SSM2319 0.1F* AUDIO IN- AUDIO IN+ IN- 40k IN+ 40k VBATT 2.5V TO 5.5V VDD 160k OUT+ MODULATOR (-) FET DRIVER OUT- 0.1F* 160k SHUTDOWN SD BIAS POP/CLICK SUPPRESSION INTERNAL OSCILLATOR SYNC SYNCO SYNC OUTPUT SYNC INPUT *INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. 07550-001 GND SYNCI Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. SSM2319 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Overview ..................................................................................... 14 General Description ......................................................................... 1 Gain .............................................................................................. 14 Functional Block Diagram .............................................................. 1 Pop-and-Click Suppression ...................................................... 14 Revision History ............................................................................... 2 Output Modulation Description .............................................. 14 Specifications..................................................................................... 3 Layout .......................................................................................... 15 Absolute Maximum Ratings............................................................ 5 Input Capacitor Selection .......................................................... 15 Thermal Resistance ...................................................................... 5 Power Supply Decoupling ......................................................... 15 ESD Caution .................................................................................. 5 Syncronization (SYNC) Operation .......................................... 15 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 17 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 17 Typical Application Circuits.......................................................... 12 REVISION HISTORY 8/08--Revision 0: Initial Version Rev. 0 | Page 2 of 20 SSM2319 SPECIFICATIONS VDD = 5.0 V, TA = 25oC, RL = 8 +33 H, SYNCI = GND (standalone mode), unless otherwise noted. Table 1. Parameter DEVICE CHARACTERISTICS Output Power Symbol Conditions POUT RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 3 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 3 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 3 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 3 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 3 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 3 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V POUT = 1.4 W, 8 , VDD = 5.0 V POUT = 1 W into 8 , f = 1 kHz, VDD = 5.0 V POUT = 0.5 W into 8 , f = 1 kHz, VDD = 3.6 V Efficiency Total Harmonic Distortion + Noise THD + N Input Common-Mode Voltage Range Common-Mode Rejection Ratio Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio VCM CMRRGSM fSW VOOS Supply Current VDD PSRR PSRRGSM ISY Shutdown Current Min Typ Max 1.41 0.72 0.33 1.77 0.91 0.42 2.53 1.28 0.56 3.17 1 1.6 0.72 3.11 1.52 0.68 3.71 1.9 0.85 93 0.06 0.02 1.0 VCM = 2.5 V 100 mV at 217 Hz, output referred VDD - 1 57 300 2.0 G = 12 dB 5.5 W W W W W W W W W W W W W W W W W W % % % V dB kHz mV ISD Guaranteed from PSRR test VDD = 2.5 V to 5.0 V, dc input floating/ground VRIPPLE = 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 F VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V VIN = 0 V, load = 8 + 33 H, VDD = 5.0 V VIN = 0 V, load = 8 + 33 H, VDD = 3.6 V VIN = 0 V, load = 8 + 33 H, VDD = 2.5 V SD = GND GAIN CONTROL Closed-Loop Gain Differential Input Impedance Av ZIN SD = VDD 12 40 dB k SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance VIH VIL tWU tSD ZOUT ISY 1 mA ISY 300 nA SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND 1.2 0.5 28 5 >100 V V ms s k Rev. 0 | Page 3 of 20 2.5 70 Unit 85 60 3.6 3.2 2.7 3.7 3.3 2.8 20 V dB dB mA mA mA mA mA mA nA SSM2319 Parameter NOISE PERFORMANCE Output Voltage Noise Symbol Conditions en Signal-to-Noise Ratio SYNC OPERATIONAL FREQUENCY SNR VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded, AV = 12 dB, A weighting POUT = 1.4 W, RL = 8 1 Min 5 Typ Max 40 V 98 dB MHz 12 Although the SSM2319 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations. Rev. 0 | Page 4 of 20 Unit SSM2319 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. THERMAL RESISTANCE Table 2. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) ESD Susceptibility Rating 6V VDD VDD -65C to +150C -40C to +85C -65C to +165C 300C 4 kV Table 3. Package Type 9-Ball, 1.5 mm x 1.5 mm WLCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 20 PCB 1S0P 2S0P JA 162 76 JB 39 21 Unit C/W C/W SSM2319 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 A B C 07550-002 SSM2319 TOP VIEW BALL SIDE DOWN (Not to Scale) Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1A 1B 1C 2A 2B 2C 3A 3B 3C IN- IN+ GND SD Inverting Input. Noninverting Input. Ground. Shutdown Input. Active low digital input. SYNC Input. Power Supply. SYNC Output. Inverting Output. Noninverting Output. SYNCI VDD SYNCO OUT- OUT+ Rev. 0 | Page 6 of 20 SSM2319 TYPICAL PERFORMANCE CHARACTERISTICS 100 RL = 8 + 33H GAIN = 12dB 1 THD + N (%) 0.1 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 07550-003 0.001 0.0001 100 VDD = 2.5V VDD = 3.6V VDD = 5V 10k 100k RL = 4 + 33H GAIN = 12dB VDD = 5V 2W 1 THD + N (%) THD + N (%) 1k 10 0.1 0.01 1 0.1 1W 0.5W 0.01 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 07550-004 0.001 0.0001 10 1k 10k 100k Figure 7. THD + N vs. Frequency, RL = 4 + 33 H, Gain = 12 dB, VDD = 5 V 100 RL = 3 + 33H GAIN = 12dB VDD = 2.5V VDD = 3.6V VDD = 5V RL = 3 + 33H GAIN = 12dB VDD = 5V 10 THD + N (%) 10 100 FREQUENCY (Hz) Figure 4. THD + N vs. Output Power into RL = 4 + 33 H, Gain = 12 dB THD + N (%) 100 Figure 6. THD + N vs. Frequency, RL = 8 + 33 H, Gain = 12 dB, VDD = 5 V RL = 4 + 33H GAIN = 12dB 10 10 FREQUENCY (Hz) Figure 3. THD + N vs. Output Power into RL = 8 + 33 H, Gain = 12 dB 100 1W 0.5W 0.25W 0.1 0.01 0.01 100 1 07550-006 THD + N (%) 10 VDD = 2.5V VDD = 3.6V VDD = 5V 10 RL = 8 + 33H GAIN = 12dB VDD = 5V 07550-007 100 1 3W 1 1.5W 0.75W 0.1 0.1 0.001 0.01 0.1 OUTPUT POWER (W) 1 10 0.001 07550-005 0.01 0.0001 10 100 1k FREQUENCY (Hz) Figure 5. THD + N vs. Output Power into RL = 3 + 33 H, Gain = 12 dB 10k 100k 07550-008 0.01 Figure 8. THD + N vs. Frequency, RL = 3 + 33 H, Gain = 12 dB, VDD = 5 V Rev. 0 | Page 7 of 20 SSM2319 100 RL = 8 + 33H GAIN = 12dB VDD = 3.6V RL = 8 + 33H GAIN = 12dB VDD = 2.5V 10 10 1 1 THD + N (%) 0.1 0.1 0.5W 10 100 1k 10k 100k FREQUENCY (Hz) Figure 9. THD + N vs. Frequency, RL = 8 + 33 H, Gain = 12 dB, VDD = 3.6 V 100 0.001 07550-009 10 100 100 RL = 4 + 33H GAIN = 12dB VDD = 2.5V THD + N (%) 1W 0.5W 1 0.1 0.25W 0.125W 0.5W 0.25W 0.01 0.01 100 1k 10k 100k Figure 10. THD + N vs. Frequency, RL = 4 + 33 H, Gain = 12 dB, VDD = 3.6 V 100 0.001 07550-010 10 FREQUENCY (Hz) 100 1k 10k 100k Figure 13. THD + N vs. Frequency, RL = 4 + 33 H, Gain = 12 dB, VDD = 2.5 V 100 RL = 3 + 33H GAIN = 12dB VDD = 2.5V 0.75W 10 1.5W THD + N (%) 1 0.1 10 FREQUENCY (Hz) RL = 3 + 33H GAIN = 12dB VDD = 3.6V 10 THD + N (%) 100k 10 0.1 0.75W 0.38W 1 0.38W 0.2W 0.1 0.01 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 07550-011 0.001 10k Figure 12. THD + N vs. Frequency, RL = 8 + 33 H, Gain = 12 dB, VDD = 2.5 V RL = 4 + 33H GAIN = 12dB VDD = 3.6V 1 0.001 1k FREQUENCY (Hz) 10 THD + N (%) 0.125W 0.0625W 07550-013 0.001 0.01 0.25W 0.125W 07550-012 0.01 0.25W Figure 11. THD + N vs. Frequency, RL = 3 + 33 H, Gain = 12 dB, VDD = 3.6 V 10 100 1k FREQUENCY (Hz) 10k 100k 07550-014 THD + N (%) 100 Figure 14. THD + N vs. Frequency, RL = 3 + 33 H, Gain = 12 dB, VDD = 2.5 V Rev. 0 | Page 8 of 20 SSM2319 2.0 3.7 RL = 8 + 33H RL = 8 + 33H GAIN = 12dB f = 1kHz 1.8 3.5 3.3 3.1 OUTPUT POWER (W) SUPPLY CURRENT (mA) 1.6 RL = 4 + 33H 2.9 RL = 3 + 33H 2.7 NO LOAD 1.4 1.2 10% 1.0 0.8 1% 0.6 0.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 0 2.5 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 15. Supply Current vs. Supply Voltage Figure 18. Maximum Output Power vs. Supply Voltage, RL = 8 + 33 H, Gain = 12 dB 4.0 100 VDD = 2.5V 90 3.5 DO NOT EXCEED 3W CONTINUOUS OUTPUT POWER 3.0 VDD = 5V 80 70 EFFICIENCY (%) OUTPUT POWER (W) 3.0 07550-018 0.2 07550-015 2.3 2.5 2.5 10% 2.0 1.5 1% VDD = 3.6V 60 50 40 30 1.0 20 RL = 3 + 33H GAIN = 12dB f = 1kHz 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 0 RL = 8 + 33H 0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.0 OUTPUT POWER (W) Figure 19. Efficiency vs. Output Power into RL = 8 + 33 H Figure 16. Maximum Output Power vs. Supply Voltage, RL = 3 + 33 H, Gain = 12 dB 100 3.5 DO NOT EXCEED 3W CONTINUOUS OUTPUT POWER 90 3.0 80 2.5 VDD = 2.5V VDD = 3.6V VDD = 5V 2.0 EFFICIENCY (%) 70 10% 1.5 1% 1.0 60 50 40 30 20 0 2.5 RL = 4 + 33H GAIN = 12dB f = 1kHz 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 10 0 RL = 4 + 33H 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 OUTPUT POWER (W) Figure 20. Efficiency vs. Output Power into RL = 4 + 33 H Figure 17. Maximum Output Power vs. Supply Voltage, RL = 4 + 33 H, Gain = 12 dB Rev. 0 | Page 9 of 20 07550-020 0.5 07550-017 OUTPUT POWER (W) 1.0 07550-019 0 2.5 10 07550-016 0.5 SSM2319 100 0.9 90 0.8 VDD = 3.6V VDD = 5V VDD = 2.5V 60 50 40 30 20 0 450 RL = 8 + 33H 0.5 1.0 1.5 2.0 2.5 3.0 3.5 RL = 8 + 33H 400 VDD = 5V 350 0.12 SUPPLY CURRENT (mA) VDD = 5V 0.10 0.08 0.06 VDD = 3.6V 0.04 300 VDD = 3.6V 250 VDD = 2.5V 200 150 100 VDD = 2.5V 50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 OUTPUT POWER (W) 0 07550-022 0 0.5 1.0 1.5 2.0 2.5 OUTPUT POWER (W) Figure 22. Power Dissipation vs. Output Power into RL = 8 + 33 H 0.30 0 07550-025 POWER DISSIPATION (W) 0.2 Figure 24. Power Dissipation vs. Output Power into RL = 3 + 33 H 0.02 Figure 25. Supply Current vs. Output Power into RL = 8 + 33 H 800 RL = 4 + 33H RL = 4 + 33H 700 0.25 VDD = 5V VDD = 5V SUPPLY CURRENT (mA) POWER DISSIPATION (W) VDD = 2.5V 0.3 OUTPUT POWER (W) 0.14 0.20 VDD = 3.6V 0.15 VDD = 2.5V 0.10 0.05 600 VDD = 3.6V 500 400 VDD = 2.5V 300 200 100 0 0.5 1.0 1.5 2.0 OUTPUT POWER (W) 2.5 3.0 07550-023 0 0.4 0 07550-021 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 Figure 21. Efficiency vs. Output Power into RL = 3 + 33 H 0 VDD = 3.6V 0.5 07550-024 RL = 3 + 33H OUTPUT POWER (W) 0.16 0.6 0.1 10 0 VDD = 5V 0.7 Figure 23. Power Dissipation vs. Output Power into RL = 4 + 33 H 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 OUTPUT POWER (W) Figure 26. Supply Current vs. Output Power into RL = 4 + 33 H Rev. 0 | Page 10 of 20 07550-026 EFFICIENCY (%) 70 POWER DISSIPATION (W) 80 RL = 3 + 33H SSM2319 7 RL = 3 + 33H 800 VDD = 5V 5 VDD = 3.6V VDD = 2.5V 3 2 300 1 200 0 100 -1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 OUTPUT POWER (W) -2 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 TIME (ms) Figure 27. Supply Current vs. Output Power into RL = 3 + 33 H Figure 30. Turn-On Response 0 7 -10 6 -20 VOLTAGE (V) PSRR (dB) 4 -40 -50 -60 2 0 -90 -1 100 1k 10k 100k 07550-028 -80 FREQUENCY (Hz) Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency -10 -20 -30 -40 -50 -60 -70 -80 1k 10k 100k FREQUENCY (Hz) 07550-029 -90 100 -2 -100 SD INPUT -80 -60 -40 -20 0 20 40 TIME (s) Figure 31. Turn-Off Response 0 CMRR (dB) 3 1 -70 -100 10 OUTPUT 5 -30 -100 10 07550-030 VOLTAGE (V) 500 400 SD INPUT 4 07550-027 SUPPLY CURRENT (mA) 700 600 OUTPUT 6 Figure 29. Common-Mode Rejection Ratio (CMRR) vs. Frequency Rev. 0 | Page 11 of 20 60 80 100 07550-031 900 SSM2319 TYPICAL APPLICATION CIRCUITS EXTERNAL GAIN SETTINGS = 160k/(40k + REXT) 0.1F 10F SSM2319 0.1F* AUDIO IN- REXT REXT AUDIO IN+ IN- IN+ VBATT 2.5V TO 5.5V VDD 160k 40k 40k OUT+ MODULATOR (-) FET DRIVER OUT- 0.1F* 160k SD SHUTDOWN POP/CLICK SUPPRESSION INTERNAL OSCILLATOR BIAS SYNC SYNC OUTPUT SYNCO GND SYNCI 07550-032 SYNC INPUT *INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. Figure 32. Differential Input Configuration, User-Adjustable Gain EXTERNAL GAIN SETTINGS = 160k/(40k + REXT ) 0.1F 10F SSM2319 0.1F REXT REXT AUDIO IN+ IN- IN+ VBATT 2.5V TO 5.5V VDD 160k 40k 40k OUT+ MODULATOR (-) FET DRIVER OUT- 0.1F 160k BIAS POP/CLICK SUPPRESSION INTERNAL OSCILLATOR GND SYNC SYNCO SYNC OUTPUT SYNCI SYNC INPUT Figure 33. Single-Ended Input Configuration, User-Adjustable Gain Rev. 0 | Page 12 of 20 07550-033 SHUTDOWN SD SSM2319 SSM2319 SSM2319 SSM2319 STANDALONE MASTER SLAVE INTERNAL OSCILLATOR FET DRIVER SYNC OUT+ MODULATOR (-) OUT- SYNC OUTPUT INTERNAL OSCILLATOR SYNCO FET DRIVER SYNC OUT+ MODULATOR (-) OUT- SYNC OUTPUT FET DRIVER INTERNAL OSCILLATOR SYNC SYNCO SYNCI SYNCI SYNCI SYNC INPUT SYNC INPUT SYNC INPUT TO SLAVE OUT- SYNC OUTPUT SYNCO 07550-035 OUT+ MODULATOR (-) FROM MASTER NOTES 1. TRACE LENGTH FROM SYNCI TO SYNCO IS LESS THAN 1mm. Figure 34. Synchronization Operation Modes SSM2319 MASTER SLAVE 1 SSM2319 SLAVE 2 OUT+ MODULATOR (-) INTERNAL OSCILLATOR FET DRIVER SYNC OUT+ MODULATOR (-) OUT- SYNC OUTPUT SYNCO INTERNAL OSCILLATOR FET DRIVER SYNC OUT+ MODULATOR (-) OUT- SYNC OUTPUT SYNCO INTERNAL OSCILLATOR FET DRIVER SYNC SYNCI SYNCI SYNCI SYNC INPUT SYNC INPUT SYNC INPUT Figure 35. Typical SYNC Master-Slave Daisy-Chain Configuration Rev. 0 | Page 13 of 20 OUT- SYNC OUTPUT SYNCO 07550-036 SSM2319 SSM2319 THEORY OF OPERATION OVERVIEW OUTPUT MODULATION DESCRIPTION The SSM2319 mono Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external components count, conserving board space and, thus, reducing systems cost. The SSM2319 does not require an output filter. Instead, it relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. Most Class-D amplifiers use some variation of pulse-width modulation (PWM), but the SSM2319 uses a - modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. - modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. - modulation reduces the amplitude of spectral components at high frequencies, reducing EMI emission that may otherwise be radiated by speakers and long cable traces. Due to the inherent spread-spectrum nature of - modulation, the need for oscillator synchronization is eliminated for designs incorporating multiple SSM2319 amplifiers. The SSM2319 uses 3-level - output modulation. Each output is able to swing from GND to VDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, there are always noise sources present. Due to the constant presence of noise, a differential pulse is generated in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. GAIN When the user wants to send an input signal, an output pulse is generated to follow the input voltage. The differential pulse density is increased by raising the input signal level. Figure 36 depicts 3-level - output modulation with and without input stimulus. OUTPUT = 0V OUT+ 0V +5V OUT- 0V +5V VOUT The SSM2319 has a default gain of 12 dB that can be reduced by using a pair of external resistors with a value calculated as follows: 0V -5V OUTPUT > 0V OUT+ External Gain Settings = 160 k/(40 k + REXT) Voltage transients at the output of the audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. Such transients can be generated when the amplifier system changes its operating mode. For example, audible transient sources include system power-up/ power-down, mute/unmute, an input source change, and a sample rate change. The SSM2319 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. 0V +5V VOUT 0V OUTPUT < 0V OUT+ OUT- VOUT +5V 0V +5V OUT- POP-AND-CLICK SUPPRESSION +5V +5V 0V +5V 0V 0V -5V 07550-034 The SSM2319 also offers protection circuits for overcurrent and temperature protection. However, most of the time, the output differential voltage is 0 V, due to the Analog Devices, Inc., patented 3-level, - output modulation feature. This feature ensures that the current flowing through the inductive load is small. Figure 36. 3-Level - Output Modulation With and Without Input Stimulus Rev. 0 | Page 14 of 20 SSM2319 LAYOUT POWER SUPPLY DECOUPLING As output power continues to increase, care must be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR and use 1 oz or 2 oz of copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality, low ESL, low ESR capacitor, usually of around 4.7 F. This capacitor bypasses low frequency noises to the ground plane. For high frequency transients noises, use a 0.1 F capacitor as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2319 helps to maintain efficient performance. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and to the supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. In addition, good PCB layouts isolate critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency circuits. SYNCRONIZATION (SYNC) OPERATION SYNC is the feature that allows an external clock signal to control the modulator of the SSM2319. The SSM2319 can act in standalone mode, act as a master device, or act as a slave device. Although the inherent random switching frequency of the Analog Devices patented 3-level PDM modulation virtually eliminates the need for SYNC, this feature can be activated in the event that end users are concerned about clock intermodulation (beating effect) of several amplifiers in close proximity. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more when compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. Another use for the SYNC feature is its ability to adjust modulator frequency to move harmonic interference to a less sensitive frequency band in certain applications with very delicate interference requirements. If the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and, similarly, the digital ground plane should be underneath the digital power plane. There should be no overlap between analog and digital ground planes or analog and digital power planes. Modulator synchronization is initiated after the internal shutdown signal is released. SYNCO buffers the internal oscillator clock with a delay of 127 clock cycles. INPUT CAPACITOR SELECTION The SSM2319 does not require input coupling capacitors if the input signal is biased from 1.0 V to VDD - 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if using a single-ended source. If highpass filtering is needed at the input, the input capacitor, along with the input resistor of the SSM2319, form a high-pass filter whose corner frequency is determined by fC = 1/{2 x (40 k + REXT) x CIN} The input capacitor can significantly affect the performance of the circuit. Not using input capacitors degrades both the output offset of the amplifier and the PSRR performance. Although the synchronization frequency operates from 5 MHz to 12 MHz, the optimal operating range is 6 MHz to 9 MHz. When synchronizing several SSM2319 amplifiers, configure them in a daisy-chain configuration, as shown in Figure 35. Using this configuration causes a small delay in the SYNCO-toSYNCO transitions of multiple SSM2319s, preventing large surges of instantaneous current and reducing excessive loading of the power supply. When configuring one device to act as a master device, it is mandatory that the connection from SYNCO to SYCNI be less than 1 mm. As in many digital systems, to maintain signal integrity when interfacing several clocking systems, users must insert series dumping resistors close to the SYNCO pin if long trace lengths are used for synchronization connections. A typical value used is 750 . The series dumping resistor should be placed as close to the SYNCO pin as possible. If careful layout practices are followed to minimize signal trace routing from the SYNCO pin of one device to the SYNCI pin of another, a dumping resistor is not necessary. If the SYNC feature is not used, or if the SYNC feature is not interfacing the SYNCO pin to an external device, it is recommended that the SYNCO pin be floated. Rev. 0 | Page 15 of 20 SSM2319 * SYNCI = external clock. SYNCO is a buffered clock output sourced from an external clock signal. One clock cycle after the internal modulator detect signal is released, an irregular pulse appears on MCLK before the first buffered output signal begins on SYNCO, as shown in Figure 39. The SYNC operating modes include the following: SD INTERNAL REF SIGNAL MOD SYNCI = GND or VDD. SYNCO stops generating pulses. The modulator is controlled by an internal clock signal, as shown in Figure 37. SYNCI SYNCO MCLK SYNCI = CLKIN Figure 39. SYNCI = External Clock SD REF INTERNAL SIGNAL MOD * SYNCI = GND, transitions to clock. When the SYNCI pin is connected to GND first but then transitions to a clock signal, SYNCO generates several internal clock signals before finally being synchronized to the external clock signal, as shown in Figure 40. SYNCI 07550-037 SYNCO MCLK SYNCI = GND Figure 37. SYNCI = GND or VDD SYNCI = SYNCO. SYNCO is the delayed clock signal of SYNCI, as shown in Figure 38. SYNCI SYNCO SD MCLK INTERNAL REF SIGNAL MOD SYNCI = GND TO CLKIN Figure 40. SYNCI = GND to Clock Input SYNCI * SYNCO MCLK SYNCI = SYNCO SYNCI = CLK, transitions to GND. When SYNCI is connected to a clock signal but then transitions to GND, the SYNCO pin immediately stops generating a clock signal. After a short clock loss detect time, the internal modulator synchronizes to the internal clock signal, as shown in Figure 41. 07550-038 * SD INTERNAL REF SIGNAL MOD 07550-040 * Initial SYNC startup. An internal reference signal, REF, is released after one complete internal clock cycle (MCLK). After REF is released, another internal signal, MOD, waits 127 internal clock cycles. This operates as a training signal to determine the SYNCI/SYNCO connection. During this time, SYNCO is the internal clock signal. Figure 38. SYNCI = SYNCO SD INTERNAL REF SIGNAL MOD SYNCI SYNCO CLK LOSS DETECT MCLK SYNCI = CLKIN TO GND Figure 41. SYNCI = Clock Input to GND Rev. 0 | Page 16 of 20 07550-041 * 07550-039 Operating Modes SSM2319 OUTLINE DIMENSIONS 1.490 1.460 SQ 1.430 SEATING PLANE 3 2 A 0.350 0.320 0.290 B C 0.50 BALL PITCH TOP VIEW (BALL SIDE DOWN) 0.385 0.360 0.335 1 BOTTOM VIEW 0.270 0.240 0.210 (BALL SIDE UP) 101507-C A1 BALL CORNER 0.655 0.600 0.545 Figure 42. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-2) Dimensions shown in millimeters ORDERING GUIDE Model SSM2319CBZ-R2 1 SSM2319CBZ-REEL1 SSM2319CBZ-REEL71 EVAL-SSM2319Z1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 17 of 20 Package Option CB-9-2 CB-9-2 CB-9-2 SSM2319 NOTES Rev. 0 | Page 18 of 20 SSM2319 NOTES Rev. 0 | Page 19 of 20 SSM2319 NOTES (c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07550-0-8/08(0) Rev. 0 | Page 20 of 20