Filterless, High Efficiency,
Mono 3 W Class-D Audio Amplifier
SSM2319
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
Filterless Class-D amplifier with ultraefficient spread-
spectrum Σ-Δ modulation
Internal modulator synchronization (SYNC)
3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion (THD)
90% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Signal-to-noise ratio (SNR): 98 dB
Single-supply operation: 2.5 V to 5.5 V
Ultralow shutdown current: 20 nA
Short-circuit and thermal protection with autorecovery
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 12 dB or user-adjustable gain setting
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
GENERAL DESCRIPTION
The SSM2319 is a fully integrated, high efficiency Class-D
audio amplifier. It is designed to maximize performance for
mobile phone applications. The application circuit requires a
minimum of external components and operates from a single
2.5 V to 5.5 V supply. It is capable of delivering 3 W of continuous
output power with <1% THD + N driving a 3 Ω load from a
5.0 V supply.
The SSM2319 features a high efficiency, low noise modulation
scheme that does not require any external LC output filters. The
modulation continues to provide high efficiency even at low output
power. It operates with 90% efficiency at 1.4 W into 8 Ω or 85%
efficiency at 3 W into 3 Ω from a 5.0 V supply and has an SNR
of 98 dB. Spread-spectrum pulse density modulation is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures.
SYNC can be activated in the event that end users are concerned
about clock intermodulation (beating effect) of several amplifiers in
close proximity.
The SSM2319 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying a
logic low to the SD pin.
The device also includes pop-and-click suppression circuitry.
This minimizes voltage glitches at the output during turn-on and
turn-off, reducing audible noise on activation and deactivation.
The default gain of the SSM2319 is 12 dB, but users can reduce
the gain by using a pair of external resistors (see the Gain section).
The SSM2319 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm
wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
S
HUTDOWN
0.1µF
VDD
POP/CLICK
SUPPRESSION
OUT+
OUT–
IN–
VBATT
2.5V TO 5.5V
IN+ MODULATOR
(Σ-Δ)
GND
SYNC OUTPUT
10µF
0.1µF*
*INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
0.1µF*
SD
AUDIO IN+
AUDIO IN–
SSM2319
40kΩ
160kΩ
160kΩ
40kΩFET
DRIVER
BIAS INTERNAL
OSCILLATOR
07550-001
SYNCI
SYNCO
SYNC INPUT
SYNC
Figure 1.
SSM2319
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Typical Application Circuits .......................................................... 12
Theory of Operation ...................................................................... 14
Overview ..................................................................................... 14
Gain .............................................................................................. 14
Pop-and-Click Suppression ...................................................... 14
Output Modulation Description .............................................. 14
Layout .......................................................................................... 15
Input Capacitor Selection .......................................................... 15
Power Supply Decoupling ......................................................... 15
Syncronization (SYNC) Operation .......................................... 15
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
8/08—Revision 0: Initial Version
SSM2319
Rev. 0 | Page 3 of 20
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω +33 μH, SYNCI = GND (standalone mode), unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power POUT RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.41 W
R
L = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.72 W
R
L = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.33 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.77 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.91 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.42 W
R
L = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 2.53 W
R
L = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.28 W
R
L = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.56 W
R
L = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.171 W
R
L = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.6 W
R
L = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.72 W
R
L = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.11
W
R
L = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.52 W
R
L = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.68 W
R
L = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.71
W
R
L = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.9 W
R
L = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.85 W
Efficiency η POUT = 1.4 W, 8 Ω, VDD = 5.0 V 93 %
Total Harmonic Distortion + Noise THD + N POUT = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.06 %
P
OUT = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.02 %
Input Common-Mode Voltage Range VCM 1.0 VDD − 1 V
Common-Mode Rejection Ratio CMRRGSM VCM = 2.5 V ± 100 mV at 217 Hz, output referred 57 dB
Average Switching Frequency fSW 300 kHz
Differential Output Offset Voltage VOOS G = 12 dB 2.0 mV
POWER SUPPLY
Supply Voltage Range VDD Guaranteed from PSRR test 2.5 5.5 V
Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating/ground 70 85 dB
PSRRGSM VRIPPLE = 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF 60 dB
Supply Current ISY VIN = 0 V, no load, VDD = 5.0 V 3.6 mA
V
IN = 0 V, no load, VDD = 3.6 V 3.2 mA
V
IN = 0 V, no load, VDD = 2.5 V 2.7 mA
V
IN = 0 V, load = 8 Ω + 33 μH, VDD = 5.0 V 3.7 mA
V
IN = 0 V, load = 8 Ω + 33 μH, VDD = 3.6 V 3.3 mA
V
IN = 0 V, load = 8 Ω + 33 μH, VDD = 2.5 V 2.8 mA
Shutdown Current ISD SD = GND 20 nA
GAIN CONTROL
Closed-Loop Gain Av 12 dB
Differential Input Impedance ZIN SD = VDD 40 kΩ
SHUTDOWN CONTROL
Input Voltage High VIH ISY ≥ 1 mA 1.2 V
Input Voltage Low VIL ISY ≤ 300 nA 0.5 V
Turn-On Time tWU SD rising edge from GND to VDD 28 ms
Turn-Off Time tSD SD falling edge from VDD to GND 5 μs
Output Impedance ZOUT SD = GND >100 kΩ
SSM2319
Rev. 0 | Page 4 of 20
Parameter Symbol Conditions Min Typ Max Unit
NOISE PERFORMANCE
Output Voltage Noise en VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded,
AV = 12 dB, A weighting
40 μV
Signal-to-Noise Ratio SNR POUT = 1.4 W, RL = 8 Ω 98 dB
SYNC OPERATIONAL FREQUENCY 5 12 MHz
1 Although the SSM2319 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.
SSM2319
Rev. 0 | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage 6 V
Input Voltage VDD
Common-Mode Input Voltage VDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Susceptibility 4 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3.
Package Type PCB θJA θ
JB Unit
9-Ball, 1.5 mm × 1.5 mm WLCSP 1S0P 162 39 °C/W
2S0P 76 21 °C/W
ESD CAUTION
SSM2319
Rev. 0 | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SSM2319
TOP VIEW
BALL SIDE DOWN
(Not to Scale)
BALL A1
CORNER
A
321
B
C
07550-002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1A IN− Inverting Input.
1B IN+ Noninverting Input.
1C GND Ground.
2A SD Shutdown Input. Active low digital input.
2B SYNCI SYNC Input.
2C VDD Power Supply.
3A SYNCO SYNC Output.
3B OUT− Inverting Output.
3C OUT+ Noninverting Output.
SSM2319
Rev. 0 | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-006
FREQUENCY (Hz)
THD + N (%)
R
L
= 8Ω + 33µH
GAIN = 12dB
V
DD
= 5V
1W
0.5W
0.25W
VDD = 2.5V
VDD = 3.6V
VDD = 5V
0.001
0.01
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10
0
7550-003
OUTPUT POWER (W)
THD + N (%)
RL = 8Ω + 33µH
GAIN = 12dB
Figure 3. THD + N vs. Output Power into RL = 8 Ω + 33 μH, Gain = 12 dB
Figure 6. THD + N vs. Frequency, RL = 8 Ω + 33 μH, Gain = 12 dB, VDD = 5 V
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
0.001
0.01
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10
07550-004
OUTPUT POWER (W)
THD + N (%)
R
L
= 4Ω + 33µH
GAIN = 12dB
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-007
FREQUENCY (Hz)
THD + N (%)
R
L
= 4Ω + 33µH
GAIN = 12dB
V
DD
= 5V
1W
0.5W
2W
Figure 4. THD + N vs. Output Power into RL = 4 Ω + 33 μH, Gain = 12 dB
Figure 7. THD + N vs. Frequency, RL = 4 Ω + 33 μH, Gain = 12 dB, VDD = 5 V
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
0.01
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10
0
7550-005
OUTPUT POWER (W)
THD + N (%)
R
L
= 3Ω + 33µH
GAIN = 12dB
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-008
FREQUENCY (Hz)
THD + N (%)
R
L
= 3Ω + 33µH
GAIN = 12dB
V
DD
= 5V
1.5W
0.75W
3W
Figure 5. THD + N vs. Output Power into RL = 3 Ω + 33 μH, Gain = 12 dB
Figure 8. THD + N vs. Frequency, RL = 3Ω + 33 μH, Gain = 12 dB, VDD = 5 V
SSM2319
Rev. 0 | Page 8 of 20
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-009
FREQUENCY (Hz)
THD + N (%)
R
L
= 8Ω + 33µH
GAIN = 12dB
V
DD
= 3.6V
0.25W
0.125W
0.5W
Figure 9. THD + N vs. Frequency, RL = 8 Ω + 33 μH, Gain = 12 dB, VDD = 3.6 V
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-010
FREQUENCY (Hz)
THD + N (%)
R
L
= 4Ω + 33µH
GAIN = 12dB
V
DD
= 3.6V
1W
0.5W
0.25W
Figure 10. THD + N vs. Frequency, RL = 4 Ω + 33 μH, Gain = 12 dB, VDD = 3.6 V
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-011
FREQUENCY (Hz)
THD + N (%)
R
L
= 3Ω + 33µH
GAIN = 12dB
V
DD
= 3.6V
0.75W
0.38W
1.5W
Figure 11. THD + N vs. Frequency, RL = 3 Ω + 33 μH, Gain = 12 dB, VDD = 3.6 V
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-012
FREQUENCY (Hz)
THD + N (%)
R
L
= 8Ω + 33µH
GAIN = 12dB
V
DD
= 2.5V
0.125W
0.0625W
0.25W
Figure 12. THD + N vs. Frequency, RL = 8 Ω + 33 μH, Gain = 12 dB, VDD = 2.5 V
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-013
FREQUENCY (Hz)
THD + N (%)
R
L
= 4Ω + 33µH
GAIN = 12dB
V
DD
= 2.5V
0.25W
0.125W
0.5W
Figure 13. THD + N vs. Frequency, RL = 4 Ω + 33 μH, Gain = 12 dB, VDD = 2.5 V
10 100 1k 10k 100k
0.001
0.01
0.1
1
10
100
07550-014
FREQUENCY (Hz)
THD + N (%)
R
L
= 3Ω + 33µH
GAIN = 12dB
V
DD
= 2.5V
0.38W
0.2W
0.75W
Figure 14. THD + N vs. Frequency, RL = 3 Ω + 33 μH, Gain = 12 dB, VDD = 2.5 V
SSM2319
Rev. 0 | Page 9 of 20
NO LOAD
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
2.5 3.0 3.5 4.0 4.5 5.0 5.5
07550-015
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
R
L
= 8Ω + 33µH
R
L
= 3Ω + 33µH
R
L
= 4Ω + 33µH
Figure 15. Supply Current vs. Supply Voltage
2.5 3.0 3.5 4.0 4.5 5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
10%
1%
R
L
= 3Ω + 33µH
GAIN = 12dB
f = 1kHz
07550-016
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
DO NOT EXCEED 3W
CONTINUOUS OUTPUT POWER
Figure 16. Maximum Output Power vs. Supply Voltage,
RL = 3 Ω + 33 μH, Gain = 12 dB
2.53.03.54.04.55.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
10%
1%
R
L
= 4Ω + 33µH
GAIN = 12dB
f = 1kHz
DO NOT EXCEED 3W
CONTINUOUS OUTPUT POWER
07550-017
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
Figure 17. Maximum Output Power vs. Supply Voltage,
RL = 4 Ω + 33 μH, Gain = 12 dB
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.53.03.54.04.55.0
10%
1%
R
L
= 8Ω + 33µH
GAIN = 12dB
f = 1kHz
0
7550-018
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
Figure 18. Maximum Output Power vs. Supply Voltage,
RL = 8 Ω + 33 μH, Gain = 12 dB
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V
DD
= 5V
R
L
= 8Ω + 33µH
07550-019
OUTPUT POWER (W)
EFFICIENCY (%)
V
DD
= 3.6V
V
DD
= 2.5V
Figure 19. Efficiency vs. Output Power into RL = 8 Ω + 33 μH
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
0
10
20
30
40
50
60
70
80
90
100
V
DD
= 5V
R
L
= 4Ω + 33µH
07550-020
OUTPUT POWER (W)
EFFICIENCY (%)
V
DD
= 3.6V
V
DD
= 2.5V
Figure 20. Efficiency vs. Output Power into RL = 4 Ω + 33 μH
SSM2319
Rev. 0 | Page 10 of 20
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
0
10
20
30
40
50
60
70
80
90
100
V
DD
= 5V
R
L
= 3Ω + 33µH
07550-021
OUTPUT POWER (W)
EFFICIENCY (%)
V
DD
= 3.6V
V
DD
= 2.5V
Figure 21. Efficiency vs. Output Power into RL = 3 Ω + 33 μH
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
07550-022
OUTPUT POWER (W)
POWER DISSIPATION (W)
V
DD
= 5V
V
DD
= 3.6V
V
DD
= 2.5V
R
L
= 8Ω + 33µH
Figure 22. Power Dissipation vs. Output Power into RL = 8 Ω + 33 μH
0
0.05
0.10
0.15
0.20
0.25
0.30
0 0.5 1.0 1.5 2.0 2.5 3.0
07550-023
OUTPUT POWER (W)
POWER DISSIPATION (W)
V
DD
= 5V
V
DD
= 2.5V
V
DD
= 3.6V
R
L
= 4Ω + 33µH
Figure 23. Power Dissipation vs. Output Power into RL = 4 Ω + 33 μH
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0 0.5 1.0 1.5 2.0 2.5 3.53.0
07550-024
OUTPUT POWER (W)
POWER DISSIPATION (W)
V
DD
= 5V
V
DD
= 2.5V
V
DD
= 3.6V
R
L
= 3Ω + 33µH
Figure 24. Power Dissipation vs. Output Power into RL = 3 Ω + 33 μH
0
50
100
150
200
250
300
350
400
450
0 0.5 1.0 1.5 2.0 2.5
07550-025
OUTPUT POWER (W)
SUPPLY CURRENT (mA)
V
DD
= 5V
V
DD
= 2.5V
V
DD
= 3.6V
R
L
= 8Ω + 33µH
Figure 25. Supply Current vs. Output Power into RL = 8 Ω + 33 μH
0
100
200
300
400
500
600
700
800
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
07550-026
OUTPUT POWER (W)
SUPPLY CURRENT (mA)
V
DD
= 5V
V
DD
= 2.5V
V
DD
= 3.6V
R
L
= 4Ω + 33µH
Figure 26. Supply Current vs. Output Power into RL = 4 Ω + 33 μH
SSM2319
Rev. 0 | Page 11 of 20
0
100
200
300
400
500
600
700
900
800
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
7550-027
OUTPUT POWER (W)
SUPPLY CURRENT (mA)
V
DD
= 5V
V
DD
= 2.5V
V
DD
= 3.6V
R
L
= 3Ω + 33µH
–10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
OUTPUT
–2
–1
0
1
2
3
4
5
6
7
0
7550-030
TIME (ms)
VOLTAGE (V)
SD INPUT
Figure 27. Supply Current vs. Output Power into RL = 3 Ω + 33 μH
Figure 30. Turn-On Response
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k
07550-028
FREQUENCY (Hz)
PSRR (dB)
–2
–1
0
1
2
3
4
5
6
7
–100 –80 –60 –40 –20 0 20 40 60 80 100
07550-031
TIME (µs)
VOLTAGE (V)
OUTPUT
SD INPUT
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 31. Turn-Off Response
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k
07550-029
FREQUENCY (Hz)
CMRR (dB)
Figure 29. Common-Mode Rejection Ratio (CMRR) vs. Frequency
SSM2319
Rev. 0 | Page 12 of 20
TYPICAL APPLICATION CIRCUITS
0.1µF VBATT
2.5V TO 5.5V
10µF
EXTERNAL GAIN SETTINGS = 160kΩ/(40kΩ +
R
EXT
)
0.1µF*
0.1µF*
AUDIO IN+
AUDIO IN–
R
EXT
R
EXT
07550-032
SHUTDOWN
VDD
POP/CLICK
SUPPRESSION
OUT+
OUT–
IN–
IN+
MODULATOR
(Σ-Δ)
GND
SYNC OUTPUT
*INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
SD
SSM2319
40kΩ
160kΩ
160kΩ
40kΩ
FET
DRIVER
BIAS INTERNAL
OSCILLATOR
SYNCI
SYNCO
SYNC INPUT
SYNC
Figure 32. Differential Input Configuration, User-Adjustable Gain
0.1µF VBATT
2.5V TO 5.5V
10µF
EXTERNAL GAIN SETTINGS = 160kΩ/(40kΩ +
R
EXT
)
0.1µF
0.1µF
AUDIO IN+
R
EXT
R
EXT
07550-033
SHUTDOWN
VDD
POP/CLICK
SUPPRESSION
OUT+
OUT–
IN–
IN+
MODULATOR
(Σ-Δ)
GND SYNCI
SYNCO
SYNC INPUT
SYNC OUTPUT
SD
SSM2319
40kΩ
160kΩ
160kΩ
40kΩ
FET
DRIVER
BIAS
SYNC
INTERNAL
OSCILLATOR
Figure 33. Single-Ended Input Configuration, User-Adjustable Gain
SSM2319
Rev. 0 | Page 13 of 20
07550-035
OUT+
STANDALONE MASTER SLAVE
OUT–
MODULATOR
(Σ-Δ)
SYNCI
SYNCO
SYNC
INPUT
SYNC
OUTPUT
SSM2319
FET
DRIVER
SYNC
INTERNAL
OSCILLATOR
OUT+
OUT–
MODULATOR
(Σ-Δ)
SYNCI
TO SLAVE
NOTES
1. TRACE LENGTH FROM SYNCI TO SYNCO IS LESS THAN 1mm.
SYNCO
SYNC
INPUT
SYNC
OUTPUT
SSM2319
FET
DRIVER
SYNC
INTERNAL
OSCILLATOR
OUT+
OUT–
MODULATOR
(Σ-Δ)
SYNCI
FROM MASTER
SYNCO
SYNC
INPUT
SYNC
OUTPUT
SSM2319
FET
DRIVER
SYNC
INTERNAL
OSCILLATOR
Figure 34. Synchronization Operation Modes
07550-036
OUT+
SLAVE 1MASTER SLAVE 2
OUT–
MODULATOR
(Σ-Δ)
SYNCI
SYNCO
SYNC
INPUT
SYNC
OUTPUT
SSM2319
FET
DRIVER
SYNC
INTERNAL
OSCILLATOR
OUT+
OUT–
MODULATOR
(Σ-Δ)
SYNCI
SYNCO
SYNC
INPUT
SYNC
OUTPUT
SSM2319
FET
DRIVER
SYNC
INTERNAL
OSCILLATOR
OUT+
OUT–
MODULATOR
(Σ-Δ)
SYNCI
SYNCO
SYNC
INPUT
SYNC
OUTPUT
SSM2319
FET
DRIVER
SYNC
INTERNAL
OSCILLATOR
Figure 35. Typical SYNC Master-Slave Daisy-Chain Configuration
SSM2319
Rev. 0 | Page 14 of 20
THEORY OF OPERATION
OVERVIEW OUTPUT MODULATION DESCRIPTION
The SSM2319 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count, conserving board space and, thus, reducing systems cost.
The SSM2319 does not require an output filter. Instead, it relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square wave output. Most Class-D amplifiers
use some variation of pulse-width modulation (PWM), but the
SSM2319 uses a Σ-Δ modulation to determine the switching
pattern of the output devices, resulting in a number of important
benefits. Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width modulators
often do. Σ-Δ modulation reduces the amplitude of spectral
components at high frequencies, reducing EMI emission that
may otherwise be radiated by speakers and long cable traces.
Due to the inherent spread-spectrum nature of Σ-Δ
modulation, the need for oscillator synchronization is eliminated
for designs incorporating multiple SSM2319 amplifiers.
The SSM2319 uses 3-level Σ-Δ output modulation. Each output
is able to swing from GND to VDD and vice versa. Ideally, when
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present. Due to the
constant presence of noise, a differential pulse is generated
in response to this stimulus. A small amount of current flows
into the inductive load when the differential pulse is generated.
However, most of the time, the output differential voltage is 0 V,
due to the Analog Devices, Inc., patented 3-level, Σ-Δ output
modulation feature. This feature ensures that the current flowing
through the inductive load is small.
When the user wants to send an input signal, an output pulse is
generated to follow the input voltage. The differential pulse density
is increased by raising the input signal level. Figure 36 depicts
3-level Σ-Δ output modulation with and without input stimulus.
OUTPUT > 0V
+5V
0V
OUT+
+5V
0V
OUT–
+5V
0V
VOUT
OUTPUT < 0V
+5V
0V
OUT+
+5V
0V
OUT–
0V
–5V
VOUT
OUTPUT = 0V
OUT+
+5V
0V
+5V
0V
OUT–
+5V
–5V
0V
VOUT
07550-034
The SSM2319 also offers protection circuits for overcurrent and
temperature protection.
GAIN
The SSM2319 has a default gain of 12 dB that can be reduced by
using a pair of external resistors with a value calculated as follows:
External Gain Settings = 160 kΩ/(40 kΩ + REXT)
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of the audio amplifiers can occur
when shutdown is activated or deactivated. Voltage transients as
low as 10 mV can be heard as an audio pop in the speaker. Clicks
and pops can also be classified as undesirable audible transients
generated by the amplifier system and, therefore, as not coming
from the system input signal. Such transients can be generated
when the amplifier system changes its operating mode. For
example, audible transient sources include system power-up/
power-down, mute/unmute, an input source change, and a sample
rate change. The SSM2319 has a pop-and-click suppression
architecture that reduces these output transients, resulting in
noiseless activation and deactivation.
Figure 36. 3-Level Σ-Δ Output Modulation With and Without Input Stimulus
SSM2319
Rev. 0 | Page 15 of 20
LAYOUT
As output power continues to increase, care must be taken to
lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Ensure that track widths are at least 200 mil for every inch of
track length for lowest DCR and use 1 oz or 2 oz of copper PCB
traces to further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs
to minimize losses due to parasitic trace resistance.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching noise
from coupling into the audio signal. To maintain high output swing
and high peak output power, the PCB traces that connect the
output pins to the load and to the supply pins should be as wide
as possible to maintain the minimum trace resistances. It is also
recommended that a large ground plane be used for minimum
impedances.
In addition, good PCB layouts isolate critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more
when compared with double-sided boards. A multilayer board
allows a complete layer to be used for the ground plane, whereas
the ground plane side of a double-sided board is often disrupted
by signal crossover.
If the system has separate analog and digital ground and power
planes, the analog ground plane should be underneath the analog
power plane, and, similarly, the digital ground plane should be
underneath the digital power plane. There should be no overlap
between analog and digital ground planes or analog and digital
power planes.
INPUT CAPACITOR SELECTION
The SSM2319 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recom-
mended input dc common-mode voltage range, if high-pass
filtering is needed, or if using a single-ended source. If high-
pass filtering is needed at the input, the input capacitor, along
with the input resistor of the SSM2319, form a high-pass filter
whose corner frequency is determined by
fC = 1/{2π × (40 kΩ + REXT) × CIN}
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the PSRR performance.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low THD, and high PSRR, proper
power supply decoupling is necessary. Noise transients on the
power supply lines are short-duration voltage spikes. Although
the actual switching frequency can range from 10 kHz to 100 kHz,
these spikes can contain frequency components that extend into
the hundreds of megahertz. The power supply input needs to be
decoupled with a good quality, low ESL, low ESR capacitor, usually
of around 4.7 μF. This capacitor bypasses low frequency noises
to the ground plane. For high frequency transients noises, use a
0.1 μF capacitor as close as possible to the VDD pin of the device.
Placing the decoupling capacitor as close as possible to the
SSM2319 helps to maintain efficient performance.
SYNCRONIZATION (SYNC) OPERATION
SYNC is the feature that allows an external clock signal to control
the modulator of the SSM2319. The SSM2319 can act in standalone
mode, act as a master device, or act as a slave device. Although
the inherent random switching frequency of the Analog Devices
patented 3-level PDM modulation virtually eliminates the need for
SYNC, this feature can be activated in the event that end users are
concerned about clock intermodulation (beating effect) of several
amplifiers in close proximity.
Another use for the SYNC feature is its ability to adjust modulator
frequency to move harmonic interference to a less sensitive
frequency band in certain applications with very delicate
interference requirements.
Although the synchronization frequency operates from 5 MHz to
12 MHz, the optimal operating range is 6 MHz to 9 MHz.
Modulator synchronization is initiated after the internal shut-
down signal is released. SYNCO buffers the internal oscillator
clock with a delay of 127 clock cycles.
When synchronizing several SSM2319 amplifiers, configure
them in a daisy-chain configuration, as shown in Figure 35.
Using this configuration causes a small delay in the SYNCO-to-
SYNCO transitions of multiple SSM2319s, preventing large
surges of instantaneous current and reducing excessive loading
of the power supply.
When configuring one device to act as a master device, it is
mandatory that the connection from SYNCO to SYCNI be less
than 1 mm. As in many digital systems, to maintain signal integrity
when interfacing several clocking systems, users must insert series
dumping resistors close to the SYNCO pin if long trace lengths
are used for synchronization connections. A typical value used
is 750 Ω. The series dumping resistor should be placed as close
to the SYNCO pin as possible. If careful layout practices are
followed to minimize signal trace routing from the SYNCO pin
of one device to the SYNCI pin of another, a dumping resistor is
not necessary. If the SYNC feature is not used, or if the SYNC
feature is not interfacing the SYNCO pin to an external device,
it is recommended that the SYNCO pin be floated.
SSM2319
Rev. 0 | Page 16 of 20
Operating Modes • SYNCI = external clock. SYNCO is a buffered clock output
sourced from an external clock signal. One clock cycle after
the internal modulator detect signal is released, an irregular
pulse appears on MCLK before the first buffered output signal
begins on SYNCO, as shown in Figure 39.
The SYNC operating modes include the following:
• Initial SYNC startup. An internal reference signal, REF, is
released after one complete internal clock cycle (MCLK).
After REF is released, another internal signal, MOD, waits
127 internal clock cycles. This operates as a training signal
to determine the SYNCI/SYNCO connection. During this
time, SYNCO is the internal clock signal.
07550-039
SD
REF
MOD
SYNCI
SYNCO
MCLK
INTERNAL
SIGNAL
SYNCI = CLKIN
• SYNCI = GND or VDD. SYNCO stops generating pulses.
The modulator is controlled by an internal clock signal, as
shown in Figure 37.
07550-037
SD
REF
MOD
SYNCI
SYNCO
MCLK
INTERNA
L
SIGNAL
SYNCI = GND
Figure 39. SYNCI = External Clock
• SYNCI = GND, transitions to clock. When the SYNCI pin is
connected to GND first but then transitions to a clock signal,
SYNCO generates several internal clock signals before finally
being synchronized to the external clock signal, as shown
in Figure 40.
07550-040
SD
REF
MOD
SYNCI
SYNCO
MCLK
INTERNA
L
SIGNAL
SYNCI = GND TO CLKIN
Figure 37. SYNCI = GND or VDD
• SYNCI = SYNCO. SYNCO is the delayed clock signal of
SYNCI, as shown in Figure 38.
07550-038
SD
REF
MOD
SYNCI
SYNCO
MCLK
INTERNAL
SIGNAL
SYNCI = SYNCO
Figure 40. SYNCI = GND to Clock Input
• SYNCI = CLK, transitions to GND. When SYNCI is
connected to a clock signal but then transitions to GND,
the SYNCO pin immediately stops generating a clock signal.
After a short clock loss detect time, the internal modulator
synchronizes to the internal clock signal, as shown
in Figure 41.
Figure 38. SYNCI = SYNCO
07550-041
SD
REF
MOD
SYNCI
SYNCO
MCLK
INTERNAL
SIGNAL
SYNCI = CLKIN TO GND
CLK LOSS
DETECT
Figure 41. SYNCI = Clock Input to GND
SSM2319
Rev. 0 | Page 17 of 20
OUTLINE DIMENSIONS
101507-C
1.490
1.460 SQ
1.430
0.350
0.320
0.290
0.655
0.600
0.545
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
A
123
B
C
0.270
0.240
0.210
0.385
0.360
0.335
A1 BALL
CORNER SEATING
PLANE
0.50
BALL PITCH
Figure 42. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
SSM2319CBZ-R21−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
SSM2319CBZ-REEL1
−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
SSM2319CBZ-REEL71
−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
EVAL-SSM2319Z1
Evaluation Board
1 Z = RoHS Compliant Part.
SSM2319
Rev. 0 | Page 18 of 20
NOTES
SSM2319
Rev. 0 | Page 19 of 20
NOTES
SSM2319
Rev. 0 | Page 20 of 20
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07550-0-8/08(0)
