3
QS52807/A
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = -40°C to +85°C, VCC = 5.0V ± 10%, VHC = VCC - 0.2V, VLC = 0.2V
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Guaranteed Logic HIGH for All Inputs 2 — — V
VIL Input LOW Voltage Guaranteed Logic LOW for All Inputs — — 0.8 V
VIC Clamp Diode Voltage (3) Vcc = Min., IIN = -18mA — –0.7 –1.2 V
VOH Output HIGH Voltage Vcc = Min., VIN = VIH or VIL, IOH = -12mA 3.6 4.3 — V
Vcc = Min., VIN = VIH or VIL, IOH = -24mA 2.4 — —
VOL Output LOW Voltage Vcc = Min., VIN = VIH or VIL, IOL = 12mA — — 0.5 V
IIN Input Leakage Current Vcc = Max., VIN = VCC or GND — — ±1 µA
IOFF Input Power Off Leakage Vcc = 0V, VIN = VCC or GND — — ±1 µA
IOS Short Circuit Current (2,3) Vcc = Max., VOUT = GND –60 ——mA
∆VTInput Hysteresis VTLH - VTHL for All Inputs — 0.2 — V
ROUT Output Resistance (4) Vcc = Min., IOL = 12mA — 28 — Ω
NOTES:
1. Typical values are at VCC = 5. 0V, TA = 25° C.
2. Not m ore than one output should be used t o test this high power cond i t i on. Duratio n i s less t han one second.
3. Guaranteed by design but no t test ed.
4. Output resi s tance represents t he total output i m pedance of the logic devic e and i ncludes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Typ. Max. Unit
ICC Quiescent Power Supply Current VCC = Max., VIN = GND or Vcc 0.005 0.5 mA
∆ICC Supply Current per Input HIGH VCC = Max., VIN = 3.4V
Input toggling at 50% duty cycle 0.5 2.5 mA
ICCD Dynamic Power Supply Current per Output (1) VCC = Max., outputs Enabled 0.12 0.2 mA/MHz
ICTotal Power Supply Current Examples (2) VCC = Max.,
Input at 50% duty cycle VIN = GND or Vcc 12 21 mA
fI = 10MHz VIN = GND or 3V 12 2.2
VCC = Max.,
Input at 50% duty cycle VIN = GND or Vcc 3 6
fI = 2.5MHz VIN = GND or 3V 3.5 7
NOTES:
1. Guaranteed by design but not tested. CL = 0pF.
2. IC = ICC + (∆ICC)(DH)(NT) + ICCD (fO)(NO)
where:
DH = Input Duty Cycle
NT = Number of TTL HIGH inputs at DH
fO = Output Frequency
NO = Number of out puts at fO