Lattice ispLSI 2032E Fe aor contec tor In-System Programmable SuperFAST High Density PLD eee + SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 1000 PLD Gates 32 1/0 Pins, Two Dedicated Inputs 32 Registers High Speed Giobal Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Smail Logic Block Size for Random Logic 100% Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices + HIGH PERFORMANCE E?CMOS* TECHNOLOGY fmax = 200 MHz Maximum Operating Frequency tpd = 3.5 ns Propagation Delay TTL Compatible Inputs and Outputs ~~ 5V Programmable Logic Core ispJTAG In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port User-Selectable 3.3V or 5V 1/O (48-Pin Package Only) oO Supports Mixed Voltage Systems o 5V Tolerant /O When 3.3V I/O Selected memes PCI Compatible Outputs (48-Pin Package Only) ar Open-Drain Output Option - Electrically Erasable and Reprogrammable Global Routing Poo: (GRP) . Logic GLB Array Fy Output Routing Pool (ORP) Non-Voiatile The ispLS! 2032E is a High Density Programmabie Logic Unused Product Term Shutdown Saves Power Device. The device contains 32 Registers, 32 Universal ispLS| OFFERS THE FOLLOWING ADDED FEATURES oe an ne ane np Gs: lore peaieate Increased Manufacturing Yields, Reduced Time-to- OCK Input Fins, one dedicated Global Vr Input pin an Market and Improved Product Quality a Global Routing Pool (GRP). The GRP provides com- Reprogram Soldered Devices for Faster Prototyping plete interconnectivity between all of these elements. : OFFERS THE EASE OF USE AND FAST SYSTEM The ispLSi 2032E features ov in-system programmabil- SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY ity and in-system diagnostic capabilities. The ispLS! OF FIELD PROGRAMMABLE GATE ARRAYS 2032E offers non-volatile reprogrammability of the logic. Complete Programmable Device Can Combine Glue _as well as the interconnect to provide truly reconfigurable Logic and Structured Designs systems. Enhanced Pin Locking Capability _ Three Dedicated Clock Input Pins The basic unit of logic on the ispLS! 2032E device is the Synchronous and Asynchronous Clocks Generic Logic Block (GLB). The GLBs are labeled AO. At Programmable Output Slew Rate Control to .. A7 (see Figure 1). There are a total of eight GLBs in the Minimize Switching Noise ispLSI 2032E device. Each GLB is made up of four Flexibie Pin Placement macrocells. Each GLB has 18 inputs, a programmabie Optimized Giobal Routing Pool Provides Global AND/OR/Exclusive OR array, and four outputs which can interconnectivity be configured to be either combinatorial or registered. : ispEXPERT LOGIC COMPILER AND COMPLETE inputs to the GLB come from the GRP and dedicated ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS = inputs. All of the GLB outputs are brought back into the THROUGH IN-SYSTEM PROGRAMMING GRP so that they can be connected to the inputs of any - Superior Quality of Results GLB on the device. Tightly integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER PC and UNIX Platforms Copyright 1998 Lattice Semiconductor Corn All brand or product names are trademarks or registered trademarks ofiheirrespective holders The specifications and informaticn herein are subject to change without notice. November 1998 LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; hitp:/Awww.latticesemi.corm: 47 The device also has 32 1/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individuallyseas Semiconductor anee Corporation Specifications ispLS! 2032E Functional Block Diagram Figure 1. ispLSI 2032E Functional Block Diagram GOE 0 208 LOB uO 10 von input Bus WO 12 wad 24) 44 vO1S) Beg Global Routing Foot iGRP) a] | voas VOR 4028 WO 28 HG 2? WO 26 HO 26 bO 25 WO2s wO 22 WO 24 O20 Output Routing Pool {ORP) it Bus yo te yO 18 uO 17 wats TOVIN G TOON 4 mS BSTAN Notes. {ang RESET are mutticiexed on the same pin programmed to be a combinatorial input, output or bi- directional 1/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be pro- grammed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pins to a common 5V or 3.3V power supply, 1/O output levels can be matched to 5V or 3.3V compat- ible voltages. When connected to a 5V supply, the 1/O pins provide PCl-compatible output drive (48-pin device only). Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to aset of 32 universal |/O cells by the ORP. EachispLSI 2032E device contains one Megablock. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O ceils. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLS!| 2032E device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1. Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2032E are individually program- mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external joading and puil-up. This output configuration is controlled by a pro- grammable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispEXPERT software tools. 48Lattice Specifications ispLS! 2032E aeae Corporation External Timing Parameters Over Recommended Operating Conditions PARAMETER | Coan: | # DESCRIPTION sain Ia as Wan UNITS tpa1 A 1 | Data Propagation Delay, 4PT Bypass, ORP Bypass ~ 3.5 - 5.0 ns! tpd2 A 2 | Data Propagation Delay ~ | 55 ~ | 75 ns fmax A 3 | Clock Frequency with Internal Feedback? 200); ~ | 180] - MHz | fax (Ext.} - 4 | Clock Frequency with External Feeclback Gasven) 167 | ~ | 125) MHz fmax (Tog.) - 5 | Clock Frequency, Max. Toggle 250! - | 200} | MHz tsui - 6 | GLB Register Setup Time before Clock, 4 PT Bypass 2.5 - |30; - ns tco1 A 7 | GLB Register Clock ta Output Delay, ORP Bypass ~ | 25 ~ 40 ns thi - 8 | GLB Register Hold Time after Clock, 4 PT Bypass 0.0 - 0.0; - ns tsu2 - 9 | GLB Register Setup Time before Clock 3.5 ~ 4.0 - ns tco2 ~ 10! GLB Register Clock to Output Delay ~ | 3.5 - | 45 ns | the __~__| 11} GLB Register Hold Time after Clock 00) ~ | 00; - i ns: tri A | 12 | &xternal Reset Pin to Output Delay ~ | 50!) - | 70: ns tw ~ 13 | External Reset Pulse Duration 35} - | 40) - ns tptoeen B | 14/ Input to Output Enable ~ | 7.0: ~ 110.0! ns tptoedis Cc 15 | Input to Output Disable a ~ 7.0: - | 10.0 ns | tgoeen B 16 | Global OE Output Enable ~ {35} - | 50 ns tgoedis C | 17| Global OE Output Disable ~ 135) - 150] ns | twh - 18 | External Synchronous Clock Flulse Duration, High : 20 - 255 = ns tw - 19 | External Synchronous Clock Pulse Duration, Low 20] - | 26 : - ns . Unless noted otherwise, ali parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and YO clock. Table 2-0030A/20326 . Refer to Timing Model in this data sheet for further details . Standard 16-bit counter using GRP feedback. . Reference Switching Test Conditions section. -FOoOnM 49alice Specifications ispLS!I 2032E rh = Corporation Externai Timing Parameters Over Recommended Operating Conditions PARAMETER conb! # DESCRIPTION' ; ea oan TWX UNITS | tod1 A 1 | Data Propagation Delay, 4PT Bypass, ORP Bypass Doe | 7S 4 ~ | 10.0 ns tpd2 A 2 | Data Propagation Delay oe 4100) ~ 113.0] ns i fmax A 3 | Clock Frequency with Internal Feedbacks - 137 i 4att ~ MHz : fmax (Ext.) ~ 4 | Clock Frequency with External Feedback (seam) : ~ 400 | 1770, MHz fmax (Tog.) - 5 | Clack Frequency, Max. Toggle 167 ~ 125. - MHz tsut 6 | GLB Register Setup Time before Ciock, 4 PT Bypass 40; ~ 5.5 L - ms! tco1 A 7 |GLB Register Clock to Output Delay, ORP Bypass _ 45) 55} ns | thi - 8 | GLB Register Hold Time after Clock, 4 PT Bypass (O00! - | Oa; ~ ns tsu2 ~ 9 | GLB Register Setup Time before Clock 5.5 755 =} ns - tco2 | 10 GLB Register Clock to Output Delay _ ~ 58!) - 65! ns the ~ | 41 GLB Register Hold Time after Clock _ 00, - |o0)- | ms. tri A 12 | External Reset Pin to Output Delay | 10.0 13.5; ns trwv1 ~ |13)xternal Reset Pulse Duration 50, - 165) - 1 ns | tptoeen B | 14|Inputto OutputEnable - [i20) - [445 ns tptoedis G | 15) Input to Output Disable - 11201 - 1145) ns , tgoeen 8 16 | Global OE Output Enable ON - 60! - 7.0 ns | tgoedis C 17 | Global OE Output Disable a ~ |60. - | 7.0 ns : twh > 18 | External Synchronous Clock Pulse Duration, High _ 3.0) - 40) - ns twi -- | 19 | External Synchronous Clock Pulse Duration, Low 3.0 | : ~ | 40 - ns 1, Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 FTXOR path, ORP and YG clock. Table 20030820826 2. Refer to Timing Model in this data sheet for further details 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. 50