LP3879MRX-1.2/NOPB - NATIONAL SEMICONDUCTOR

LP3879

www.ti.com

SNVS396B –MAY 2006–REVISED APRIL 2013

LP3879 Micropower 800mA Low Noise "Ceramic Stable" Voltage Regulator for Low

Voltage Applications

Check for Samples: LP3879

1FEATURES DESCRIPTION

The LP3879 is a 800 mA fixed-output voltage

2• Standard Output Voltage: 1.00V, 1.20V regulator designed to provide high performance and

• Custom Voltages Available from 1.0V to 1.2V low noise in applications requiring output voltages

(50 mV Increments) between 1.0V and 1.2V.

• Input Voltage: 2.5 to 6V Using an optimized VIP (Vertically Integrated PNP)

• 1% Initial Output Accuracy process, the LP3879 delivers superior performance:

• Designed for Use with Low ESR Ceramic Ground Pin Current: Typically 5.5 mA @ 800 mA

Capacitors load, and 200 µA @ 100 µA load.

• Very Low Output Noise Low Power Shutdown: The LP3879 draws less than

• Sense Option Improves Load Regulation 10 μA quiescent current when shutdown pin is pulled

• 8-Lead SO PowerPad and WSON Surface low.

Mount Packages Precision Output: Ensured output voltage accuracy

• <10 μA Quiescent Current in Shutdown is 1% at room temperature.

• Low Ground Pin Current at all Loads Low Noise: Broadband output noise is only 18 μV

• High Peak Current Capability (typical) with 10 nF bypass capacitor.

• Over-Temperature/Over-Current Protection

• -40°C to +125°C Junction Temperature Range

APPLICATIONS

• ASIC Power Supplies In:

– Desktops, Notebooks and Graphic Cards

– Set Top Boxes, Printers and Copiers

• DSP and FPGA Power Supplies

• SMPS Post-Regulator

• Medical Instrumentation

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

BYPASS

N/C

GROUND

INPUT

SENSE

OUTPUT

SHUTDOWN

GROUND

N/C

GND

BYPASS

N/C

GROUND

INPUT SENSE

OUTPUT

N/C

SHUTDOWN

1.23V

LP3879-X.X

*0.01 PF

(See App

Hints)

*4.7 PF

**S/D

*10 PF

OUTPUT

(Ceramic or

Tantalum

recommended)

N/C

(Ceramic

recommended)

N/C

LP3879

SNVS396B –MAY 2006–REVISED APRIL 2013

www.ti.com

Basic Application Circuit

*Capacitance values shown are minimum required to assure stability. Larger output capacitor provides improved

dynamic response. Output capacitor must meet ESR requirements (see Application Information).

**The Shutdown pin must be actively terminated (see Application Information). Tie to INPUT (Pin 4) if not used.

Connection Diagram

Figure 1. Top View Figure 2. Top View

8-Lead SO PowerPad 8-Lead WSON

See DDA0008B Package See NGT0008A Package

PIN DESCRIPTIONS

Pin Name Function

1 BYPASS The capacitor connected between BYPASS and GROUND lowers output noise voltage

level and is required for loop stability.

2 N/C DO NOT CONNECT. This pin is used for post package test and must be left floating.

3 GROUND Device ground.

4 INPUT Input source voltage.

5 OUTPUT Regulated output voltage.

6 SENSE Remote Sense. Tie directly to output or remotely at point of load for best regulation.

7 N/C No internal connection.

8 SHUTDOWN Output is enabled above turn-on threshold voltage. Pull down to turn off regulator output.

SO PowerPad, SUBSTRATE The exposed die attach pad should be connected to a thermal pad at ground potential. For

WSON GROUND additional information on using Texas Instruments' Non Pull Back WSON package, please

refer to WSON application note SNOA401

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LP3879

using: The value of θJ−Afor the WSON and SO PowerPad packages are specifically dependent on PCB trace area,

LP3879

www.ti.com

SNVS396B –MAY 2006–REVISED APRIL 2013

Absolute Maximum Ratings(1)(2)

Storage Temperature Range −65°C to +150°C

Operating Junction Temperature Range -40°C to +125°C

Lead Temperature (Soldering, 5 seconds) 260°C

ESD Rating(3) 2 kV

Shutdown Pin 1kV

Power Dissipation(4) Internally Limited

Input Supply Voltage (Survival) −0.3V to +16V

Input Supply Voltage (Typical Operating) 2.5V to +6V

SENSE Pin −0.3V to +6V

Output Voltage (Survival)(5) −0.3V to +6V

IOUT (Survival) Short Circuit Protected

Input-Output Voltage (Survival)(6) −0.3V to +16V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply

when operating the device outside of its rated operating conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 kΩresistor.

(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal

resistance, θJ−A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated

trace material, and the number of layers and thermal vias. If a four layer board is used with maximum vias from the IC center to the heat

dissipating copper layers, values of θJ−Awhich can be obtained are approximately 60°C/W for the SO PowerPad and 40°C/W for the

WSON package. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go

into thermal shutdown.

(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3879 output must be diode-clamped to

ground.

(6) The output PNP structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased. Forcing the output

above the input will turn on this diode and may induce a latch-up mode which can damage the part (see Application Hints).

Product Folder Links: LP3879

OUT

LP3879

SNVS396B –MAY 2006–REVISED APRIL 2013

www.ti.com

Electrical Characteristics

Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the temperature range of -40°C to

125°C. Limits are ensured through design, testing, or correlation. The limits are used to calculate the Average Outgoing

Quality Level (AOQL). Unless otherwise specified: VIN = 3.0V, VOUT = 1V, IL= 1 mA, COUT = 10 µF, CIN = 4.7 µF, VS/D = 2V,

CBYPASS = 10 nF.

Symbol Parameter Conditions Min(1) Typical(2) Max(1) Units

VO-1.0 1.00 1.0

Output Voltage Tolerance %Vnom

-2.0 2.0

1 mA ≤IL≤800 mA, 3.0V ≤VIN ≤6V 1.00

-3.0 3.0

0.014

Output Voltage Line 3.0V ≤VIN ≤6V 0.007 %/V

0.032

Regulation

IL= 800 mA, VOUT ≥VOUT(NOM) - 1% 2.5 3.1

Minimum Input Voltage IL= 800 mA, VOUT ≥VOUT(NOM) - 1%

VIN (min) Required To Maintain 2.5 2.8 V

0≤TJ≤125°C

Output Regulation IL= 750 mA, VOUT ≥VOUT(NOM) - 1% 2.5 3.0

IGND 250

IL= 100 µA 200 µA

275

Ground Pin Current IL= 200 mA 1.5 3.3 mA

8.5

IL= 800 mA 5.5 15

IO(PK) Peak Output Current VOUT ≥VOUT(NOM) −5% 1200 mA

IO(MAX) Short Circuit Current RL= 0 (Steady State) 1400

enOutput Noise Voltage BW = 100 Hz to 100 kHz 18 µV(RMS)

(RMS) CBYPASS = 10 nF

Ripple Rejection f = 1 kHz 60 dB

SHUTDOWN INPUT

VS/D VH= Output ON 1.4 1.6

S/D Input Voltage VL= Output OFF, IIN ≤10 µA 0.1 0.50 V

VOUT ≤10 mV, IIN ≤50 µA 0.6

IS/D VS/D = 0 0.02 −1

S/D Input Current µA

VS/D = 5V 5 15

(1) Limits are ensured through testing, statistical correlation, or design.

(2) Typical numbers reperesent the most likely norm for 25°C operation.

Product Folder Links: LP3879

100

RIPPLE REJECTION (dB)

10 100 1k 10k 100k

FREQUENCY (Hz)

1.202

1.200

1.201

-40 25

1.199

JUNCTION TEMPERATURE (ºC)

VOUT (V)

0 50 75 100 125

-25

1.198

VOUT = 1.2V

-50 -25 0 25 50 75 100 125

TEMPERATURE (oC)

VOUT (V)

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

-60 -40 -20 0 20 40 60 80 100 120 140

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

IGND (mA)

TEMPERATURE (°C)

IL = 800 mA

IL = 240 mA

IL = 1 mA

LP3879

www.ti.com

SNVS396B –MAY 2006–REVISED APRIL 2013

Typical Performance Characteristics

Unless otherwise specified: VIN = 3.3V, VOUT = 1V, IL= 1 mA, CIN = 4.7 µF, COUT = 10 µF, VS/D = 2V, CBYP = 10 nF, TJ= 25°C.

IGND vs Temperature Minimum VIN Over Temperature

Figure 3. Figure 4.

IGND vs ILoad VOUT vs Temperature

Figure 5. Figure 6.

VOUT vs Temperature Ripple Rejection

Figure 7. Figure 8.

Product Folder Links: LP3879

100

RIPPLE REJECTION (dB)

10 100 1k 10k 100k

FREQUENCY (Hz)

IL= 800 mA

LP3879

SNVS396B –MAY 2006–REVISED APRIL 2013

www.ti.com

Typical Performance Characteristics (continued)

Unless otherwise specified: VIN = 3.3V, VOUT = 1V, IL= 1 mA, CIN = 4.7 µF, COUT = 10 µF, VS/D = 2V, CBYP = 10 nF, TJ= 25°C.

Ripple Rejection Line Transient Response

Figure 9. Figure 10.

Line Transient Response Line Transient Response

Figure 11. Figure 12.

Line Transient Response Line Transient Response

Figure 13. Figure 14.

Product Folder Links: LP3879

0 0.5 1 1.5 2

VS/D

0.2

0.4

0.6

0.8

1.2

VOUT (V)

0oC

125oC

25oC

LP3879

www.ti.com

SNVS396B –MAY 2006–REVISED APRIL 2013

Typical Performance Characteristics (continued)

Unless otherwise specified: VIN = 3.3V, VOUT = 1V, IL= 1 mA, CIN = 4.7 µF, COUT = 10 µF, VS/D = 2V, CBYP = 10 nF, TJ= 25°C.

Line Transient Response Load Transient Response

Figure 15. Figure 16.

Load Transient Response Turn-On Characteristics

Figure 17. Figure 18.

Product Folder Links: LP3879

5416

Error

Amp

LP3879-X.X

BYPASS

N/C

GROUND

INPUT

SENSE OUTPUT

N/C

SHUTDOWN

1.23V

LP3879

SNVS396B –MAY 2006–REVISED APRIL 2013

www.ti.com

Block Diagram

APPLICATION INFORMATION

PACKAGE INFORMATION

The LP3879 is offered in the 8-lead SO PowerPad or WSON surface mount packages to allow for increased

power dissipation compared to the SO-8 and Mini SO-8.

EXTERNAL CAPACITORS

Like any low-dropout regulator, the LP3879 requires external capacitors for regulator stability. These capacitors

must be correctly selected for good performance.

INPUT CAPACITOR: A capacitor whose value is at least 4.7 µF (±20%) is required between the LP3879 input

and ground. A good quality X5R / X7R ceramic capacitor should be used.

Capacitor tolerance and temperature variation must be considered when selecting a capacitor (see Capacitor

Characteristics section) to assure the minimum requirement of input capacitance is met over all operating

conditions.

The input capacitor must be located not more than 0.5" from the input pin and returned to a clean analog ground.

Any good quality ceramic or tantalum capacitor may be used, assuming the minimum input capacitance

requirement is met.

OUTPUT CAPACITOR: The LP3879 requires a ceramic output capacitor whose size is at least 10 µF (±20%). A

good quality X5R / X7R ceramic capacitor should be used. Capacitance tolerance and temperature

characteristics must be considered when selecting an output capacitor.

The LP3879 is designed specifically to work with ceramic output capacitors, utilizing circuitry which allows the

regulator to be stable across the entire range of output current with an ultra low ESR output capacitor.

The output capacitor selected must meet the requirement for minimum amount of capacitance and also have an

ESR (equivalent series resistance) value which is within the stable range. A curve is provided which shows the

stable ESR range as a function of load current (see Figure 19).

Product Folder Links: LP3879

0200 400 600 800

LOAD CURRENT (mA)

0.1

0.2

0.3

0.4

ESR (:)

STABLE REGION

LP3879

www.ti.com

SNVS396B –MAY 2006–REVISED APRIL 2013

Figure 19. Stable Region For Output Capacitor ESR

Important: The output capacitor must maintain its ESR within the stable region over the full operating

temperature range of the application to assure stability.

The output capacitor ESR forms a zero which is required to add phase lead near the loop gain crossover

frequency, typically in the range of 50kHz to 200 kHz. The ESR at lower frequencies is of no importance. Some

capacitor manufacturers list ESR at low frequencies only, and some give a formula for Dissipation Factor which

can be used to calculate a value for a term referred to as ESR. However, since the DF formula is usually at a

much lower frequency than the range listed above, it will give an unrealistically high value. If good quality X5R or

X7R ceramic capacitors are used, the actual ESR in the 50 kHz to 200 kHz range will not exceed 25 milli Ohms.

If these are used as output capacitors for the LP3879, the regulator stability requirements are satisfied.

It is important to remember that capacitor tolerance and variation with temperature must be taken into

consideration when selecting an output capacitor so that the minimum required amount of output capacitance is

provided over the full operating temperature range. (See Capacitor Characteristics section).

The output capacitor must be located not more than 0.5" from the output pin and returned to a clean analog

ground.

NOISE BYPASS CAPACITOR: The 10 nF capacitor on the Bypass pin significantly reduces noise on the

regulator output and is required for loop stability. However, the capacitor is connected directly to a high-

impedance circuit in the bandgap reference.

Because this circuit has only a few microamperes flowing in it, any significant loading on this node will cause a

change in the regulated output voltage. For this reason, DC leakage current through the noise bypass capacitor

must never exceed 100 nA, and should be kept as low as possible for best output voltage accuracy.

The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic

capacitors with either NPO or COG dielectric typically have very low leakage. 10 nF polypropolene and

polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low

leakage current.

CAPACITOR CHARACTERISTICS

CERAMIC: The LP3879 was designed to work with ceramic capacitors on the output to take advantage of the

benefits they offer: for capacitance values in the 10 µF range, ceramics are the least expensive and also have

the lowest ESR values (which makes them best for eliminating high-frequency noise). The ESR of a typical 10 µF

ceramic capacitor is in the range of 5 mΩto 10 mΩ, which meets the ESR limits required for stability by the

LP3879.

One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Many large value

ceramic capacitors (≥2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in

the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.

Another significant problem with Z5U and Y5V dielectric devices is that the capacitance drops severely with

applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated

voltage applied to it.

Product Folder Links: LP3879

LP3879

SNVS396B –MAY 2006–REVISED APRIL 2013

www.ti.com

For these reasons, X7R and X5R type ceramic capacitors must be used on the input and output of the

LP3879.

SHUTDOWN INPUT OPERATION

The LP3879 is shut off by pulling the Shutdown input low, and turned on by pulling it high. If this feature is not to

be used, the Shutdown input should be tied to VIN to keep the regulator output on at all times.

To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and

below the specified turn-on/turn-off voltage thresholds listed in the Electrical Characteristics section under

VON/OFF.

REVERSE INPUT-OUTPUT VOLTAGE

The PNP power transistor used as the pass element in the LP3879 has an inherent diode connected between

the regulator output and input.

During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.

However, if the output is pulled above the input, this diode will turn ON and current will flow into the regulator

output.

In such cases, a parasitic SCR can latch which will allow a high current to flow into VIN (and out the ground pin),

which can damage the part.

In any application where the output may be pulled above the input, an external Schottky diode must be

connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP3879 to

0.3V (see Absolute Maximum Ratings).

Product Folder Links: LP3879

LP3879

www.ti.com

SNVS396B –MAY 2006–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision A (April 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 10

Product Folder Links: LP3879

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3879MR-1.0/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR -40 to 125 3879

MR1.0

LP3879MR-1.2 NRND SO PowerPAD DDA 8 95 Non-RoHS

& Green Call TI Call TI LP3879

MR1.2

LP3879MR-1.2/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LP3879

MR1.2

LP3879MRX-1.0/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 3879

MR1.0

LP3879MRX-1.2/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LP3879

MR1.2

LP3879SD-1.0/NOPB ACTIVE WSON NGT 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 79SD1.0

LP3879SD-1.2/NOPB ACTIVE WSON NGT 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 79SD1.2

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 2

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3879MRX-1.0/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LP3879MRX-1.2/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LP3879SD-1.0/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3879SD-1.2/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3879MRX-1.0/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LP3879MRX-1.2/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LP3879SD-1.0/NOPB WSON NGT 8 1000 210.0 185.0 35.0

LP3879SD-1.2/NOPB WSON NGT 8 1000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

6X 1.27

8X 0.51

0.31

3.81

TYP

0.25

0.10

0 - 8 0.15

0.00

2.71

2.11

3.4

2.8 0.25

GAGE PLANE

1.27

0.40

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MS-012.

PowerPAD is a trademark of Texas Instruments.

0.25 C A B

PIN 1 ID

AREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.400

EXPOSED

THERMAL PAD

TYP

6.2

5.8

1.7 MAX

NOTE 3

5.0

4.8

B4.0

3.8

www.ti.com

EXAMPLE BOARD LAYOUT

(5.4)

(1.3) TYP

( ) TYP

VIA

0.2

(R ) TYP0.05

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

8X (1.55)

8X (0.6)

6X (1.27)

(2.95)

NOTE 9

(4.9)

NOTE 9

(2.71)

(3.4)

SOLDER MASK

OPENING

(1.3)

TYP

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-8

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(R ) TYP0.05

8X (1.55)

8X (0.6)

6X (1.27)

(5.4)

(2.71)

(3.4)

BASED ON

0.125 THICK

STENCIL

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

SYMM

BASED ON

0.125 THICK

STENCIL

BY SOLDER MASK

METAL COVERED SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

www.ti.com

PACKAGE OUTLINE

8X 0.35

0.25

3 0.05

2.4

2.6 0.05

6X 0.8

0.8 MAX

0.05

0.00

8X 0.5

0.3

A4.1

3.9 B

4.1

3.9

(0.2) TYP

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

PIN 1 ID 0.1 C A B

0.05 C

THERMAL PAD

EXPOSED

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

8X (0.3)

(3)

(3.8)

6X (0.8)

(2.6)

( 0.2) VIA

TYP (1.05)

(1.25)

8X (0.6)

(R0.05) TYP

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SYMM 9

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED

METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(R0.05) TYP

(1.31)

(0.675)

8X (0.3)

8X (0.6)

(1.15)

(3.8)

(0.755)

6X (0.8)

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

METAL

TYP

SYMM 9

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