CS4353-DNZR - Cirrus Logic, Inc.

http://www.cirrus.com

Preliminary Product Information This document contains informatio n for a new product.

Cirrus Logic reserves the right to modify this product without notice.

3.3 V Stereo Audio DAC with 2 VRMS Line Output

Features

Multi-bit Delta-Sigma Modulator

106 dB A-wt Dynamic Range

-93 dB THD+N

Single-ended Ground Centered Analog

Architecture

– No DC-blocking Capacitors Required

– Integrated Step-up/Inverting Charge Pump

– Filtered Line-level Outputs

– Selectable 1 or 2 VRMS Full-scale Output

Low Clock-jitter Sensitivity

Low-latency Digital Filtering

Supports Sample Rates up to 192 kHz

24-bit Resolution

+3.3 V Charge Pump and Core Logic, +3.3 V

Analog, and +0.9 to 3.3 V Interface Power

Supplies

Low Power Consumption

24-pin QFN, Lead-free Assembly

Description

The CS4353 is a complete stereo digital-to- ana log sys-

tem including digital interpolation, fifth-order multi-bit

delta-sigma digital-to-analog conversion, digital de-em-

phasis, analog filtering, and on-chip 2 VRMS line-level

driver from a 3.3 V supply.

The advantages of this architecture include ideal differ-

ential linearity, no di stortion mechanisms due to resistor

matching errors, no linearity dr ift over time and tempe r-

ature, high toler ance to clock jitter, a nd a min imal se t of

external components.

The CS4353 is available in a 24-pin QFN package in

both Automotive (-40°C to +105°C) and Commercial

(-40°C to +85°C) grades. The CDB4353 Customer

Demonstration Board is al so available for de vice evalu-

ation and implementation suggestions. Please see

“Ordering Informatio n” on p age 26 for complete details.

These features are ideal for cost-sensitive, 2-channel

audio systems including video game consoles, DVD

players and recorders, A/V receivers, set-top boxes,

digital TVs, mini-component systems, and mixing

consoles.

PCM Serial

Audio Port

Level Shifter

Serial

Audio

Input Multibit

∆Σ Modulator

Interpolation

Filters

Digital Core Logic and

Charge Pump Supply (VCP)

+3.3 V

Left Channel

Right Channel

Hardware

Control

Power-On

Reset

Hardware

Control

Reset

Auto Speed

Mode Detect

Analog Supply (VA)

+3.3 V

Inverting

Step-Up +VA_H

-VA_H

Interface Supply (VL)

+0.9 V to +3.3 V

Ground-Centered,

2 Vrms Line Level Outputs

DAC Pseudo Diff. Input

DEC '08

DS803PP1

CS4353

2DS803PP1

CS4353

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ................ ... .... ................... .................................................... .............................. 4

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

RECOMMENDED OPERATING CONDITIONS .................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6

DAC ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) .............................................................. 7

DAC ANALOG CHARACTERI S TI CS (AUTO MO TIVE - DNZ) ................ .... ... ... ... .... ... ... ... .................... . 8

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 9

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ........................................................ 10

DIGITAL INTERFACE CHARACTERI STICS .................... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 11

INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 11

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 12

3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 13

4. APPLICATIONS ................................................................................................................................... 14

4.1.1 Ground-Centered Outputs ........ ................... .................... ... ................... .... ................... ... ...... 14

4.1.2 Full-Scale Output Amplit ud e Cont rol ............... ... ................ ... ... .... ... ... ... .... ... ......................... 14

4.1.3 Pseudo-Differential Ou tputs ........... .... ... ... ... .... ................................... ................................... 14

4.8.1 Power-Up Sequences .............. ... ... .... ... ... .................................... ......................................... 20

4.8.1.1 External RESET Power-Up Sequence ...................................................................... 20

4.8.1.2 Internal Power-On Reset Power-Up Sequence ......................................................... 20

4.8.2 Power-Down Sequences ....... ... ... ... .................................................... ................................... 20

4.8.2.1 External RESET Power-Down Sequence .................................................................. 20

4.8.2.2 Internal Power-On Reset Power-Down Sequence .................................................... 20

4.9.1 Capacitor Placement ............................................................................................................. 21

5. DIGITAL FILTER RESPONSE PLOTS................................................................................................. 22

6. PARAMETER DEFINITIONS ................................................................................................................ 24

7. PACKAGE DIMENSIONS .................................................................................................................... 25

8. ORDERING INFORMATION ................................................................................................................ 26

9. REVISION HISTORY ............................................................................................................................ 27

DS803PP1 3

CS4353

LIST OF FIGURES

Figure 1.Serial Input Timing ...................................................................................................................... 10

Figure 2.Power-On Reset Threshold Sequence ............. .... ... ... ... .... ... ...................................................... 11

Figure 3.Typical Connection Diagram ....................................................................................................... 13

Figure 4.Stereo Pseudo-Differential Output .............................................................................................. 14

Figure 5.I²S, up to 24-Bit Data .................................................................................................................. 16

Figure 6.Left-Justified up to 24-Bit Data .................................................................................................... 16

Figure 7.De-Emphasis Curve, Fs = 44.1 kHz ........................................................................................... 17

Figure 8.Internal Power-On Reset Circuit ................................................................................................. 17

Figure 9.Initialization and Power-Down Sequence Diagram ..................................................................... 19

Figure 10.Single-Speed Stopband Rejection ............................................................................................ 22

Figure 11.Single-Speed Transition Band .................................................................................................. 22

Figure 12.Single-Speed Transition Band (detail) ...................................................................................... 22

Figure 13.Single-Speed Passband Ripple ................................................................................................ 22

Figure 14.Double-Speed Stopband Rejection ........................................................................................... 22

Figure 15.Double-Speed Transition Band ................................................................................................. 22

Figure 16.Double-Speed Transition Band (detail) .................. ... ... .... ... ... ... .................... ... ......................... 23

Figure 17.Double-Speed Passband Ripple ............................................................................................... 23

Figure 18.Quad-Speed Stopband Rejection ............................................................................................. 23

Figure 19.Quad-Speed Transition Band ................................................................................................... 23

Figure 20.Quad-Speed Transition Band (detail) ....................................................................................... 23

Figure 21.Quad-Speed Passband Ripple .............. ... ... ... .... ... ... ... .................... ... ................... ................... 23

LIST OF TABLES

Table 1. Power-On Reset Threshold Voltages .......................................................................................... 11

Table 2. Digital I/O Pin Characteristics ........ ... ... .... ... ... ... .... ... ... ... .... ................... ... ................... . ............... 12

Table 3. CS4353 Operational Mode Auto-Detect ...................................................................................... 15

Table 4. Single-Speed Mode Standard Frequencies ................................................................................15

Table 5. Double-Speed Mode Standard Frequencies ............................................................................... 15

Table 6. Quad-Speed Mode Standard Frequencies .............. ... ... .... ... ... ... .................... ... ... ... ................... 15

Table 7. Digital Interface Format ............................................................................................................... 16

4DS803PP1

CS4353

1. PIN DESCRIPTIONS

Pin Name Pin # Pin Description

SCLK 1 Serial Clock (Input) - Serial clock for the serial audio interface.

MCLK 2 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filter s.

VL 3 Serial Audio Interface Power (Input) - Positive power for the serial audio interface

DGND 4 Digital Ground (Input) - Ground reference for the digital section.

FLYP+

FLYP- 7

5Step-Up Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the

step-up charge pump’s flying capacitor.

VCP 6 Charge Pump and Digital Core Logic Power (Input) - Positive power supply for the step-up and invert-

ing charge pumps as well as the digital core logic sections.

VFILT+ 8 Step-Up Charge Pump Filter Connection (Output) - Power supply from the step-up charge pump that

provides the positive rail for the ou tput amplifiers

FLYN+

FLYN- 9

11 Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the

inverting charge pump’s flying capacitor.

CPGND 10 Charge Pump Ground (Input) - Ground reference for the Charge Pump section.

VFILT- 12 Inverting Charge Pump Filter Con nection (Output) - Power supply from the inverting charge pump that

provides the negative rail for the output amplifie rs.

AOUTB

AOUTA 13

15 Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteris-

tics table.

AOUT_REF 14 Pseudo Diff. Analog Output Reference (Input) - Ground reference for the anal og output amplifiers.

This pin must be at the same nominal DC voltage as the AGND pin.

AGND 16 Analog Ground (Input) - Ground reference for the low voltage analog section.

910 11 12

2021222324

Top-Down (Through Package) View

24-Pin QFN Package

SDIN

LRCK

I²S/LJ

DEM

1_2VRMS

RESET

FLYP+

VFILT+

FLYN+

CPGND

FLYN-

SCLK

MCLK

DGND

FLYP-

VBIAS

AGND

AOUT_REF

AOUTB

Thermal Pad

VCP

VFILT-

AOUTA

DS803PP1 5

CS4353

VA 17 Low Voltage Analog Power (Input) - Positive power supply for the analog section.

VBIAS 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.

RESET 19 Reset (Input) - Optional connecti on for an exte rnal reset control. The device enters a powe r ed-down

state when this pin is set low (GND) OR when the VCP supply falls below the Voff threshold (see

Table 1). This pin shoul d be set high (VL) during normal operation.

1_2VRMS 20 1 or 2 VRMS Select (Input) - Selects the analog output full-scale voltage. Setting this pin low (GND)

selects 1 VRMS, while setting it high (VL) selects 2 VRMS.

DEM 21 De-emphasis (Input) - Selects the standard 50 µs/15 µs digital de-emphasis filter response for 44.1 kHz

sample rates when enabled.

I²S/LJ 22 Digital Interface Format (Input) - Selects the serial audio interface format. Setting this pin low (GN D)

selects I²S, while setting it high (VL) selects Left-Justified.

LRCK 23 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line.

SDIN 24 Serial Audio Da ta Input (Input) - Input for two’s complement serial audio data.

Thermal Pad - Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated

from all board connections.

6DS803PP1

CS4353

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

AGND = DNGD = CPGND = 0 V; all voltages with respect to ground.

Notes: 1. VCP and VA must be supplied with the same nominal voltage. Additional current draw will occur if the sup-

ply voltages applied to VCP and VA differ by more than 0.5 V.

ABSOLUTE MAXIMUM RATINGS

AGN D = D NG D = C P G ND = 0 V; all voltages with respect to ground.

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Parameters Symbol Min Typ Max Units

DC Power Supply Charge Pump and Digital Core power (Note 1)

Low Voltage Analog power (Note 1)

Interface power

VCP

3.13

0.85

3.3

0.9 to 3.3

3.47

Ambient Operating Temperature (Power Applied) -CNZ

-DNZ TA

-40

-40 -

-+85

+105 °C

°C

Parameters Symbol Min Max Units

DC Power Supply Charge Pump and Digital Core Logic Power

Low Voltage Analog Power

Supply Voltage Difference

Interface Power

VCP

|VCP - VA |

-0.3

3.63

0.5

3.63

Input Current, Any Pin Except Supplies Iin -±10mA

Digital Input Voltage Digital Interface VIN-L -0.3 VL+ 0.4 V

Analog Input Voltage AOUT_REF VIN-A -0.3 0.5 V

Ambient Operating Temperature (Power Applied) TA-55 +125 °C

Storage Temperature Tstg -65 +150 °C

DS803PP1 7

CS4353

DAC ANALOG CHARACTERISTICS (COMMERCIAL - CNZ)

Test conditions (unless otherwise specified): TA = 25 °C; VCP = VA = 3.3 V; AOUT_REF = AGND = DGND =

CPGND = 0 V; VBIAS, +/-VFILT, and FLYP/N+/- capacitors as shown in Figure 3 on page 13; input test signal is a

997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz.

Notes: 2. Measured between the AOUTx and AOUT_REF pins.

3. One-half LSB of triangula r PDF dither is added to data.

4. Me asur ed with th e specified minim um AC- Load Resista nce p resent on th e AOUTx pi ns. Addition al im-

pedance between the AOUTx pin and the load will lower the voltage delivered to the load.

5. VPP is the controlling specification. VRMS specification valid for sine wave signals only.

Note that for sine wave signals:

6. Measured with AOUT_REF connected directly to ground. Additional impedance between AOUT_REF

and ground will lower the AOUT_REF rejection.

7. SDIN = 0. AOUT_REF input test signal is a 60 Hz, 50 mVpp sine wave. Measured by applying the test

signal into the AOUT_REF pin and measuring the resulting output amplitude on the AOUTx pin. Spec-

ification calculated by:

1_2VRMS = 0 1_2VRMS = 1

Parameter Symbol Min Typ Max Min Typ Max Unit

Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 2, 3)

Dynamic Range 24-bit A-Weighted

unweighted

16-bit A-Weighted

unweighted

100

106

103

Total Harmonic Distortion + Noise

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

-20 dB

-60 dB

THD+N

-93

-77

-37

-93

-75

-29

-87

-71

-31

-93

-83

-43

-93

-75

-35

-87

-77

-37

Idle Channel Noise / Signal-to-Noise Ratio (A-wt) - 100 - - 106 - dB

Interchannel Isolation (1 kHz) - 115 - - 115 - dB

Analog Output (Note 2)

Full Scale AOUTx Output Voltage (Notes 4, 5) 0.981.051.121.962.102.25V

RMS

2.77 2.97 3.17 5.54 5.94 6.36 Vpp

Max Current Draw from an AOUTx Pin IOUTmax -575- -575- µA

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Output Offset - ±5 ±8 - ±5 ±8 mV

Gain Drift - 100 - - 100 - ppm/°C

Output Impedance ZOUT -100- -100- Ω

AC-Load Resistance RL5--5--kΩ

Load Capacitance CL- - 1000 - - 1000 pF

AOUT_REF Rejection (Notes 6, 7)AOR-40- -40-dB

Analog Reference Input

AOUT_REF Input Voltage (Note 8) --0.2--0.2Vpp

VRMS Vpp

----------

AORdB 20 log10 AOUT_REF

AOUT_REF AOUTx–

---------------------------------------------------------

⎝⎠

⎛⎞

⋅=

8DS803PP1

CS4353

DAC ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ)

Test conditions (unless otherwise specified): TA = -40 to +85 °C; VCP = VA = 3.13 V to 3.47 V; AOUT_REF =

AGND = DGND = CPGND = 0 V; VBIAS, +/-VFILT, and FLYP/N+/- capacitors as shown in Figure 3 on page 13;

input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz.

8. Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output. See Section

4.1.3 for more information.

1_2VRMS = 0 1_2VRMS = 1

Parameter Symbol Min Typ Max Min Typ Max Unit

Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 2, 3)

Dynamic Range 24-bit A-Weighted

unweighted

16-bit A-Weighted

unweighted

100

106

103

Total Harmonic Distortion + Noise

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

-20 dB

-60 dB

THD+N

-93

-77

-37

-93

-75

-29

-87

-71

-31

-93

-83

-43

-93

-75

-35

-87

-77

-37

Idle Channel Noise / Signal-to-Noi s e Ratio (A-wt) - 100 - - 106 - dB

Interchannel Isolation (1 kHz) - 115 - - 115 - dB

Analog Output (Note 2)

Full Scale AOUTx Output Voltage (Notes 4, 5) 0.98 1.05 1.12 1.96 2.10 2.25 VRMS

2.77 2.97 3.17 5.54 5.94 6.36 Vpp

Max Current Draw from an AOUTx Pin IOUTmax - 575 - - 575 - µA

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Output Offset - ±5 ±8 - ±5 ±8 mV

Gain Drift - 100 - - 100 - ppm/°C

Output Impedance ZOUT - 100 - - 100 - Ω

AC-Load Resistance RL5--5--kΩ

Load Capacitance CL- - 1000 - - 1000 pF

AOUT_REF Rejection (Notes 6, 7)AOR-40- -40-dB

Analog Reference Input

AOUT_REF Input V oltage (Note 8) --0.2--0.2Vpp

DS803PP1 9

CS4353

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desir ed sam-

ple rate by multiplying the given characteristic by Fs.

Notes: 9. Response is clock-dependent and will scale with Fs.

10. For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.

For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

11. De-emphasis is available only in Single-Speed Mode.

12. Amplitude vs. Frequency plots of this data are available in “Digital Filter Response Plots” on page 22.

Parameter Min Typ Max Unit

Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.454

.499 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand 0.547 - - Fs

StopBand Attenuation (Note 10) 102 - - dB

Total Group Delay (Fs = Sample Rate) - 9.4/Fs - s

Intra-channel Phase Deviation - - ±0.56/Fs s

Inter-channel Phase Deviation - - 0 s

De-emphasis Error (Note 11)(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB

Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.430

.499 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB

StopBand .583 - - Fs

StopBand Attenuation (Note 10) 80 - - dB

Total Group Delay (Fs = Sample Rate) - 4.6/Fs - s

Intra-channel Phase Deviation - - ±0.03/Fs s

Inter-channel Phase Deviation - - 0 s

Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.105

.490 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB

StopBand .635 - - Fs

StopBand Attenuation (Note 10) 90 - - dB

Total Group Delay (Fs = Sample Rate) - 4.7/Fs - s

10 DS803PP1

CS4353

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Parameters Symbol Min Max Units

MCLK Frequency 2.048 51.2 MHz

MCLK Duty Cycle 45 55 %

Input Sample Rate (Auto selection) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

170

108

216

kHz

LRCK Duty Cycle 40 60 %

SCLK Pulse Width Low tsclkl 20 - ns

SCLK Pulse Width High tsclkh 20 - ns

SCLK Period Single-Speed Mode - s

Double-Speed Mode - s

Quad-Speed Mode - s

SCLK rising to LRCK edge delay tslrd 20 - ns

SCLK rising to LRCK edge setup time tslrs 20 - ns

SDIN valid to SCLK rising setup time tsdlrs 20 - ns

SCLK rising to SDIN hold time tsdh 20 - ns

sclkh

slrs

slrd

sdlrs

sdh

sclkl

SDATA

SCLK

LRCK

Figure 1. Serial Inp ut Timing

128()Fs

----------------------

64()Fs

------------------

64()Fs

------------------

DS803PP1 11

CS4353

DIGITAL INTERFACE CHARACTERISTICS

Test conditions (unless otherwise specified): AGND = DGND = CPG ND = 0 V; all voltages with respect to ground.

INTERNAL POWER-ON RESET THRESHOLD VOLTAGES

Test conditions (unless otherwise specified): AGND = DGND = CPG ND = 0 V; all voltages with respect to ground.

Table 1. Power-On Reset Threshold Voltages

Figure 2. Power-On Reset Threshold Sequence

Parameters Symbol Min Typ Max Units

High-Level Input Voltage 1.2 V < VL ≤ 3.3 V

0.9 V ≤ VL ≤ 1.2 V VIH

VIH

0.7xVL

0.9xVL -

-V

Low-Level Input Voltage 1.2 V < VL ≤ 3.3 V

0.9 V ≤ VL ≤ 1.2 V VIL

VIL

-0.3xVL

0.1xVL V

Input Leakage Current Iin --±10µA

Input Capacitance - 8 - pF

Parameters Symbol Min Typ Max Units

Internal Reset Asserted at Power-On Von1 -1.00- V

Internal Reset Released at Power-On Von2 -2.14- V

Internal Reset Asserted at Power-Off Voff -2.00- V

VCP

Von2

Von1

Voff

DGND

No Power reset

undefined reset

active DAC

Ready reset

active

reset

(internal)

12 DS803PP1

CS4353

DC ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise specified): VCP = VA = VL = 3.3 V; A G N D = D GND = CP G ND = 0 V; SDIN = 0;

all voltages with respect to ground.

Notes: 13. Current consumption increases with increasing sample rate and increasing MCLK frequency. Typical

values are based on Fs = 48 kHz and MCLK = 12.288 MHz. Maximum values are based on highest

sample rate and highest MCLK frequency; see Switching Specifications - Serial Audio Interface. Vari-

ance between speed modes is small.

14. Power-down is defined as RESET pin = Low with all clock and data lines held static low. All digital inputs

have a weak pull-down (approximately 50 kΩ) which is only present during reset. Opposing this pull-

down will slightly increase the power-down current.

15. Valid with the recommended capacitor value on VBIAS as shown in the typical connection diagram in

Section 3.

16. Typical voltage shown for “Initialization State”, see Section 4.7. Typical voltage may be up to 1.5 V lower

during normal operation.

2.1 Digital I/O Pin Characteristics

Input and output levels and a ssociated power su pply voltag e are sho wn in Table 2. Logic levels should not

exceed the corresponding power supply voltage.

Table 2. Digital I/O Pin Characteristics

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current (Note 13) Normal Operation

Power-Down, All Supplies (Note 14)

IVCP

IVA

IVL

IPD

2.4

0.1

0.2

µA

Power Dissipation (All Supplies) Normal Operation, 1_2VRMS = 0

(Note 13) Power-Down (Note 14) -

-127

1152

-mW

Power Supply Rejection Ratio (Note 15) (1 kHz)

(60 Hz) PSRR -

-60

60 -

-dB

DC Output Voltages

Pin Voltage FLYP+ to FLYP-

VFILT+ to GND (Note 16)

FLYN+ to FLYN-

GND to VFILT- (Note 16)

VA to VBIAS

3.3

6.6

2.1

Pin Name Power Supply I/O Driver Receiver

RESET

Input - 0.9 V - 3.3 V, with Hysteresis

MCLK Input - 0.9 V - 3.3 V

LRCK Input - 0.9 V - 3.3 V

SCLK Input - 0.9 V - 3.3 V

SDIN Input - 0.9 V - 3.3 V

DEM Input - 0.9 V - 3.3 V

I²S/LJ Input - 0.9 V - 3.3 V

1_2VRMS Input - 0.9 V - 3.3 V

DS803PP1 13

CS4353

3. TYPICAL CONNECTION DIAGRAM

VL+0.9 V to +3.3 V

RESET

LRCK

MCLK

SCLK

AOUT_REF

SDIN

-VFILT

AOUTA

562 Ω

2.2 nF

Rext

Line Level Out

Left & Right

I²S/LJ

DEM

1_2VRMS

+VFILT

Digital Audio

Processor

Hardware

Control

Values shown are for

Fc = 130 kHz.

Capacitors must be

C0G or equivalent.

562 Ω

2.2 nF

AOUTB

VBIAS

FLYN-

FLYN+

0.1 µF

2.2 µF

FLYP-

FLYP+

2.2 µF

0.1 µF

+3.3 V

0.1 µF

VCP

Note 1:

CPGND

DGND

AGND

22 µF

2.2 µF

Note 1

10 416

176

Note 2

Note 2:Connect RESET

to VL if internal

power-on reset is

used.

CS4353

Figure 3. Typical Connection Diagra m

14 DS803PP1

CS4353

4. APPLICATIONS

4.1 Line Outputs

4.1.1 Ground-Centered Outputs

An on-chip char ge pum p creates bo th positiv e and negative high-voltage supplies, which allows the full-

scale output swing to be centered around ground . Th is elim inates the need for large DC- blocking capac-

itors which create audib le pops at power-on, allows the CS43 53 to deliver a larger full-scale output at low-

er supply voltages, and provides improved bandwidth frequency response.

4.1.2 Full-Scale Output Amplitude Control

The full-scale output voltage amplitude is selected via the 1_2VRMS pin. When the pin is connected to

VL, the full-scale output voltage at the AOUTx pins is approximately 2 VRMS. When the p in is conn ecte d

to GND, the full-scale output voltage at the AOUTx pins is approximately 1 VRMS. Additional impe dance

between the AOUTx pin and the load will lower the voltage delivered to the load. See the DAC Analog

Characteristics (Commercial - CNZ) or DAC Analog Characteristics (Automotive - DNZ) table for the com-

plete specifications of the full-scale output voltage.

4.1.3 Pseudo-Differential Outputs

The CS4353 implements a pseudo -differential output stage. The AOUT_REF input is intended to be used

as a pseudo-differential reference sign al. This feature provides common mode noise re jection with single-

ended signals. Figure 4 shows a basic diagram outlining the internal implementation o f the pseudo-differ -

ential output stage, including a recomme nded stereo pseudo-differential output topology. If pseudo-differ-

ential output functionality is not required, simply connect the AOUT_REF pin to ground next to the

CS4353. If a split-ground d esign is used, the AOUT_REF pin should be connected to AGND. See the Ab-

solute Maximum Ratings table for the maximum allowable voltage on the AOUT_REF pin. Applying a DC

voltage on the AOUT_REF pin will cause a DC offset on the DAC output.

Internal Left

DAC Signal

AOUTA

AOUT_REF //

// Left Output

GND

(pseudo-d ifferential traces)

AOUTB // Right Output

(pseudo-d ifferential traces)

Internal Right

DAC Signal Psuedo-differential output improves common

mode reje ction, reducing external syst em noise

Figure 4. Stereo Pseudo-Differential Output

DS803PP1 15

CS4353

4.2 Sample Rate Range/Operational Mode Detect

The CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when

the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in

Table 3. Sample rates outside the specified range for each mode are not supported. In addition to a valid

LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must a lso be applied to th e device

for speed mode auto-detection; see Figure 9.

Table 3. CS4353 Operational Mode Auto-Detect

4.3 System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.

The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the

MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-

dard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6.

Refer to Section 4.4 for th e required SCLK timing associa ted with th e selected Digital Interface For mat and

to “Switching Specifications - Serial Audio Interface” on page 10 for the maximum allowed clock frequen-

cies.

Table 4. Single-Speed Mode St andard Frequencies

Table 5. Double-Speed Mode Standard Freque ncies

Table 6. Quad-Speed Mode Standard Frequencies

Input Sample Rate (Fs) Mode

8 kHz - 54 kHz Single-Speed Mode

84 kHz - 108 kHz Double-Speed Mode

170 kHz - 216 kHz Quad-Speed Mode

Sample Rate

(kHz) MCLK (MHz)

256x 384x 512x 768x 1024x

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 33.8688 45.1584

48 12.2880 18.4320 24.5760 36.8640 49.1520

Sample Rate

(kHz) MCLK (MHz)

128x 192x 256x 384x 512x

88.2 11.2896 16.9344 22.5792 33.8688 45.1584

96 12.2880 18.4320 24.5760 36.8640 49.1520

Sample Rate

(kHz) MCLK (MHz)

128x 192x 256x

176.4 22.5792 33.8688 45.1584

192 24.5760 36.8640 49.1520

16 DS803PP1

CS4353

4.4 Digital Interface Format

The device will accept audio samples in either I²S or Left-Justified digital interface formats, as illustrated in

Table 7.

The desired format is selected via the I² S/LJ pin. For an illustration of the required relationship between the

LRCK, SCLK and SDIN, see Figures 5-6. For all formats, SDIN is valid on the rising edge of SCLK. Also,

SCLK must have at least 32 cycles per LRCK period in the Left-Justified format.

For more information about se rial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-

nel Serial Audio Interface: A Tutorial, available at http://www.cirrus.com.

Table 7. Digital Interface Format

Figure 5. I²S, up to 24-Bit Data

Figure 6. Left-Justified up to 24-Bit Data

I²S/LJ Description Figure

0I²S, up to 24-bit Data 5

1Left-Justified, up to 24-bit Data 6

LRCK

SCLK

Left Channel Right Channel

SDIN +3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB

LSB LSB

LRCK

SCLK

Left Channel Right Channel

SDIN +3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

LSB MSB LSB

DS803PP1 17

CS4353

4.5 De-Emphasis Control

The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to

44.1 kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs.

The de-emphasis error will increase for sample rates other than 44.1 kHz.

When the DEM pin is connected to VL, the 44.1 kHz de-emphasis filter is activated. When the DEM pin is

connected to GND, the de-emphasis filter is turne d off.

Note: De-emphasis is only available in Single-Speed Mode.

4.6 Internal Power-On Reset

The CS4353 features an internal power-on reset (POR) circuit. The POR circuit allows the RESET pin to be

connected to VL during power-up and power-down sequences if the external reset function is not needed.

This circuit monitors the VCP supply and automatically asserts or releases an internal reset of the DAC’s

digital circuitry when the supply reaches de fi ned th resholds ( see “Internal Power-On Reset Threshold Volt-

ages” on page 11). No external clocks are required for the POR circuit to function.

Figure 8. Internal Power-On Reset Circuit

When power is first applied, the POR circuit monitor s the VCP supply voltag e to determine when it r eaches

a defined threshold, Von1. At this time, the POR circuit asserts the internal reset low, resetting all of the

digital circuitry. Once the VCP supply reaches the secondary threshold, Von2, the POR circuit releases the

internal reset.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 k Hz 10 .61 kHz

Figure 7. De-Emphasis Curve, Fs = 44.1 kHz

RESET

(external)

Po wer-On Rese t

Circuit

VCP

DGND

reset

(internal)

18 DS803PP1

CS4353

Note: For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-

neously with VCP.

When power is remove d and the VCP voltage rea ches a defined th reshold, Voff, the POR circuit asserts the

internal reset low, resetting all of th e dig ita l circu itry .

4.7 Initialization

When power is first applied, the DA C enters a reset (low power) state at the beginning of the initialization

sequence. In this state, the AOUTx pins are weakly pulled to ground and VBIAS is connected to VA.

The device will remain in the reset state until the RESET pin is brought high. Once the RESET pin is high,

the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Alterna-

tively, if no external reset control is required, the internal power-on reset can be used by tying the RESET

pin to VL (see Section 4.6).

Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg-

es the capacitors for both the positive and negative high-voltage supplies.

Once LRCK and SCLK are va lid, the number o f MCL K cycles is counted r elative to th e LRCK p eri od to d e-

termine the MCLK/LRCK frequency rati o. Next, the device enters the power-up state in which the interpo-

lation and decimation filters and delta-sigma modulators are turned on, the internal voltage reference,

VBIAS, powers up to normal operation, the analog output pull-down resistors are removed, and power is

applied to the output amplifiers.

After this power-up state sequence is complete, normal operation begins and analog output is generated.

If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time f rom RE-

SET being set high to the analog audio output from AOUTx is less than 50 ms.

See Figure 9 for a diagram of the device’s states and transition conditions.

DS803PP1 19

CS4353

USER: Apply Power

USER: Apply MCLK

MCLK/LRCK Ratio Detection

USER: Apply LRCK and SCLK

Reset State

Power-Down State

Initialization State

Power-Up State

Outputs Grounded

Normal Operation State

Mute State

Valid MCLK/LRCK Ratio

USER: RESET Set High

RESET Tied High (if using POR)

USER: Change MCLK/LRCK ratio

Outputs Muted

Analog Output Generated

USER: RESET

Set Low

USER: Change MCLK/LRCK ratio

Valid MCLK/LRCK Ratio

Remove MCLK

Figure 9. Initialization and Power-Down Sequence Diagram

20 DS803PP1

CS4353

4.8 Recommended Power-Up and Power-Down Sequences

4.8.1 Power-Up Sequences

4.8.1.1 External RESET Power-Up Sequence

Follow the power-up sequence below if the external RESET pin is used:

1. Hold RESET low while the power supplies are turned on.

2. Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.

3. Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies as

discussed in Section 4.3.

4. After the power supplies, configuration pins, and clock signals are stable, bring RESET high. The

device will initiate the power-up sequence seen in Figure 9. The sequence will complete and audio

will be output from AOUT x with in 50 ms after RESET is set high.

4.8.1.2 Internal Power-On Reset Power-Up Sequence

Follow the power-up sequence below if the internal power-on reset is used:

1. Hold RESET high (connected to VL) while the power supplies are turned on. The power-on reset

circuitry will function as described in Section 4.6.

2. Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.

3. After the power supp lies and configuration pins are stable, provide the correct MCLK, LRCK, and

SCLK signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure 9.

The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid

clocks are applied.

4.8.2 Power-Down Sequences

4.8.2.1 External RESET Power-Down Sequence

Follow the power-down sequence below if the external RESET pin is used:

1. For minimal pops, set the input dig ital data to zero for at least 8192 consecutive samples.

2. Bring RESET low.

3. Remove the power supply voltages.

4.8.2.2 Internal Power-On Reset Power-Down Sequence

Follow the power-down sequence below if the internal power- on reset is used:

1. For minimal pops, set the input dig ital data to zero for at least 8192 consecutive samples.

2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin.

3. Remove the power supply voltages.

Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum

MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may

occur on the analog outputs if th e MCLK signa l duty cycle specification is violated when the MCLK signal

is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page 10.

DS803PP1 21

CS4353

4.9 Grounding and Power Supply Arrangements

As with any high-resolution converter, the CS4353 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 3 shows the recommended power ar-

rangements, with VCP, VA, and VL connected to clean supplies. It is strongly recom mended that a single

ground plane be used, with the DGND, CPGND, and AGND pins all connected to this common plane.

Should it be necessary to split the grou nd pl anes, the DGND and CPGND pins should be con nected to the

digital ground plane and the AGND pin should be connected to the analog ground plane. In this configura-

tion, it is critical that the digital and analog ground pl anes be tied together wit h a low-impedance connection,

ideally a strip of copper on the printed circuit board, at a single point near the CS4353.

All signals, especially clocks, should be kept away fr om the VBIAS pin in order to avoid unwanted coupling

into the DAC.

4.9.1 Capacitor Placement

Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic

capacitor being the closest. To further minimize impedance, these capacitors should be located on the

same PCB layer as the device. If desired, all supply pins may be connected to the same supply, but a

decoupling capacitor should still be placed on each supply pin. See DC Electrical Characteristics for the

voltage present across pin pair s. This is useful for choosing ap propriate capacitor voltage ra tings and ori-

entation if electrolytic capacitors are used.

The CDB4353 evaluation board demonstrates the optimum layout and power supply arrangements.

22 DS803PP1

CS4353

5. DIGITAL FILTER RESPONSE PLOTS

0.4 0.5 0.6 0.7 0.8 0.9 1

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

Figure 10. Single-Speed Stopband Rejection Figure 11. Single-Speed Transitio n Ban d

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−0.02

−0.015

−0.01

−0.005

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 12. Single-Speed Transition Band (de tail) Figure 13. Single-Speed Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 14. Double-Speed Stopband Rejection Figure 15. Double-Speed Transition Band

DS803PP1 23

CS4353

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 16. Double-Speed Transition Band (detail) Figure 17. Double-Speed Passband Ripple

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.8

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 18. Quad-Speed Stopband Rejection Figure 19. Quad-Speed Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25

0.2

0.15

0.1

0.05

0.1

0.15

0.2

Frequency(normalized to Fs)

Amplitude (dB)

Figure 20. Quad-Speed Transition Band (detail) Figure 21. Quad-Speed Passband Ripple

24 DS803PP1

CS4353

6. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the RMS value of the sig nal to the RMS sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-scale RMS value of the signal to the RMS su m of all other spectral components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full

scale. This technique ensu res that the distortion components are be low the noise level and do not affect the

measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-

1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the in put under test and a full-scale signal applied to the other channel. Units in deci-

bels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

DS803PP1 25

CS4353

7. PACKAGE DIMENSIONS

Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1994.

2. Dimensioning lead width applies to the metallized terminal and is measured between 0.15 mm and

0.30 mm from the terminal tip.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A - - 0.03937 - - 1.00 1

A1 0.00000 - 0.00197 0.00 - 0.05 1

b 0.00787 0.00984 0.01181 0.20 0.25 0.30 1, 2

e 0.01772 0.01969 0.02165 0.45 0.50 0.55 1

D 0.15748 BSC 4.00 BSC 1

D2 0.10433 0.10630 0.10827 2.65 2.70 2.75 1

E 0.15748 BSC 4.00 BSC 1

E2 0.10433 0.10630 0.10827 2.65 2.70 2.75 1

L 0.01181 0.01575 0.01969 0.30 0.40 0.50 1

Controlling Dimension is Millimeters

Parameter Symbol Min Typ Max Units

Junction to Ambient Thermal Impedance 2 Layer Board

4 Layer Board θJA

θJA

-68

28 -

-°C/Watt

°C/Watt

PIN #1

CORNER

1.00 REF

PIN #1 IDENT IFIER

LASER MARKING

TOP VIEW SIDE VIEW BOTTOM VIEW

24L QFN (4.00 mm BODY) PACKAGE DRAWING

26 DS803PP1

CS4353

8. ORDERING INFORMATION

Product Description Pack age Pb-Free Grade Temp Range Container Order #

CS4353 3.3 V S tereo Audio DAC

with 2 VRMS Line Output 24-pin QFN YES Commercial -40° to +85° C Rail CS4353-CNZ

Tape & Reel CS4353-CNZR

CS4353 3.3 V S tereo Audio DAC

with 2 VRMS Line Output 24-pin QFN YES Automotive -40° to +105° C Rail CS4353-DNZ

Tape & Reel CS4353-DNZR

CDB4353 CS4353 Evaluation Board - - - - CDB4353

DS803PP1 27

CS4353

9. REVISION HISTORY

Release Changes

PP1

– Updated interchann el isolation specification in the DAC Analog Characteristics (Commercial - CNZ) and

DAC Analog Characteristics (Automotive - DNZ) specification tables.

– Updated minimum Quad-Speed Mode SCLK period in the Switching Specifications - Serial Audio Interface

table.

– Updated power supply current and power dissipation specifications in the DC Electrical Characteristics

table.

– Updated the FLYN+ to FLYN- DC voltage in the DC Electrical Characteristics table.

– Added “SDIN = 0” to the test cond itions in the DC Electrical Characteristics table.

– Updated Section 4.8.1.1 on page 20.

– Updated output impedance specification in the DAC Analog Characteristics (Commercial - CNZ) and DAC

Analog Characteristics (Automotive - DNZ) specification tables.

28 DS803PP1

CS4353

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com.

IMPORTANT NOTICE

“Preliminary” p rod uct in formation describe s pr od ucts that a re in pr od uction, but for which full chara cteri zatio n da ta is not yet available.

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject

to change without notice a nd is pr ovided “A S IS” wi thout war ranty of any ki nd (expres s or i mplied). Customers are advi sed to ob tain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sa le

supplied a t the time of order acknowled gment, including tho se pertaining to warra nty, indemnification, an d limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third

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