XA-SCC UG - Philips Semiconductors / NXP Semiconductors

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Documentation developed by Andrew B. Napell

International Consulting Group

2021 The Alameda, Suite 220

San Jose, California 95126

http://www.icg-sj.com

The author wishes to thank the following persons:

Ata Khan, Bill Kolb, Frank Lee, Mary Ohanessian Sumner, Charlie Rehor, Greg Goodhue, Zhimin Ding,

Jay Slivkoff, Jerry Hao, Jane Zheng, Hartmut Habben, Amr Eissa, Ismael Nass-Duce, Carol McCarthy, and

Mark Powell.

iii
Table of Contents
List of Figures.......................................................................................................................xiii
List of Tables.......................................................................................................................xvii
Preface ..................................................................................................................................xxi
Chapter 1: Introduction....... ....... ...... ....... ...... ....... ...... ....... ......................... ....... ...... ....... .........1
1 About the XA Serial Communications Controller.............................................................2
2 Overview of XA-SCC Architecture...................................................................................3
2.1 XA-SCC Block Diagram....................................................................................3
2.2 Communications Between the CPU and Other On-Chip Devices.....................4
2.3 Receive  (Rx) Data Flow Simpli fie d............ ...... ...... ..... ...... ................. ..... ...... .....4
2.4 Transmit (Tx) Data Flow Simplified...................................................................5
2.5 SCC Options: Autobaud and V.54/2047...........................................................5
2.6 An Option for SCC0, SCC1, and SCC2: IDL Interface......................................6
2.7 Communications Between the CPU and Off-Chip Devices: 
SCP Interface6
2.8 Input/Output Using Multifunction Pins and Pin Function Multiplexing...............6
3 Major Features of the XA-SCC........................................................................................7
4 Typical Applications.......................................................................................................10
4.1 ISDN Terminal Adapter...................................................................................10
4.2 Four Independent Serial Channels .................................................................12
Chapter 2: XA-SCC CPU.......................................................................................................13
1 Introduction....................................................................................................................14
2 Timers............................................................................................................................14
2.1 Timer/Counters ...............................................................................................14
2.2 Watchdog Timer..............................................................................................14
3 Serial Ports (UARTs).....................................................................................................15
4 Event Interrupts.............................................................................................................15
5 Internal Data Me mo ry and Addre ssin g Scope............... ...... ..... ................. ...... ..... ...... ...15
5.1 Internal Data Me mo ry.......... ..... ...... ...... ..... ...... ................. ..... ...... ...... ..............15
5.2 Data Memory Addressing Scope ....................................................................16

iv
Table of  Con ten ts
6 Internal Code  Memo ry............................ ......................................................... ..... ...... ...16
7 Memory Mapped Registers (MMRs)..............................................................................17
8 ResetOut ....................................................................................................................... 18
8.1 Operation of Pin 58 and ResetOut During and After Power-Up......................19
9 External WAIT tim ing.............. ..... ........................................................ ...... ...... ..... ...... ...19
10 Special Function Register (SFR) Modifications.............................................................19
10.1 BCR (46Ah)..................................................................................................... 20
10.2 BTRH (469h)............................ ............................. ..... ...... ..... ...... ...... ..............20
10.3 BTRL (468h).................................................................................................... 20
10.4 MRBL (496h)...................................................................................................20
10.5 MRBH (497h)..................................................................................................21
10.6 MICFG (499h).................................................................................................21
10.7 IPA6 (4A6h).....................................................................................................21
10.8 IPA7 (4A7h).....................................................................................................21
10.9 PCON (404h).................................................................................................. 21
10.10 RSTSRC (463h)..............................................................................................21
10.11 XA-G3 SFRs Which Have Been Removed From the XA-SCC.......................22
Chapter 3: Memory Interface (MIF) and DRAM Controller.................................................23
1 Introduction.................................................................................................................... 24
2 MIF Architecture............................................................................................................24
2.1 MIF Block Diagram..........................................................................................24
2.2 MIF Register Set.............................................................................................26
3 MIF Memory Banks .......................................................................................................27
3.1 Bank 0............................................................................................................. 28
3.2 Banks 1 - 5......................................................................................................30
3.3 Bank 0 / Bank 1 Swapping..............................................................................31
4 Generic Memory Interface.............................................................................................34
4.1 Generic Memory Interface Addressing ............................................................ 34
4.2 Generic Memory Interface Timing................................................................... 34
5 DRAM Interface.............................................................................................................34
5.1 DRAM Burst Reads......................................................................................... 34
5.2 DRAM Interface Addressing............................................................................ 35
5.3 DRAM Interface Timing................................................................................... 36
6 DRAM Refresh .............................................................................................................. 37
6.1 DRAM Refresh Cycle Timing.......................................................................... 37

v
Table o f Conte nts
7 WAIT and Size8.............................................................................................................38
7.1 WAIT...............................................................................................................38
7.2 External WAIT Tim ing.............. ......................................................... ..... ...... ...39
7.3 Size8............................................................................................................... 39
8 MIF Arbiter.....................................................................................................................41
8.1 DMA Channel High Priority Override (DMA CHPO)........................................41
9 XA-SCC Memory Mapped Register Relocation.............................................................42
9.1 MRBH and MRBL............................................................................................42
10 MIF Configuration Example...........................................................................................42
11 MIF Special Function Register Descriptions.................................................................. 50
11.1 BTRH: Bus Timing Register High Byte (SFR 469h)........................................50
11.2 BTRL: Bus Timing Register Low Byte  (SFR 468h).........................................50
11.3 MRBH: MMR Base Address High Byte (SFR 497h)  ......................................51
11.4 MRBL: MMR Base Address Low Byte (SFR 496h) ........................................ 51
11.5 MICFG: Memory Interface Configuration (SFR 499h).....................................51
12 MIF Memory Mapped Register Descriptions.................................................................52
12.1 BiCFG: Bank i Configuration...........................................................................52
12.2 BiAM: Bank i Base Address/DRAM Address Multiplexer Control ................... 55
12.3 BiTMG: Bank  i Timing.............. ...... ...... ........................................................ ...55
12.4 MBCL: Memory Bank Configuration Lock....................................................... 58
12.5 RFSH: Refresh Timing....................................................................................59
Chapter 4: Direct Memory Access (DMA) Controller .........................................................61
1 Introduction.................................................................................................................... 62
2 DMA Channel Architecture............................................................................................62
3 Data Buffer Manag em ent in Ma in Memory..................................... ..... ...... ...... ..... ...... ...63
3.1 Circular Buffers ...............................................................................................64
3.2 Linear Buffers..................................................................................................65
4 Serial Tran smit DMA Transfer Process (Tx DMA) ......................................................... 65
4.1 General Principles of Tx DMA.........................................................................66
4.2 Tx Chaining.....................................................................................................67
4.3 Non-SDLC/HDLC Tx Chai nin g.................. ......................................................67
4.4 SDLC/HDLC Tx Chaining................................................................................ 69
4.5 Stop on TC (Terminal Count)..........................................................................73
4.6 Periodic Interrupt.............................................................................................73

vi
Table of  Con ten ts
5 Serial Receive DMA Transfer Process (Rx DMA).........................................................74
5.1 General Principles of Rx DMA ........................................................................74
5.2 Rx SDLC/HDLC ..............................................................................................75
5.3 Packet Status Byte..........................................................................................76
5.4 Rx SDLC/HDLC Partia l Byte...........................................................................77
5.5 Periodic Interrupt.............................................................................................79
5.6 Asynchronous Character Time Out.................................................................79
5.7 Asynchronous Character Match...................................................................... 80
5.8 Typical Response to an MCIP Interrupt .......................................................... 83
6 DMA Interrupts ..............................................................................................................84
7 DMA Register Descriptions ........................................................................................... 86
7.1 Global DMA Interrupt Register........................................................................87
7.2 DMA Control Register.....................................................................................88
7.3 Segment Regi ste r .................... ...... ...... ..... ......................................................90
7.4 Buffer Base Register...................... ...... ............................ ..... ...... ...... ..... ...... ...90
7.5 Buffer Bound Regis ter......... ..... ...... ...... ..... ......................................................90
7.6 Address Pointer Re gi ste r............... ...... ..... ......................................................91
7.7 Byte Count Regist er................. ...... ............................ ...... ..... ...... ...... ..... ......... 91
7.8 FIFO Control & Status Register ......................................................................91
7.9 Data FIFO Registers.......................................................................................92
7.10 Rx Character Time Out Register (RxCTOR)...................................................93
Chapter 5: Serial Communications Controller (SCC) ........................................................95
1 Introduction.................................................................................................................... 96
2 Features  of the SCC.................... ...... ..... ...... ............................ ...... ..... ...... ...... ..... ......... 96
3 SCC Architecture...........................................................................................................97
4 Communication Modes..................................................................................................99
4.1 Asynchronous Mode .......................................................................................99
4.2 SDLC/HDLC Mode........................................................................................101
4.3 Monosync Mode............................................................................................104
4.4 Bisync Mode..................................................................................................106
4.5 External Syn c Mode.............................................. ..... ...... ..... ...... ...... ............108
4.6 Transpar ent Mo de......... ...... ..... ...... ............................ ...... ..... ...... ...... ..... ....... 10 9
5 Baud Rate Genera tor .................. ...... ..... ...... ............................ ...... ..... ...... ...... ..... ....... 11 1
5.1 BRG and Autobaud....................................................................................... 111
5.2 The SCC Baud Rate Generator....................................................................111
5.3 Baud Rate Generator Example.....................................................................114

vii
Table o f Conte nts
6 SCC Clocks.................................................................................................................115
6.1 SCC Clock Issues When (and when not) Using IDL..................................... 115
6.2 SCC0 Clock Discus si on................. ...... ..... ...... ............................ ...... ..... ...... .117
6.3 SCC0 Clock Inputs.................................... ...... ...... ..... ...... ..... ........................118
6.4 SCC0 Clock Outputs...................... ...... ..... ...... ............................ ...... ..... ...... .119
7 SCC Interrupts.............................................................................................................123
7.1 SCC Channel Interrupt Groups.....................................................................124
7.2 IE Bits and IP Bits .........................................................................................125
7.3 SCC Interrupt Priorities.................................................................................125
7.4 SCC Receive Interrupts ................................................................................125
7.5 SCC Transmit Interrupts ...............................................................................126
7.6 SCC External/Status Interrupts.....................................................................126
8 SCC Write Registers ...................................................................................................129
8.1 Write Register 0: Command Register ........................................................... 130
8.2 Write Register 1: Transmit/Receive Interrupt Control ...................................133
8.3 Write Register 2: SDLC Enhancement..........................................................135
8.4 Write Register 3: Receiver Control................................................................136
8.5 Write Regi ste r 4: Tx and Rx Paramet ers and  Modes............ ...... ...... ............139
8.6 Write Register 5: Transmitter Control............................................................141
8.7 Write Register 6: Station Address/Sync Char Low/Async Match Char.........143
8.8 Write Register 7: HDLC Flag/Sync Char High/Async Match Char................144
8.9 Write Registe r 8: Tx Data Buffer............... ....................................................144
8.10 Write Register 9: Channel Reset/Master Interrupt Enable............................144
8.11 Write Register 10: Miscellaneous Tx and Rx Control....................................146
8.12 Write Register 11: Clock Mode Control.........................................................148
8.13 Write Register 12: Baud Rate Generator TC Lower Byte .............................149
8.14 Write Register 13: Baud Rate Generator TC Upper Byte ............................. 150
8.15 Write Register 14: Miscellaneous Control Bits..............................................151
8.16 Write Register 15: External/Status Interrupt Control..................................... 1 54
8.17 Write Registers 16 and 17: Async Match Characters ...................................156
9 SCC Read Registers................................................................................................... 156
9.1 Read Register 0: Interrupt Status Bits...........................................................157
9.2 Read Register 1: Special Receive Condition................................................ 160
9.3 Read Register 3: Interrupt Pending...............................................................161
9.4 Read Register 6: SDLC Byte Count Lower Byte...........................................163
9.5 Read Register 7: SDLC Byte Count Upper Byte...........................................164
9.6 Read Register 8: Rx Data  Buffer...................................................................164
9.7 Read Register 10: Miscellaneous Status Bits...............................................165

viii
Table of  Con ten ts
Chapter 6: Autobaud........... ....... .......................... ...... ....... ...... ....... ...... ...... ....... ...... ....... .....167
1 Introduction.................................................................................................................. 168
2 Autobaud Detection.....................................................................................................168
3 Clocks and Valid Baud Rates......................................................................................171
3.1 Autobaud Source Clock ................................................................................171
3.2 Valid Baud Rates ..........................................................................................171
3.3 Acceptable Baud Rate Error Margins............................................................173
4 Autobaud Echo............................................................................................................174
5 Autobaud Interrupts.....................................................................................................174
6 Using Autobaud...........................................................................................................175
6.1 SCC Write Register Configuration for Autobaud...........................................176
7 Autobaud Register Descriptions..................................................................................177
7.1 BDAEE: Autobaud Echo Enab le  .................... ...... ..... ............................ ...... .177
7.2 BDCS: Autobaud Control and Status ...........................................................177
Chapter 7: V.54/2047 Units.................................................................................................179
1 Introduction.................................................................................................................. 180
2 Assigning V.54/2047 Units ..........................................................................................180
2.1 Assigning V.54/2047 Unit A ..........................................................................180
2.2 Assigning V.54/2047 Unit B ..........................................................................183
3 V.54 and 2047 Receive............................................................................................... 1 85
3.1 V.54 Receive................................................................................................. 186
3.2 2047 Receive................................................................................................186
4 V.54 and 2047 Generate.............................................................................................187
4.1 V.54 Generate...............................................................................................187
4.2 2047 Generate.............................................................................................. 187
5 V.54/2047 Interrupts....................................................................................................187
6 V.54/2047 Register Descriptions.................................................................................189
6.1 VxCS: Unit x Control and Status Register.....................................................189
6.2 VxCFG: Unit x Configuration Register ..........................................................191
6.3 VxTCL: Unit x Receiver Threshold Counter Low Byte..................................192
6.4 VxTCH: Unit x Receiver Threshold Counter High Byte.................................192
6.5 VxEC: Unit x Receiver Error Counter............................................................192
7 V.54 and 2047 Circuits................................................................................................193

ix
Table o f Conte nts
Chapter 8: IDL Interface......................................................................................................195
1 Introduction.................................................................................................................. 196
2 IDL Interface Architecture............................................................................................196
2.1 IDL Interface Block Diag ram.......... ...... ..... ....................................................196
3 IDL Bus Signals...........................................................................................................199
3.1 How the XA-SCC Uses D Channel Request and Grant................................199
3.2 Assigning SDS1 and SDS2...........................................................................200
4 IDL Interface Clocks.................................................................................................... 2 00
4.1 Maximum Frequency for L1Clk.....................................................................201
5 Assigning B1, B2, and D Channels to SCCs...............................................................203
6 B Channel Bit Masking and Enable.............................................................................203
6.1 B Channel Bit Masking..................................................................................203
6.2 B Channel Enable.........................................................................................204
7 Configuration Example................................................................................................206
8 IDL Interface Register Descriptions.............................................................................208
8.1 MSI Control Register.....................................................................................208
8.2 DataMask Register........................................................................................210
Chapter 9: SCP Interface....................................................................................................213
1 Introduction.................................................................................................................. 214
2 The SCP State Machine..............................................................................................215
3 SCP Timing .................................................................................................................216
3.1 Data Rate - Frequency of SCPClk................................................................216
3.2 Description of SCP Bus Cycle....................................................................... 2 16
4 SCP Interrupts.............................................................................................................218
5 SCP Register Descriptions.......................................................................................... 2 19
5.1 SCPCFG: SCP Configuration .......................................................................219
5.2 SCPD: SCP Data Byte............. ...... ............................ ...... ..... ...... ...... ..... ....... 22 0
5.3 SCPCS: SCP Control and Status................................................................. .220
Chapter 10: Interrupts......... ....... ...... .......................... ....... ...... ....... ...... ...... ....... ...... ....... .....223
1 Introduction.................................................................................................................. 224
2 Overview of Native XA Interrupts ................................................................................224
2.1 SFR Bit Addressing Primer...........................................................................225
3 XA-SCC Event Interrupts.............................................................................................226
4 High Priority Software Interrupts..................................................................................228

x
Table of  Con ten ts
5 SCP Interrupt...............................................................................................................229
6 Autobaud and V.54/2047 Interrupts.............................................................................229
7 SCC Interrupts.............................................................................................................230
8 DMA Interrupts ............................................................................................................235
9 External Interrupt 2 (INT2)...........................................................................................237
10 External Interrupts 0 and 1, and Timers 0 and 1.........................................................238
Chapter 11: XA-SCC Pins................ .......................... ....... ...... ....... ...... ...... ....... ...... ....... .....241
1 Introduction.................................................................................................................. 242
2 XA-SCC Pin Signals and Functions ............................................................................242
3 Pin Groupings By Function..........................................................................................244
3.1 Functional Pin Groups for Typical ISDN Configuration.................................245
3.2 Functional Pin Groups for 4 Independent Serial Channels...........................246
4 Multifunction Pins ........................................................................................................247
4.1 Review of XA I/O Ports ................................................................................. 247
4.2 I/O Port Naming Conventions .......................................................................247
4.3 I/O Port Configurations.................................................................................. 2 48
4.4 Multifunction Pin Programming Example...................................................... 249
4.5 Pin Multiplexing Control Register (PMCR), MMR 2D0h................................ 2 50
5 Multifunction Pin Schematics....................................................................................... 2 52
5.1 Pin 56: P3.0_CS4_RAS4_RTClk1................................................................252
5.2 Pin 57: P3.1_CS5_RAS5_RTS1................................................................... 253
5.3 Pin 58: P3.2_Timer0_ResetOut.................................................................... 254
5.4 Pin 63: P3.3_BRG1_Timer1_Sync1.............................................................. 255
5.5 Pin 64: P3.4_CTS1 .......................................................................................256
5.6 Pin 65: P3.5_RxD1........................................................................................ 2 57
5.7 Pin 66: P3.6_TxD1........................................................................................ 258
5.8 Pin 67: P3.7_INT 1_TRClk1..........................................................................259
5.9 Pin 68: P1.0_RxD2........................................................................................ 2 60
5.10 Pin 69: P1.1_TxD2........................................................................................ 261
5.11 Pin 70: P1.2_RTClk2.....................................................................................262
5.12 Pin 71: P1.3_TRClk2.....................................................................................263
5.13 Pin 72: P1.4_CD2.........................................................................................264
5.14 Pin 73: P1.5_CTS2 .......................................................................................265
5.15 Pin 74: P1.6_RTS2 .......................................................................................266
5.16 Pin 75: P1.7_BRG2_Sync2........................................................................... 267
5.17 Pin 78: CD1_Int2 (Input Only)....................................................................... 2 68

xi
Table o f Conte nts
11.5.18 Pin 80: P2.0_RxD3........................................................................................269
11.5.19 Pin 81: P2.1_TxD3........................................................................................ 270
11.5.20 Pin 82: P2.2_RTClk3.....................................................................................271
11.5.21 Pin 83: P2.3_ComClk_TRClk3...................................................................... 2 72
11.5.22 Pin 84: P2.4_CD3.........................................................................................273
11.5.23 Pin 85: P2.5_CTS3 .......................................................................................274
11.5.24 Pin 86: P2.6_RTS3 .......................................................................................275
11.5.25 Pin 87: P2.7_Sync3_BRG3........................................................................... 276
11.5.26 Pin 90: P0.0_Sync0_BRG0_SDS2 ...............................................................277
11.5.27 Pin 91: P0.1_RTS0_L1RQ............................................................................278
11.5.28 Pin 92: P0.2_CTS0_L1GR............................................................................279
11.5.29 Pin 93: P0.3_CD0_L1SY1.............................................................................280
11.5.30 Pin 94: P0.4_TRClk0_SDS1......................................................................... 2 81
11.5.31 Pin 95: P0.5_RTClk0_L1Clk ......................................................................... 282
11.5.32 Pin 96: TxD0_L1TxD.....................................................................................283
11.5.33 Pin 97: RxD0_L1RxD.................................................................................... 284
11.5.34 Pin 99: P0.6_SCPTx.....................................................................................285
11.5.35 Pin 100: P0.7_SCPRx...................................................................................286
11.6 XA-SCC Pinout............................................................................................................ 287
Appendix A: XA-SCC Programming Examples................................................................289
A.1 Introduction.................................................................................................................. 290
A.2 Boot Code & Bank 0 / Bank 1 Swapping (Assembly).................................................. 290
A.3 Set Up SCC3/DMA3 for Async Mode (C)....................................................................295
A.4 Set Up IDL (C)............................................................................................................. 297
A.5 Set Up SCC1/DMA1 for Clear Channel with IDL (C)...................................................299
A.6 Set Up SCC3/DMA3 for Clear Channel with NMSI (C) ............................................... 302
A.7 Set Up SCC0/DMA0 for HDLC Tx Chaining with IDL (C)............................................304
A.8 Note About Reset External/Status Interrupts Command.............................................307
Appendix B: Bus Timing Examples...................................................................................309
B.1 SRAM (or other generic memory) Timing Examples...................................................310
B.2 DRAM Timing Examples .............................................................................................325
Appendix C: SFR and MMR Addresses.............................................................................339
C.1 Special Function Register (SFR) Addresses...............................................................340
C.2 Memory Mapped Register (MMR) Addresses.............................................................343

xii

Table of Con ten ts

Appendix D: V.54 & 2047 Generator Output.....................................................................351

D.1 V.54 Generator Scrambled Zeros Output (VxGP = 0).................................................352

D.2 V.54 Generator Scrambled Ones Output (VxGP = 1) .................................................353

D.3 2047 Generator Output................................................................................................354

Glossary...............................................................................................................................355

Index.....................................................................................................................................360

xiii
List of Figures
Figure 1-1 Simplified Block Diagram of the XA-SCC .........................................................................3
Figure 1-2 ISDN Terminal Adapter...................................................................................................10
Figure 1-3 ISDN Terminal Adapter, showing DMA channels...........................................................11
Figure 1-4 Four Independent Serial Channels................................................................................. 12
Figure 2-1 Logic for Pin 58 Showing Details of ResetOut................................................................18
Figure 3-1 MIF Block Diagram (showing address and strobe generation only) ...............................25
Figure 3-2 DRAM Refresh Cycle...................................................................................................... 38
Figure 3-3 External WAIT State s....................................................................... ..... ...... ...... ..... ..... . ...39
Figure 3-4 Typical circuits for WAIT_Size8 pin ................................................................................40
Figure 3-5 Interconnections for MIF Configuration Example............................................................43
Figure 4-1 DMA Register Set........................................................................................................... 63
Figure 4-2 Circular Buffer.................................................................................................................64
Figure 4-3 Non-SDLC/HDLC Tx Chaining packet format in memory...............................................68
Figure 4-4 SDLC/HDLC Tx Chaining Packet format in memory ...................................................... 71
Figure 4-5 SDLC/HDLC Tx Chaining Flow-Chart.............................................................................72
Figure 4-6 Rx SDLC/HDLC packet format in main memory............................................................. 76
Figure 4-7 SDLC/HDLC Residue Bits - Rx DMA Memory Images for “Partial Byte”........................78
Figure 4-8 Rx Character Time Out Timer......................................................................................... 80
Figure 4-9 Relevant MMRs for Asynchronous Character Match......................................................82
Figure 4-10 DMA Interrupt Structure..................................................................................................85
Figure 5-1 Block Diagram of a Typical SCC Channel......................................................................98
Figure 5-2 Baud Rate Genera tor............... ..... ...... ..... ......................................................... ..... ...... .111
Figure 5-3 SCC clock options when (and when not) using IDL......................................................117
Figure 5-4 SCC0 Clocks (see Section s 5.6. 3 and 5.6.4 ).................. ...... ..... ...... .............................120
Figure 5-5 SCC1 Clocks...................... ...... ..... ...... ..........................................................................121
Figure 5-6 SCC2 Clocks...................... ...... ..... ...... ..........................................................................122
Figure 5-7 SCC3 Clocks...................... ...... ..... ...... ..........................................................................123
Figure 5-8 SCC0/SCC1 Interrupt Structure....................................................................................128

xiv
List of Fig ure s
Figure 5-9 Continuation of SCC Interrupt Structure, Showing Both SCC Interrupt Groups...........129
Figure 5-10 Least Significant Bit First, 6 Bits per Character ............................................................ 1 53
Figure 5-11 Most Significant Bit First, 6 Bits per Character ............................................................. 1 53
Figure 6-1 Autobaud Detection State Diagram ..............................................................................170
Figure 7-1 Logic for Pin 96.............................................................................................................182
Figure 7-2 Logic for Pin 69.............................................................................................................182
Figure 7-3 Logic for Pin 66.............................................................................................................184
Figure 7-4 Logic for Pin 81.............................................................................................................185
Figure 7-5 V.54 Generator .............................................................................................................193
Figure 7-6 V.54 Receiver ...............................................................................................................193
Figure 7-7 2047 Generator.............................................................................................................194
Figure 7-8 2047 Receiver...............................................................................................................194
Figure 8-1 IDL Interface Block Diag ram.................... ...... ...... ..... ...... ..............................................198
Figure 8-2 IDL Clocks to SCC0......................................................................................................201
Figure 8-3 IDL Clocks to SCC1......................................................................................................202
Figure 8-4 IDL Clocks to SCC2......................................................................................................202
Figure 8-5 DataMask Bits and B Channel Bit Time Slots............................................................... 204
Figure 8-6 DataMask and P0[4] Affecting SDS1 and SDS2...........................................................205
Figure 8-7 Bit Masking, Showing Clocks to SCC1 and SCC2........................................................ 207
Figure 8-8 D Channel Grant, Showi ng Cloc ks to SCC0........ ..... ...... ..............................................208
Figure 8-9 8-Bit Frame (“Short Frame”) IDL Format ...................................................................... 211
Figure 8-10 10-Bit Frame IDL Format..............................................................................................211
Figure 9-1 SCP Block Diagram......................................................................................................215
Figure 9-2 SCP Bus Cycle Timing with both Polarities of SCPClk................................................. 218
Figure 10-1 XA-SCC Event Interrupt Structure................................................................................239
Figure 11-1 Typical ISDN: SCC0 - SCC2 using IDL, SCC3 using NMSI interface ..........................245
Figure 11-2 Four Independent Serial Channels............................................................................... 246
Figure 11-3 Multifunction Pin Exampl e, using Pin 94....................................................................... 249
Figure 11-4 Pin Mux Control Register (PMCR)................................................................................250
Figure 11-5 Pin 86, Showing the Use of PMCR[3]........................................................................... 251
Figure 11-6 Pin 56............................................................................................................................252
Figure 11-7 Pin 57............................................................................................................................253
Figure 11-8 Pin 58............................................................................................................................254

xv
List of  Figures
Figure 11-9 Pin 63............................................................................................................................255
Figure 11-10 Pin 64............................................................................................................................256
Figure 11-11 Pin 65............................................................................................................................257
Figure 11-12 Pin 66............................................................................................................................258
Figure 11-13 Pin 67............................................................................................................................259
Figure 11-14 Pin 68............................................................................................................................260
Figure 11-15 Pin 69............................................................................................................................261
Figure 11-16 Pin 70............................................................................................................................262
Figure 11-17 Pin 71............................................................................................................................263
Figure 11-18 Pin 72............................................................................................................................264
Figure 11-19 Pin 73............................................................................................................................265
Figure 11-20 Pin 74............................................................................................................................266
Figure 11-21 Pin 75............................................................................................................................267
Figure 11-22 Pin 78............................................................................................................................268
Figure 11-23 Pin 80............................................................................................................................269
Figure 11-24 Pin 81............................................................................................................................270
Figure 11-25 Pin 82............................................................................................................................271
Figure 11-26 Pin 83............................................................................................................................272
Figure 11-27 Pin 84............................................................................................................................273
Figure 11-28 Pin 85............................................................................................................................274
Figure 11-29 Pin 86............................................................................................................................275
Figure 11-30 Pin 87............................................................................................................................276
Figure 11-31 Pin 90............................................................................................................................277
Figure 11-32 Pin 91............................................................................................................................278
Figure 11-33 Pin 92............................................................................................................................279
Figure 11-34 Pin 93............................................................................................................................280
Figure 11-35 Pin 94............................................................................................................................281
Figure 11-36 Pin 95............................................................................................................................282
Figure 11-37 Pin 96............................................................................................................................283
Figure 11-38 Pin 97............................................................................................................................284
Figure 11-39 Pin 99............................................................................................................................285
Figure 11-40 Pin 100..........................................................................................................................286
Figure B-1 Typical SRAM 16-Bit Bus Read Cycle..........................................................................310

xvi
List of Fig ure s
Figure B-2 SRAM 16-Bit Bus Read Cycle with Longer Access Time.............................................311
Figure B-3 SRAM 16-Bit Bus Read Cycle with CS to BLE/BHE Delay...........................................312
Figure B-4 SRAM 16-Bit Bus Read Cycle with Longer Recovery Time..........................................313
Figure B-5 Typical SRAM 16-Bit Bus Write Cycle..........................................................................313
Figure B-6 SRAM 16-Bit Bus Write Cycle with Longer Access Time ............................................. 314
Figure B-7 SRAM 16-Bit Bus Write Cycle with CS to BLE/BHE Delay...........................................315
Figure B-8 SRAM 16-Bit Bus Write Cycle with Longer Access Time and CS to BLE/BHE 
Delay.............................................................................................................................316
Figure B-9 SRAM 16-Bit Bus Write Cycle with CS to WE Delay....................................................317
Figure B-10 SRAM 16-Bit Bus Write Cycle with CS to WE Delay and BLE/BHE Conversion to
WEL/WEH.....................................................................................................................318
Figure B-11 SRAM 16-Bit Bus Write Cycle with Longer Recovery Time..........................................319
Figure B-12 Typical SRAM Word Read Cycle on an 8-Bit Bus, or 2-Word Burst Code Fetch 
on a 16-Bit Bus .............................................................................................................320
Figure B-13 SRAM 8-Bit Bus Word Read Cycle with CS to BLE Delay ...........................................321
Figure B-14 Typical SRAM Word Write Cycle on an 8-Bit Bus......................................................... 322
Figure B-15 SRAM 8-Bit Bus Word Write Cycle with BLE converted to WEL..................................323
Figure B-16 SRAM 8-Bit Bus Word Write Cycle with No CS to WE Delay.......................................324
Figure B-17 Typical DRAM 16-Bit Bus Word Write Cycle ................................................................325
Figure B-18 DRAM Word Write Cycle on 16-Bit Bus, with longer RAS to CAS delay, and Longer
Recovery Time..............................................................................................................327
Figure B-19 Typical DRAM 8-Bit Bus Word Write Cycle ..................................................................328
Figure B-20 Typical DRAM 16-Bit Bus Data Read Cycle................................................................. 329
Figure B-21 DRAM 16-Bit Bus Data Read Cycle, with Longer Recovery Time................................330
Figure B-22 Typical Fast Page Mode DRAM Burst Code Read (x2) on 16-Bit Bus......................... 331
Figure B-23 Fast Page Mode DRAM Burst Code Read (x2) on  16-Bit Bus, with Longer RAS 
to CAS Delay ................................................................................................................332
Figure B-24 Fast Page Mode DRAM Burst Code Read (x2) on  16-Bit Bus, with Longer 
Access Time .................................................................................................................333
Figure B-25 Fast Page Mode DRAM Burst Code Read (x2) on  16-Bit Bus, with Longer 
Recovery Time..............................................................................................................334
Figure B-26 Typical EDO DRAM Burst Code Read (x2) on 16-Bit Bus............................................335
Figure B-27 EDO DRAM Burst Code  Read (x2) on 16-Bit Bus, with Longer RAS to CAS Delay.....336
Figure B-28 EDO DRAM Burst Code  Read (x2) on 16-Bit Bus, with Longer Access Time..............337
Figure B-29 EDO DRAM Burst Code  Read (x2) on 16-Bit Bus, with Longer Recovery Time ..........338

xvii
List of Tables
Table 2-1 How to Access Internal and External Data Memory .......................................................16
Table 3-1 MIF Register Set.............................................................................................................26
Table 3-2 Bank 0 Size and Address Range Select ........................................................................29
Table 3-3 Banks 1-5 Size and Base Address Select ......................................................................30
Table 3-4 CS0 (ROM) and CS1 (DRAM) Control Bits Before and After Swapping.........................33
Table 3-5 CS0 (ROM) and CS1 (Generic) Control Bits Before and After Swapping.......................33
Table 3-6 BiMX1 and BiMX0 Configuration ....................................................................................35
Table 3-7 DRAM Row and Column Address Multiplexing............................................................... 36
Table 3-8 MIF Arbiter Priority Rankings..........................................................................................41
Table 4-1 DMA Registers................................................................................................................62
Table 4-2 Tx DMA Modes...............................................................................................................67
Table 4-3 Byte Count and LastFrag Bit Options, non-SDLC/HDLC Tx Chaining............................69
Table 4-4 Byte Count and LastFrag options, SDLC/HDLC Tx Chaining.........................................71
Table 4-5 SDLC/HDLC Residue Bits and Data Bit Positions of Last Byte of pa cket ......................78
Table 4-6 Last Matched Codes.......................................................................................................81
Table 4-7 DMA Interrupt Bits........................................................................................................... 86
Table 5-1 BRG Programming for BRGClk = PClk = 14.7456 MHz (CClk = 29 .4912 MHz) ..........113
Table 5-2 Maximum SCC Clock Frequencies...............................................................................115
Table 5-3 SFR Addresses for SCC Interrupts...............................................................................124
Table 5-4 External/ Statu s Inte rrupt s .. ...... ..... ...... ..... ...... ............................ ...... ..... ...... ...... ..... ....... 127
Table 5-5 Write Registe r  6 Bit Positions ....... ...... ............................ ...... ..... ...... ..... ...... ..................143
Table 5-6 Write Registe r  7 Bit Positions ....... ...... ............................ ...... ..... ...... ..... ...... ..................144
Table 6-1 Baud RateM with CClk = 29.4912 MHz ........................................................................ 172
Table 6-2 Baud RateM Error Windows in Number of CClk Cycles ...............................................173
Table 6-3 Recommended SCC Write Register Values for Use with Autobaud.............................176
Table 7-1 V.54/2047 Unit A Assignment Bits................................................................................181
Table 7-2 V.54/2047 Unit B Assignment Bits................................................................................184
Table 7-3 V.54 and 2047 Interrupt Conditions..............................................................................188

xviii
List of  Tab les
Table 10-1 Native XA Interrupts .................................................................................................. ... 224
Table 10-2 XA-SCC Event Interrupts.............................................................................................. 227
Table 10-3 Autobaud and V.54/2047 Interrupt Flags......................................................................229
Table 10-4 SCC0 Interrupts....................... ..... ...... ........................................................ ...... ..... .. .... .231
Table 10-5 SCC1 Interrupts....................... ..... ...... ........................................................ ...... ..... .. .... .232
Table 10-6 SCC2 Interrupts....................... ..... ...... ........................................................ ...... ..... .. .... .233
Table 10-7 SCC3 Interrupts....................... ..... ...... ........................................................ ...... ..... .. .... .234
Table 10-8 DMA 0 Interrupts...........................................................................................................236
Table 10-9 DMA 1 Interrupts...........................................................................................................236
Table 10-10 DMA 2 Interrupts...........................................................................................................237
Table 10-11 DMA 3 Interrupts...........................................................................................................237
Table 10-12 GPI/O Configurations for External Event Interrupts...................................................... 240
Table 11-1 XA-SCC Pin Signals and Functions .............................................................................242
Table 11-2 I/O Port Configuration Modes .......................................................................................248
Table 11-3 Programming Pin 94.....................................................................................................250
Table 11-4 Programming Pin 56.....................................................................................................252
Table 11-5 Programming Pin 57.....................................................................................................253
Table 11-6 Programming Pin 58.....................................................................................................254
Table 11-7 Programming Pin 63.....................................................................................................255
Table 11-8 Programming Pin 64.....................................................................................................256
Table 11-9 Programming Pin 65.....................................................................................................257
Table 11-10 Programming Pin 66..................................................................................................... 258
Table 11-11 Programming Pin 67..................................................................................................... 259
Table 11-12 Programming Pin 68..................................................................................................... 260
Table 11-13 Programming Pin 69..................................................................................................... 261
Table 11-14 Programming Pin 70..................................................................................................... 262
Table 11-15 Programming Pin 71..................................................................................................... 263
Table 11-16 Programming Pin 72..................................................................................................... 264
Table 11-17 Programming Pin 73..................................................................................................... 265
Table 11-18 Programming Pin 74..................................................................................................... 266
Table 11-19 Programming Pin 75..................................................................................................... 267
Table 11-20 Programming Pin 78 (Input Only) .................................................................................268
Table 11-21 Programming Pin 80..................................................................................................... 269

xix
List of  Tables
Table 11-22 Programming Pin 81..................................................................................................... 270
Table 11-23 Programming Pin 82..................................................................................................... 271
Table 11-24 Programming Pin 83..................................................................................................... 272
Table 11-25 Programming Pin 84..................................................................................................... 273
Table 11-26 Programming Pin 85..................................................................................................... 274
Table 11-27 Programming Pin 86..................................................................................................... 275
Table 11-28 Programming Pin 87..................................................................................................... 276
Table 11-29 Programming Pin 90..................................................................................................... 277
Table 11-30 Programming Pin 91..................................................................................................... 278
Table 11-31 Programming Pin 92..................................................................................................... 279
Table 11-32 Programming Pin 93..................................................................................................... 280
Table 11-33 Programming Pin 94..................................................................................................... 281
Table 11-34 Programming Pin 95..................................................................................................... 282
Table 11-35 Programming Pin 96 (Output Only)...............................................................................2 83
Table 11-36 Programming Pin 97 (Input Only) .................................................................................284
Table 11-37 Programming Pin 99..................................................................................................... 285
Table 11-38 Programming Pin 100...................................................................................................286
Table A-1 Initial Confi gur atio n, Before Swappin g...................... ...... ...... ..... ...... .............................290
Table A-2 Final Configuration, After Swapping .............................................................................290
Table C-1 Special Function Register (SFR) Addresses ...............................................................340
Table C-2 Memory Mapped Register (MMR) Addresses ..............................................................343

List of Tab les

Preface xxi

Preface 1

This book provides information about the Philips XA Serial Communications Controller

(XA-SCC). The typographic conventions used in the book are explained below.

Convention Meaning

Overline An overlined si

nal name (for example RAS ) is the inverse

of that si

nal.

Square brackets, [ ] Contain bit number(s).

Example: [3] identifies bit 3; whereas [4:2] identifies bits 4,

3, and 2.

In addition, this book makes use of gray shadow boxes, like thi s one, to prov ide notes

and warnings.

xxii Preface

Chapter 1: Introduction 1

Chapter 1

Introduction 1

Contents

1.1 About the XA Serial Communicat ions Controller...... ............. ............. ............ ............. ............ ......................2

1.2 Overview of XA-SCC Architecture .................................................................................................................3

1.3 Major Features of the XA-SCC...................................................................................................................... 7

1.4 Typical Applications.....................................................................................................................................10

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

2Chapter 1: Introduction

About the XA Seria l Comm unicat ions Con trolle r

1.1 About the XA Serial Communications Controller

The XA Serial Communications Controller (XA-SCC) is a DMA driven, multi-channel,

multi-protocol, serial comm unications controller with an embedded high-performance

16-bit 80C51-XA core. Because of its flexible architecture and extensive

programmability, the XA-SCC is able to provide bidirectional, full-du plex, serial

communications on as many as four channels simultaneously, with each channel using a

dif ferent com mun icat i o ns pro to col if desir ed.

The XA-SCC incorporates numerous features to reduce system cost. By virtue of its six

resizable memory banks, each with a dedicated Chip Select (CS) outp ut, as many as six

external memory devices can be connected to the XA-SCC using no external glue logic.

Additionally, the XA-SCC provides an on- chip DRAM controller, which supports DRAM

sizes up to 8 MBytes.

At the heart of the XA-SCC are four independent, high-speed, bidirectional Serial

Communications Controllers (SCCs). Each SCC interfaces with the system bus through a

dedicated pair of DMA channels; one channel for Transmit (Tx) and one for Receive

(Rx). The SCCs are based on an industry standard design, but they incorporate extensive

architectural modifications and functional improvements which greatly enhance their

programmability, flexi bil ity, and ease-of-use.

All four SCCs support six different protocols, and each protocol can be implemented on

the industry standard IDL (Interchip Digital Link) or NMSI (Non-Multiplex e d Serial

Interface) physical layer interface. An SCC can be clocked by external clock sources, or

internally via its programmable Baud Rate Generator. Since each SCC’s transmitter and

receiver operate independently, they can be clocked independently. Each SCC has a

dedicated Autobaud circuit, which can provide automatic baud rate detection and Baud

Rate Generator configuration for the channel.

Three of the SCCs can be internally connected to the on-chip IDL Interface, a glueless

interface to Layer One devices. Thus connected, the three SCCs efficiently support the

ISDN B1, B2, and D channels. In addition, all four SCCs provide support for the seven

standard NMSI interface signals: RxD, TxD, RClk, TClk, RTS, CTS, and CD. Other

mode m control signals, like DSR a nd DTR, can be easi ly suppor t ed under software

control through General Purpose Input/Output (GPI/O) Ports.

In addition to their multiple clock options, Autobaud capabilities, and IDL Interface

connectivity, each SCC has direct access to a V. 54/2047 line testing protocol generator

and receiver.

Chapter 1: Introduction 3

Overview of XA-SCC Architecture

The XA-SCC’s core CPU is a high performance 16-bit 80C51-XA. The CPU, with its

enhanced instruction set and architecture, provides extensive bit-oriented operations in

addition to support for multi-tasking operating system s and high-level languages. The XA

CPU has a 24-bit address space (16M Bytes), 16-bit stack pointers and general purpose

registers, and offers both 16-bit and 8-bit bus access. Since most instructions are between

two and four bytes in length, the XA core executes code very efficiently. It also offers

Power-Down and Idle power reduction modes, and hardware support for multi-tasking

software.

For contro l communications with a U-Chip, and/or other physical layer devices, the CPU

uses the on-chip SCP Interface. This interface is a bidirectional, full duplex, synchronous

communication bus, similar to SPI and Microwire. General Purpose I/O Port (GPI/O) pin

functions are used to provide SCP enables (CS) to slave devices, and so the number of

supportable slave devices is limited only by the number of available port pins.

1.2 Overview of XA-SCC Architecture

1.2.1 XA-SCC Block Diagram

A simplified block diagram of the XA-SCC appears in Figure 1-1. As depicted in the

figure, the XA-SCC’s architecture revolves around nine functional blocks (or devices) of

primary importance: CPU, DRAM Controller and Memory Interface (MIF), DMA, SCC,

Autobaud, V.54/2047, IDL Interface, SCP Interface, and Pin Function MUX.

Figure 1-1 Simplifie d Block Diagram of the XA-SCC

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

4Chapter 1: Introduction

Overview of XA-SCC Architecture

1.2.2 Communications Between the CPU and Other On-Chip Devices

The CPU communicates with other devices on the chip in three fundamental ways:

1. The CPU issues commands by writing to a device’s control registers. Nearly all of

the control registers, for devices other than the CPU itself, are Memory Mapped

Registers (MMRs). The exception is th e DRAM Controller and MIF, which also uses

a few Special Function Registers (SFRs). SFRs are discussed in Chapter 2,

“XA-SCC CPU.” MMRs are discussed in Chapter 2, “XA-SCC CPU,” and again in

Chapter 3, “Memory Interface (MIF) and DRAM Controller.”

2. The CPU gathers information about the status of a device by reading the device’s

status registers. Nearly all of the status registers are MMRs.

3. Some devices can interrupt the CPU by setting one or more interrupt flags. Some

interrupt flags are SFR bits and some are MMR bits. Furthermore, some interrupt

flags are cleared by writing ‘0’ to the flag’s bit position, and some are cleared by

writing ‘1’. Details can be fou nd in the individual register descriptions for the

relevant device.

1.2.3 Receive (Rx) Data Flow Simplified

The following is a typical process whereby the XA-SCC receives Rx data from the

physical layer interface, and stores it in external memory:

Receive data are shifted bit-by-bit into an SCC’s Rx Shift Register. The data may or may

not have been time-demultiplexed by the IDL Interface, depending on the configuration.

When the complete character has been assembled, it is transferred to the SCC’s Rx Data

Buffer. While the next character is accumulating in the Rx Shift Register, the dedicated

Rx DMA channel fetches the character, places it in its Data FIFO Registers, and asserts

bus request to the MIF. When bus grant is given to that DMA channel, the character is

written to external memory.

DMA Data FIFOs are four bytes deep, so bus grant can be delayed for as long as five

“Byte-Times” (four bytes in DMA Data FIFO plus one byte in SCC Rx Data Buffer)

without the risk of ov er-writing d ata. Even at th e highest serial data-rates, bus grant is

normally received long before the Data FIFO fills up.

Notice that when the above process is functioning norm ally, no CPU intervention is

required.

Chapter 1: Introduction 5

Overview of XA-SCC Architecture

1.2.4 Transmit (Tx) Data Flow Simplified

The following is a typical process whereby the XA-SCC fetches data from external

memory, and transmits it via the physical layer interface:

Data to be transmitted are placed in the SCC’s Tx Data Buffer, from where they are

automatically transferred to the Tx Shift Register when it becomes available. Upon being

shifted out of the Tx Shift Register, the data may or may not be time-multiplexed by the

IDL Interface, depending on the configuration.

Each time the SCC fetches a character from its Tx Data Buffer and places it in its Tx

Shift Register, the SCC signals the DMA channel that its Tx Data Buffer is empty. While

the character is being shifted out, the DMA channel fetches the next byte from its Data

FIFO and places it in the SCC’s Tx Data Buffer. Since the DMA always fetches two bytes

from an even address in external memory, after every second byte is transferred to the

SCC, the DMA channel asserts bus request to the MIF. When bus grant is given to that

DMA channel, two more bytes are fetched from external memory and placed in the

DMA’s Data FIFO.

Bus grant can be delayed for as long as four “byte-times” (two bytes in DMA Data FIFO,

plus one byte in SCC Rx Data Buffer and one byte in SCC Tx Shift Register) without the

risk of Tx underrun (running out of data for the Tx Shift Register). Even at the highest

serial data-rates, bus grant is normally received long before four byte-times have elapsed.

Notice that when the above process is functioning norm ally, no CPU intervention is

required.

The SCCs are the subject of Chapter 5, “Serial Communications Controller (SCC),” and

the DMA is the subject of Chapter 4, “Direct Memory Access (DMA) Controller.”

1.2.5 SCC Options: Autobaud and V.54/2047

Each SCC has access to a hardware Autobaud detector and a hardware V.54/2047

transceiver.

Autobaud can be used with any SCC that is operating in Asynchronous mode. When

Autobaud is enabled for an SCC, it automa tically detects the baud rate, number of data

bits per character (7 or 8 only), and parity by searching the incoming data stream for

certain character sequences. When an Autobaud detection sequence is successfully

completed, the Autobaud circuit will program the SCC channel’s Baud Rate Generator,

and configure the SCC for 7 or 8 Data Bits, as well as Even, Odd, or No Parity. The SCC

channel will then be automatically enabled to Receive.

6Chapter 1: Introduction

Overview of XA-SCC Architecture

One of the two hardware transceivers which support the V.54/2047 line testing standards

can be attached to each SCC. During V.54/2047 line testing sequences, the V.54/2047

units send interrup ts to the CPU, and the CPU can determine the quality of the

transmissi on line by reading the V.54/2047 units’ status registers.

The Autobaud circuits are the subject of Chapter 6, “Autobaud,” and the V.54/2047

circuits are the subject of Chapter 7, “V.54/2047 Units.”

1.2.6 An Option for SCC0, SCC1, and SCC2: IDL Interface

SCC0, SCC1, and SCC2 can be internally connected to the on-chip IDL Interface, a

glueless interface to Layer One devices. Thus connected, the three SCCs efficiently

support the ISDN B1, B2, and D channels, while the IDL Interface time-multiplexes and

demultiplex e s the outgoing and inco ming serial data streams.

Other configurations are also available; an individual SCC can be assigned to both B1

and B2 Channels simultaneously.

IDL is the subject of Chapter 8, “IDL Interface.”

1.2.7 Communications Between the CPU and Off-Chip Devices:

SCP Interface

The SCP Interface provides a means for the CPU to communicate with the U-Chip, and/

or other off-chip devices, using a bidirectional, full duplex, synchronous communication

bus, similar to SPI and Microwire.

The SCP Interface is the subject of Chapter 9, “SCP Interface.”

1.2.8 Input/Output Using Multifunction Pins and Pin Function Multiplexing

The XA-SCC has 36 multifunction pins which are highly programmable. As m a ny as

four separate I/O functions might share a single pin, so pin function multiplexing allows

software to choose a particular function for a given pin. Virtually all functional blocks in

the XA-SCC use mult i fu nct ion pi n s fo r vari ou s of I/O rela te d pu rpo ses . Sin ce it wo uld be

prohibitively complex to show these signal paths in the XA-SCC Sim plified Block

Diagram (Figure 1-1), multifunction pins and pin function multiplexing have been

grouped into the “virtual functional block” labeled “Pin Function MUX.”

Multifunction pins and pin function multiplexing are the subject of Chapter 1 1, “XA-SCC

Pins.”

Chapter 1: Introduction 7

Major Fe atures of th e XA-SCC

1.3 Major Features of the XA-SCC

16-Bit XA CPU

• 30 MHz maximum clock frequency

• Separate 16 MByte Code and 16 MByte Data Address Spaces, or Unified Code/Data

Space

• Dynamic Bus Sizing, 16 or 8-bit wide Data Bus access

• 256 Bytes of Internal (On-Chip) Data Memory

• Wat chdog Timer with ou tput via Re setOut

• Two Enhanced XA Counter/Timers

• XA Interrupt Controller with 15 Maskable Ev ent Interrupts

• 32 General Pu rpo se Inp ut/ O utpu t (GP I/ O) Port p i ns , with fo ur conf i gur ati o ns avail ab le

per pin

• Enhanced instruction set, tailored for high-level lan guage support, which includes b it

intensive logic operations, and fast signed or unsigned 16 × 16 multip ly and 32 / 16

divide

• Multi-tasking features, including segmented data memory and banked registers, to

support fast context switching

Serial Communications Controllers

• Four independent, high-speed, DMA driven, full-duplex serial communication

channels

• Data rates to 4M bits / second can be sustained on all eight wires simultaneously

• Asynchronous, SDLC/HDLC, Monosync, Bisync, External Sync, and Transparent

operating modes

• Optional hardware-based automatic CRC generation and checking

• FM0, FM1, NRZ, or NRZI data encoding

• Multiple clock options

• Programmable Baud Rate Generators

• Dedicated hardware Autobaud circuit for each SCC, can service up to 921.6 Kbps

• 7/8 clock prescaler for 64K to 56K synchronous support

• Auto-Echo and Local-Loopback modes

8Chapter 1: Introduction

Maj or Features of the XA- SCC

IDL Interface

• Three SCCs can connect to the on-chip IDL Interface

• A separate SCC can be assigned to each of the time-multiplexed 2B+D channels

• Flexible IDL Interface architecture allows many alternate configurations

Memory Interface (MIF)

• Direct, glueless interface to both EDO and FPM DRAM, as well as SRAM, Flash,

EPROM, ROM, and other generic memory types

• Six Memory Banks, each with a dedicated Chip Select (CS) output

– Bank 0 (boot bank) supports generic memory, and can be Code Space, Data Space,

or both. Supports bank swapping with Bank 1

– Banks 1 - 5 support DRAM or generic memory, and can be Code Space, Data

Space, or both

• Dynamic bus sizing: Each bank can be either 8 or 16-bits wide

• DRAM controller supports DRAMs between 256 KBytes and 8 MBytes per bank, for

a total of up to 32 MBytes

• Programmable Refresh Timing, and CAS before RAS refresh generator

• Programmable bus timing

• Suppor t for external WAIT

• Intelligent Arbiter to assign bus access priorities between Refresh, DMA access, and

CPU access

Direct Memory Access (DMA) Controller

• Eight DMA channels, one dedicated to each of the four serial Rx and Tx channels

• 4-Byte FIFO Data Buffer in each channel (plus 2 bytes in each SCC)

• DMA architecture specifically designed to efficiently implement circular buffers in

external memory

– Circular buffers can be as large as 64 KBytes, greatly reducing the interrupt

response requir ements on the CPU

• DMA operating in SDLC/HDLC mode with circular buffers allows the reception and

transmission of multiple HDLC packets with no need to service interrupts on a

per-packet basis

• Urgency based dynamic prioritization for access to external memory

Chapter 1: Introduction 9

Major Fe atures of th e XA-SCC

Autobaud

• One dedicated hardware Autobaud circuit for each SCC

• Support for (asynchronous) baud rates up to 921.6 Kbps, 7 or 8 data bits, with or

without parity, when using a 29.4912 MHz system clock

• Optional Autobaud Echo mode

V.54 and 2047 Circuits

• Two independent V.54/2047 trans ceiv e rs implemented i n hard war e

• Up to two SCCs may be doing V.54/2047 line testing simultaneously

SCP Interface

• Support for as many SCP slave devices as there are available GPI/O Port pins

• Selectable inverted or n on- inverted clock polarities

• Selectable bit rates, from 1/32 to 1/4 of the system clock rate

• Selectable data frame length, from 1 to 8 bits

Memory Mapped Registers

• The control and configuration registers for most XA-SCC functions are in read/write

Memory Mapped Registers

• All MMRs are in one contiguous block of address space, 4096 bytes deep

• An individual MMR is addressed by its offset above the MMR base address

• The MMR base address is programmable

Multifunction Pins and P in Multiplexer

• On the 100-Pin LQFP Package, 36 pins have multiple functio ns

• Individual functions are chosen for each of these pins by software

– The 32 GPI/O Port bits of the XA CPU all share a Multifunction Pin with at least

one o t her function

– Some multifunction pin s use a bit in the “Pin Multiplexing Control Register” as a

function s e lect

10 Chapter 1: Introduction

Typical Applications

1.4 Typical Applications

The flexible architecture of the XA-SCC allows it to be easily configured for use in a

wide variety of applications, using either IDL, NMSI (non-multiplexed serial interface),

or both types of physical layer interface. Two of the more common applications appear

below.

1.4.1 ISDN Terminal Adapter

Figure 1-2 ISDN Terminal Adapter

The XA-SCC is well suited for ISDN terminal ad apter applications . In a typical

configurat ion, as depicted in Figur e 1-2, SCC3 would be op erat ed in As yn chro nou s mo de

and would communicate with the host PC on an RS-232 or similar serial interface. SCC0

- SCC2 would be op erating in Synchronous mode, attached to the on-chip IDL interface,

with one SCC assigned to each of the ISDN B1, B2, and D channels. The on-chip SCP

interface would be used for communication between the CPU and the physical layer

interface, such as a U-Chip or other device.

XA-SCC

SCC0

CPU SCP

SCC1

IDL Control

U-Chip

SCP (for control)

B1, B2, D

IDL Bus

Mem

RS232 or Similar

SCC2

SCC3

IDL

Demux

Mux 6

DMA,

DRAM

Controller &

MIF

Chapter 1: Introduction 11

Typica l Applic ations

As shown in Figure 1-3, receive and transmit data from each SCC would be moved in

and out of optional circular buffers in external memory by one dedicated channel of

on-chip DMA.

Figure 1-3 ISDN Terminal Adapter, showing DMA channels

XA CPU

External

Memory

DRAM

Controller

MIF

SCC3

SCC2

Tx3

Rx3

Tx2

Rx2

Tx1

Rx1

Tx0

Rx0

DMA

SCC1 IDL

SCC0

U-Chip

Async

DTE

12 Chapter 1: Introduction

Typical Applications

1.4.2 Four Independent Serial Channels

Another common application is four independent serial channels, operating

simultaneously, with each channel using a different communication protocol if desired.

This configuration is depicted in Figure 1-4.

Receive and transmit data are moved to and from optional circular buffers in external

memory by the eight dedicated DMA channels, greatly minimizing the interrupt response

requirements on the CPU.

Many applications which normally use stand-alon e UARTs or SCC devices can be

streamlined in chip-count, circuit board complexity, and overall cost by the XA-SCC’s

integrated DMA capabilities and multi-channel, multi-protocol, high-speed serial

communication options.

Figure 1-4 Four Independent Serial Channels

XA CPU

Off-Chip Memory

16 MB Program

and 16 MB Data

MIF and

DRAM

Controller

SCC3

SCC2

8 Ch

DMA

4 RX

4 TX

SCC1

SCC0 Rx

Chapter 2: XA-SCC CPU 13

Chapter 2

XA-SCC CPU 2

Contents

2.1 Introductio n..................................................................................................................................................14

2.2 Timers .........................................................................................................................................................14

2.3 Serial Ports (UARTs)...................................................................................................................................15

2.4 Event Interrupts...........................................................................................................................................15

2.5 Internal Data Memory and Addressin

Scope....................... ................................ ..................... .................15

2.6 Internal Code Memory......... ........................................................................................................................16

2.7 Memory Mapped Re

isters (MMRs) ...........................................................................................................17

2.8 ResetOut.....................................................................................................................................................18

2.9 External WAIT timin

...................................................................................................................................19

2.10 Special Function Re

ister (SFR) Modifications.........................................................................................19

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

14 Chapter 2: XA-SCC CPU

Introduction

2.1 Introduction

The XA-SCC’s on-board CPU is an 80C51XA-G3 with certain modifications. Detailed

information on the standard XA core is av ailable in the XA User Guide, Section 3 of

16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.

Detailed information o n the XA-G3 derivative is available in Section 4 of the same

publication. This chapter is primarily concerned with the differences between the

standard XA-G3, as outlined in the 16-bit 80C51XA Microcontrollers (eXtended

Architecture) Data Handbook IC25, and the CP U in the XA-SCC.

The XA-SCC CPU differs from the standard XA-G3 in these general areas:

•Timers

• Serial Ports/UARTs

• Event Interrupts

• Internal Data Memory and Addressing Scope

• Internal Code Memory

• Memory Mapped Registers

• ResetOut

• External WAIT timing

• Special Function Register Set

2.2 Timers

2.2.1 Timer/Counters

The XA-SCC has two standard 16-bit enhanced Timer/Counters, Timer 0 and Timer 1,

which function identically to their counterparts in the XA-G3. Timer 2, the XA-G3’s

additional 16-bit Up/Down Timer/Counter, has been removed from the XA-SCC.

For complete, detailed instructions on the operation of Timer 0 and Timer 1, please see

XA-G3 CMOS single-chip 16-bit microcontroller, in Section 4 of 16-Bit 80C51XA

Microcontrollers (eXtended Architecture) Data Handbook IC25.

2.2.2 Watchdog Timer

The XA-SCC Watchdog Timer subsystem is the same as that in the XA-G3. When the

Watchdog Timer underflows, it causes an XA-SCC in ternal reset. The Watchdo g Timer

will be running after any type of reset, and will continue to periodically reset the chip

unless it is either “fed” or disabled by user software. For complete details on the

Chapter 2: XA-SCC CPU 15

Serial Ports (UARTs)

Watchdog Timer, please see XA-G3 CMOS single-chip 16-bit microco ntroller, in Section

4 of 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.

2.3 Serial Ports (UARTs)

The two XA-G3 Serial Ports (UARTs ) have been removed from the XA-SCC.

2.4 Event Interrup ts

There are 15 Event Interrupts implemented in the XA-SCC. On the XA-G3, only nine

Event Interrupts are implemented. Four of the XA-SCC Event Interrupts are called “High

Priority Software Interrupts.” The High Priority Software Interrupt flag bits are set by

software, rather than by ex ternal hardware events. Nor mal XA-G3 and XA-SCC Software

Interrupts have fixed priorities between 1 and 7, but the XA-SCC High Priority Software

Interrupts can be as signed any priority from 9 to 15 and appear to the CPU as Event

Interrupts.

For details on XA-SCC interrupts, please see Chapter 10, “Interrupts.” For a complete

discussion of XA interrup ts, see both the XA User Guide and XA-G3 sections of 16-bit

80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.

2.5 Internal Data Memory and Addressing Scope

2.5.1 Internal Data Me mor y

The XA-SCC has 256 bytes of Internal Data Memory, populating addresses

000000h-0000FFh. It is possible, depending on how the Memory Interface (MIF) is

programmed, for External Data Memory to overlap this address space. In that case,

consider the following:

• DMA reads and writes at addresses 00h-FFh will always access External Data

Memory.

• CPU reads and writes at addresses 00h-FFh (using either Direct Addressing or Indirect

Addressing) will normally access Internal Data Memory.

• The CPU can access the overlapping portion of Extern al Data Memory only by using a

form of the MOVX instruction. See the XA User Guide, Section 3 of 16-Bit 80C51XA

Microcontrollers (eXtended Architecture) Data Handbook IC25, for details.

16 Chapter 2: XA-SCC CPU

Internal Code Memory

2.5.2 Data Memory Addressing Scope

The rules for accessing Internal and External Data Memory in Segment 00h (addresses

000000h - 00FFFFh) are summarized in Table 2-1.

Table 2-1 How to Access Internal and External Data Memory

2.6 Internal Code Memory

The XA-SCC has no Internal Code Memory. Therefore, External Code Memory starts at

address 000000h. See the XA User Guide, Section 3 of 16-Bit 80C51XA Microcontrollers

(eXtended Architect ure) Data Handbook IC25, for details.

A Data Memory

access to hex

address range...

using Direct

Addressing,

accesses...

using Indirect

Addressing,

accesses...

using the MOVX

Instruction,

accesses... using DMA,

accesses...

000400 - 00FFFF Not Applicable External Data

Memory External Data

Memory always!

000100 - 0003FF External Data

Memory

000000 - 0000FF Internal Data

Memory Internal Data

Memory

Note 1: SFRs are always accessed, without reference to a pointer or se

ment re

ister, with the

10-bit address encoded in instructions accessin

SFRs. See Section 2.10 for details about

XA-SCC SFRs.

Note 2: The CPU has a 4 Kbyte MMR space with a relocatable base address. All CPU Data

Memory accesses in that address space always access MMRs. Additionally, it is ille

al to map the

MMR base address to 000000h. See Section 2.7 for details about XA-SCC MMRs.

Note 3: DMA accesses are i

nored by Internal Data Memory, SFRs, and MMRs. A DMA access to

Internal Data Memory space or MMR space will access External Data Memory.

Chapter 2: XA-SCC CPU 17

Memory Mapped Registers (MMRs)

2.7 Memory Mapped Re gisters (MMRs)

The XA-SCC has a 4096 byte block of On-Chip Memory Mapped Registers, whose base

address is relocatable under software control. Most of the control and status registers for

the various XA-SCC functional blocks are Memory Mapped Registers.

All MMRs are addressed by their offset from the MMR base address. The base address is

stored in two Special Function Registers (SFRs), MRBH and MRBL. The base address is

formed by appending 12 zero bits to the concatenation of MRBH[7:0] with MRBL[7:4],

as follows:

It is illegal to map the MMR base add r ess to address 000000h.

An XA-SCC Memory Bank may be configured to overlap the same address space as the

MMRs, depending on how the Memory Interface (MIF) has been programmed. If so,

CPU reads and writes to that address space always access MMRs, while DMA reads and

writes always access the external memory. To avoid confusion, it is best not to configure

the MIF in this manner.

For more information on XA-SCC MMRs, as well as MRBH and MRBL, please see

Chapter 3, “Memory Interface (MIF) and DRAM Controller.”

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

MRBH[7:0] MRBL[7:4] 000000000000

18 Chapter 2: XA-SCC CPU

ResetOut

2.8 ResetOut

The XA-SCC has a ResetOut signal, which can be programmed to appear on Pin 58. The

purpose of ResetOut is to provide an active-low RESET pulse which responds to an

internal reset. An internal reset is caused either by Watch dog Timer underflow or by

execution of a RESET instruction.

Note that a reset pulse arriving on ResetIn does not cause a ResetOut pulse. However, a

ResetOut pulse can be generated under software control by successively writing ‘0’ then

‘1’ to P3[2]. The logic for Pin 58 is shown below, in Figure 2-1.

Figure 2-1 Lo gic for Pin 58 Showing Detail s of ResetOut

As shown in the figure, in order for the ResetOut function to drive Pin 58 the following

must be true:

1. The ResetOut function must be enabled by writing RSTSRC[7] = 1. RSTSRC is a

new SFR that has been added to the XA-SCC. See Section 2.10.10 for details.

2. P3.2 (Port 3 Bit[2]) must be configured as an output.

3. The P3[2] Output Latch must contain a one.

4. Timer 0’s output must be disabled (Timer0_Out_Disable = 1).

P3.2_Timer0_ResetOut

PIN 58

P3[2] Output Latch

ResetOut

Timer0_Out_Disable

Timer0_Out

Border of

XA-SCC Chip

PAD LOGIC

Timer0

Reset Out

Timer0_In

P3CFGB[2]

P3CFGA[2]

Watchdog Underflow

RESET Instruction

P3[2]_DataIn

RSTSRC

Digital

One Shot

Chapter 2: XA-SCC CPU 19

External WAIT timing

Conversely, the Reset Out function should be disabled by writing RstSrc[7] = 0 when

programming Pin 58 for use as an output by either GPI/O P3.2 or Timer 0.

2.8.1 Operation of Pin 58 and ResetOut During and After Power-Up

Once the initial 128 PClk cycle is ove r (where P Clk = System Clock / 2 = CClk / 2), the

ResetOut function can be enabled to appear on Pin 58 by writing RSTSRC[7] = 1. The

duration of all subsequent ResetOut pulses will be 128 PClk cycles (8.681 µsec if

CClk = 29.4912 MHz.).

If ResetOut is enabled on Pin 5 8, then ResetOut can be externally connected to ResetIn

on Pin 55. In this case, internal resets (Watchdog Timer or RESET instruction) will assert

ResetIn, and will function as external resets. With this configuration, any reset will result

in RSTSRC[2:0] = 001. For details on the RSTSRC Register, see Section 2.10.10.

2.9 External WAIT timing

The external WAIT timing of the XA-SCC differs from that of the XA-G3. For a

complete discussion of XA-SCC external WAIT, please see Section 3.7 in Chapter 3 ,

“Memory Interface (MIF) and DRAM Controller.”

2.10 Special Function Register (SFR) Modifications

For a complete discussion of XA Special Function Registers, please see the XA User

Guide, Section 3 of 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data

Handbook IC 25. For a complete list of XA-G3 Special Function Registers and their

addresses, please see XA-G3 CMOS single-chip 16-bit microcontroller, in Section 4 of

16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.

For a complete list of XA- SCC Special Function Registers and their addresses, please see

Appendix C, “SFR and MMR Addresses.”

On power-up, Pin 58 will be in an unknown (possibly low) state for the first

128 PClk cycles, where PClk is an internal clock whose frequency is equal to

half that of the System Clock, CClk. Pin 58 is the only pin with a GPI/O

function that behaves in this manner. All other GPI/O pins go high, driven by a

weak pull-up, in respons e to ResetIn.

20 Chapter 2: XA-SCC CPU

Speci al Function Registe r (SFR) Modif ication s

The XA-SCC SFR address space is 1 KBytes, populating addresses 400h-7FFh, and

constitutes a separate address space from Data Memory space. Any SFR may be accessed

at any time without reference to a pointer or segment. SFR access is independent of any

segment register, so SFRs are always accessible with the 10-bit address encoded in

instructions accessing SFRs.

SFRs may not be accessed via Indirect Addressing. Any time indirection is used, Data

Memory is accessed. If an SFR address is referenced as an indirect address, Extern al Data

Memory at that address (if it exists) is accessed. Please see Table 2-1.

Details of the changes in the XA-SCC Special Function Register set, from that of the

XA-G3, are specified below.

2.10.1 BCR (46Ah)

BCR (Bus Configuration Register) comes out of reset containing the value 00000111.

This register does not function as described in 16-bit 80C51XA Microcontrollers

(eXtended Architect ure) Data Handbook IC25, and should never be written with any

other value.

2.10.2 BTRH (469h)

BTRH (Bus Timing Register High Byte) comes out of reset containing the value FFFFh.

Upon XA-SCC reset, 01010001b = 51h must be written to this register. This register does

not function as described in 16-bit 80C51XA Microcontrollers (eXtended Architecture)

Data Handbook IC25, and should never be written with any other value.

2.10.3 BTRL (468h )

BTRL (Bus Timing Register Low Byte) comes out of reset containing the value EFh.

Upon XA-SCC reset, 01000000b = 40h must be written to this register. This register does

not function as described in 16-bit 80C51XA Microcontrollers (eXtended Architecture)

Data Handbook IC25, and should never be written with any other value.

2.10.4 MRBL (496h)

MRBL (Memory Mapped Registers Base Address Low Byte) is a new register, which has

been added to the XA-SCC. Please see Section 2.7 Memory Mapped Registers (MMRs)

or Section 3.11 MIF Special Function Register Descriptions.

Warning! BTRH and BTRL do not function as described in 16-bit 80C51XA

Microcontrollers (eXtended Architecture) Data Handbook IC25, and must be written

with the values 51h and 40h respectively. Furthermore, it is recommended that BTRH

be initialized first, then BTRL, followed by at least five NOPS .

Chapter 2: XA-SCC CPU 21
Special Fu nction  Register  (SFR) M odifica tions
2
2.10.5 MRBH (497h)
MRBH (Memory Mapped Registers Base Address High Byte) is a new register, which 
has been added to the XA-SCC. Please see Section 2.7 Memory Mapped Registers 
(MMRs) or Section 3.11 MIF Special  Function Register Descriptions.
2.10.6 MICFG (499 h)
MICFG (Memory Interface General Configuration) is a new register, which has been 
added to the XA-SCC. Please see Section 3.11 MIF Special Function Register 
Descriptions.
2.10.7 IPA6 (4A6h)
IPA6 (Interrupt Priority 6) is a new register, which has been added to the XA-SCC. It 
contains the Interrupt Priority fields for the Event Interrupts “HSWR1” and “HSWR0,” 
two of the new High Priority Software Interrupts. Please see Section 1 0.4 Hig h Priority  
Software Interrupts.
2.10.8 IPA7 (4A7h)
IPA7 (Interrupt Priority 7) is a new register, which has been added to the XA-SCC. It 
contains the Interrupt Priority fields for the Event Interrupts “HSWR3” and “HSWR2,” 
two of the new High Priority Software Interrupts. Please see Section 1 0.4 Hig h Priority  
Software Interrupts.
2.10.9 PCON (404h)
PCON (Power Control Register), as in the XA-G3, contains only two functional bits 
PCON[1] and PCON[0]. Setting these bits activates Power Down and Idle modes, 
respectively.
2.10.10 RSTSRC (463h)
RSTSRC (Reset Source) is a new register, which has been added to the XA-SCC. There 
are four functional bits in this register, which are discussed below.
If there is DRAM in the system, activating Power Down mode by settin g PCON[1] = 1 
will halt refresh, resulting in loss of data.

22 Chapter 2: XA-SCC CPU

Speci al Function Registe r (SFR) Modif ication s

RSTSRC[7] - ROEN (Reset Out Enable)

RSTSRC Bit[7] enables or disables the ResetOut function. For details on ResetOut,

please see Section 2.8 ResetOut.

RSTSRC[2:0] - [R_WD R_CMD R_EXT]

RSTSRC Bits[2:0] reflect the cause of the last XA-SCC reset. After a reset, one of these

three bits will be se t to one, and the other bits will be zero.

2.10.11 XA-G3 SFRs Which Have Been Removed From the XA-SCC

S0CON, S0STAT, S0BUF, S0ADDR, S0ADEN (Serial Port 0 removed)

S1CON, S1STAT, S1BUF, S1ADDR, S1ADEN (Serial Port 1 removed)

T2CON, T2MOD, TH2, TL2, T2CAPH, T2CAPL (Timer 2 removed)

0 ResetOut disabled.

1 ResetOut enabled.

100 Reset was due to Watchdog Timer underflow.

010 Reset was due to execution of RESET instruction.

001 Reset was external, due to R esetIn.

Chapter 3: Memory Interface (MIF) and DRAM Controller 23

Chapter 3

Memor

Interface

(

MIF

)

and DRAM

Controller 3

Contents

3.1 Introduction..................................................................................................................................................24

3.2 MIF Architecture..........................................................................................................................................24

3.3 MIF Memory Banks.....................................................................................................................................27

3.4 Generic Memory Interface...........................................................................................................................34

3.5 DRAM Interface...........................................................................................................................................34

3.6 DRAM Refresh............................................................................................................................................37

3.7 WAIT and Size8 ..........................................................................................................................................38

3.8 MIF Arbiter...................................................................................................................................................41

3.9 XA-SCC Memory Mappe d Re

ister Relocation ..........................................................................................42

3.10 MIF Confi

uration Example........ ............................................................................................................... 42

3.11 MIF Special Function Re

ister Descriptions ............................................................................................. 50

3.12 MIF Memory Mapped Re

ister Descriptions.............................................................................................52

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

24 Chapter 3: Memory Interface (MIF) and DRAM Controller

Introduction

3.1 Introduction

The XA-SCC Memory Interface (MIF) allows up to six external memory devices to

interface directly to the XA-SCC using no external glue logic. Five of the six banks can

be DRAM, and all six banks can be configured as Code Memory, Data Memory, or both.

The size and base address for each bank is individually programmable.

The MIF provides automatic DRAM refresh with programmable timing, individually

programmable Read/Write bus cycle timing for each bank, and support for external

WAIT states. Also built into the MIF is an Intelligent Arbiter, which arbitrates bus grants

between the eight XA-SCC DMA channels, the CPU, and the DRAM refresh generator.

The XA-SCC DRAM Controller and MIF support:

• Fast Page Mode and EDO DRAM, with automatic refresh.

• DRAMs from 256K bytes to 4M words (8M bytes).

• Generic memory interface. Memory types, such as SRAM, Flash, ROM, EPROM, etc.

can be mixed.

• Up to six memory banks with unified code and data address spaces.

• Individual Chip Select pins for each bank eliminate the need for external glue logic.

• Dynamic bus sizing (8 or 16-bit wide data bus for each bank).

• Programmable bus timing, on a bank-by-bank basis.

• Timing ge nerator.

• Intelligent arbiter assigns priorities between refresh, CPU access, and DMA access.

•External WAIT.

• Bank 0 / Bank 1 Swap, for booting from ROM or Flash, and executing from RAM.

• Relocatable Memory Mapped Register (MMR) space.

3.2 MIF Architecture

3.2.1 MIF Block Diagram

The following discussion relates to the MIF Block Diagram, Figure 3-1.

The individual Chip Select (CS) pin for each Memory Bank is physically connected to

the memory device(s) dedicated to that bank, usually via the RAS pin on DRAM

packages or the CS pin on SRAM and ROM packages. The Chip Select Decoder

compares the most significant address bits of all memory addresses to the base addresses

of the six Memory Banks (including Code space and Data space qualifiers), and asserts

the CS pin for that bank which matches. Never more than the 12 most significant bits

Chapter 3: Memory Interface (MIF) and DRAM Controller 25

MIF Architecture

need be compared, since all memory bank base addresses are on 4 KByte boundaries,

hence their 12 least significant bits are zero.

Memory addresses from the CPU and the eight DMA channels, are multiplexed

(selected) onto the Address Bus, under control of the Arbiter. DRAM logical address bits

a22-a0 are multiplexed onto address pins A17-A6 during the row and column phases by

the Row/Column Address MUX (see Table 3-6 and Table 3-7). Generic memory (SRAM,

ROM, etc.) logical addresses, a19-a0, appear on address pins A19-A0 directly.

The correct Read/Write bus cycle timing for each bank, which has been programmed into

that bank’s Timing Register (BiTMG), is applied via the Timing Generator whenever the

bank is selected. Optionally, an External WAIT signal can be used to extend bus cycle

timing.

Figure 3-1 M IF Block Diagra m (showing addre ss and strobe generatio n only)

Chip Select

Decoder

Row/Column

Address

Generator

Arbiter

DRAM Refresh

Timer

CS5-CS0

Control

WAIT

CPU Request

CPU Address (24 bits)

DMA Address (24 bits)

CPU Grant

DMA Request

Refresh Request

DMA Grant

BLE, BHE, OE, WE

WAIT

A19-A18, A5-A0

A17-A6*

a23-a0 a23-a12

*a22-a0 are multiplexed

onto pins A17-A6 during

various DRAM CAS cycles.

Address

Select

Timing

Generator

26 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Archite c t ur e

3.2.2 MIF Register Set

The MIF uses five Special Function Registers (BTRH, BTRL, MRBH, MRBL, and

MICFG) and twenty Memory Mapped Registers (MBCL, BiCFG, BiAM, BiTMG, and

RFSH). The index “i” is used to reference any of the MIF Memory Banks 0 - 5.

Warning! BTRH and BTRL do not functi on as described in 16-bit 80C51XA

Microcontrollers (eXtended Architecture) Data Handbook IC25 and must be written

with the values 51h and 40h respectively. Also, never write to the BCR register. It is

preloaded at Reset with 07h, the only legal value. Any change to this value will cause

system malfunctions.

Table 3-1 MIF Register Set

BTRH

(Bus Timi n

ister Hi

h Byte) Comes out of reset confi

ured for slowest bus speed. Before

pro

rammin

any other re

isters, 01010001b = 51h must be

written to this SFR. See Section 3.11.1 on pa

e 50.

BTRL

(Bus Timi n

ister Low Byte) Comes out of reset confi

ured for slowest bus speed. Before

pro

rammin

any other re

isters, 01000000b = 40h must be

written to this SFR. See Section 3.11.2 on pa

e 50.

MRBH

(Memory Mapped Re

ister Base Address Hi

h) Contains address bits a23-a16 of the base address for the 4

KByte Memory Mapped Re

ister space. See Section 3.9 on pa

42.

MRBL

(Memory Mapped Re

ister Base Address Low) Contains address bits a15-a12 of the base address for the 4

KByte Memory Mapped Re

ister space. See Section 3.9 on pa

42.

MICFG

(Memory Interface General Confi

uration) Contains the CLKOUT Enable bit. See Section 3.11.5 on pa

51.

MBCL

(Memory Bank Confi

uration Lock) Contains the bits for lockin

and unlockin

the BiCFG Re

isters.

See Section 3.12.4 on pa

e 58.

BiCFG

(Bank i Confi

uration) Contains the size, type, bus width, and enable bits for Memory

Bank i. See Section 3.12.1 on pa

e 52.

BiAM

(Bank i Base Address/DRAM Address

Multiplexer Control)

Contains the base address bits and DRAM address multiplex

control bits for Memory Bank i. See Section 3.12.2 on pa

e 55.

BiTMG

(Bank i Timin

)Contains the timin

control bits for Memory Bank i. See Section

3.12.3 on pa

e 55.

RFSH

(Refresh Timin

)Contains the refresh time constant and DRAM Refresh Timer

enable bit. See Section 3.12.5 on pa

e 59.

Chapter 3: Memory Interface (MIF) and DRAM Controller 27

MIF Memory Banks

3.3 MIF Memory B anks

The XA-SCC supports six memory banks, Banks 0 through 5. The MIF provides an

individual Chip Select pin for each bank (CS0 through CS5), allo wing for a gluel ess

interface to external memory. Each memory bank can be independently enabled for either

Code memory access (Harvard Architecture Code space), Data memory access (Harvard

Architecture Data space), or both (Von Neuman Architecture).

If a memory bank is configured for both Code and Data Memory access, the same

address range is used for both. Bank i (i = 0...5) is selected (CSi asserted) if logical

address bits a23-a12 (fewer for banks larger than 4K) match that bank’s base address,

AND the type of access (Code or Data) matches that bank’s Code/Data enable qualifier.

Bank sizes range from 4 KBytes to 8 MBytes, so logical address bits a11-a0 are not

compared.

Two memo ry banks can be assigned to the same address range, on the condition that one

is enabled for Code access only, and the other for Data access only (Harvard

Architecture). In that case, only processor Code fetches (PSEN = 0) in that address range

will activate the CS pin for the Code enabled memory bank. All DMA reads and writes,

as well as processor Data memory accesses (PSEN = 1) in that addr ess range will activate

the CS pin for the Data enabled memory bank.

The XA-G3 core has 256 bytes of internal Data RAM which occupy addresses

000000h - 0000FFh. If a memory bank is configured to overlap this address range, with

Data memory access enabled, CPU Data reads and writes using direct or indirect

addressing will still be directed to the internal RAM. The CPU can access the

overlapping portion of External Data Memory only by using a form of the MOVX

instruction. See th e XA Us er Guide, Section 3 of 16-Bit 80C51XA Microcontrollers

(eXtended Architect ure) Data Handbook IC25, for details. DMA reads and writes at

addresses 000000h-0000FFh will always access External Data Memory (if populated).

Banks 1-5 can be either DRAM Interfaces (Fast Page Mode or EDO DRAM), or Generic

Memory Interfaces (SRAM, ROM, EPROM, Flash, etc.). B ank 0 can only be a Generic

Memory Interface.

Burst reads are supported on Code Memory reads only. Burst reads are not supported for

Data Memory accesses, and burst is never used during Write cycles. However, both word

reads and word writes on an 8-bit bus will access 2 consecutive bytes.

Warning! Never configure two banks such that they will respond to the same

memory access. The only configuration in which overlapping address ranges

are permitted, is when one b ank is Code only, and the other is Data only.

28 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Memory Banks

Code Memory accesses to sequential addresses, with address bits a23-a4 in common, are

made with burst reads. Burst reads cannot be interrupted by DRAM Refresh Request,

DMA, or CPU bus request. The longest burst is 16 bytes.

A hardware reset configures Bank 0 into a known state. The processor, which initially

executes code from Bank 0, can later configure all the bank s as needed. The routine for

configuring and initializing a memory bank typically proceeds as follows:

• Configure the bank’s base address (BiAM Register).

• Configure the bank’s size (BiCFG Register).

• Configure the bank’s memory interface type, Generic or DRAM (BiCFG Register).

• Configure the bank’s bus timing parameters (BiTMG Register).

MIF Memory Banks can be up to 8 MBytes in size. Physical addressing for Generic

Memory is limited to 20 bits (A19-A0), so there can be as many as six Generic Memory

Banks, each up to 1 MByte in size. Physical addressing for DRAM provides A22-A0, so

DRAM banks can be up to 8 MBytes in size.

3.3.1 Bank 0

Bank 0 is the boot bank and cannot be configured fo r use as a DRAM Interface. It is

forced by hardw are into the Generic Memory Interface configuration. Upon hardware

reset, code execution begins from Bank 0, so the boot-up sequence (typically in Flash or

ROM) must be in physical memory connected to CS0. However, Bank 0 supports both

code and data memory accesses in support of the “Bank 0 / Bank 1 Swapping” feature.

See Section 3.3.3 on page 31.

Other important features of Bank 0.

• The base address for Bank 0 is hard wired to 000000h.

• Bank 0 has a minimum bank size of 64 K bytes. 32K byte (or smaller) memory can be

used, but the entire 64K byte address space will be occupied.

• Bank 0 is always en abled f or code memor y access and can be en abled for data memory

access.

• Bus width for Bank 0 is determined during a hardware reset (described below) and

cannot be changed by the processor.

Chapter 3: Memory Interface (MIF) and DRAM Controller 29

MIF Memory Banks

State of Bank 0 after a hardware reset

• B0CFG = 8Fh = [1 0 0 0 1 1 1 1]. The interpretation of these bit values is descr i bed

below.

– Code memory access is enabled (B0CFG[7] = 1 is hard wired).

– Data memory access is disabled (B0CFG[6] = 0). No write can occur until th is bit is

reconfigured.

– Bus width is determined by the state of the WAIT_Size8 pin (Pin 52) immediately

after the rising edge of ResetIn (B0CFG[5] = don’t care for Bank 0). If

WAIT_Size8 = 1, the Bank 0 bus width will be 8 bits. If WAIT_Size8 = 0, the bus

width will be 16 bits. See Sectio n 3.7.3 for details on the Size8 function.

– Bank 0 is configured as Generic Memory (B0CFG[4] = 0 is hard wired).

– Bank 0 size is 8 MBytes with address range from 000000h to 7FFFFFh

(B0CFG[3:0] = 1111, with B0CFG[3] = 1 hard wired).

• B0TMG = 7Ah = [0 1 1 1 1 0 1 0]. The interpretation of these bit values is described

below.

– Write de la y is disable d ( B0TMG[7] = 0).

– One cycle delay from CS0 to BLE/BHE (B0TMG[6] = 1).

– Access T ime (BLE /BHE low to BLE/BHE high) is 7 + 1 = 8 cycles

(B0TMG[5:3] = 111).

– Two cycle minimum delay (Recovery Time) from CS0 high to CS0 low again

(B0TMG[2:1] = 01).

–BLE

/BHE are normal data strobes, not converted to WEL/WEH (B0TMG[0] = 0).

After reset, Bank 0 can be configured to 64 KBytes - 8 MBytes, as shown in Table 3-2.

The size and address range are determined by the 4-bit field B0CFG[3:0]. Note, however,

that B0CFG[3] is hard wired to logic one.

Table 3-2 Bank 0 Size and Address Range Select

B0CFG[3] B0CFG[2] B0CFG[1] B0CFG[0] Bank 0 Size Bank 0 Address Range

100064K Bytes000000h - 00FFFFh

1001128K Bytes000000h - 01FFFFh

1010256K Bytes000000h - 03FFFFh

1011512KBytes 000000h - 07FFFFh

11001M Bytes000000h - 0FFFFFh

11012M Bytes000000h - 1FFFFFh

11104M Bytes000000h - 3FFFFFh

11118M Bytes000000h - 7FFFFFh

30 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Memory Banks

3.3.2 Banks 1 - 5

Banks 1 throug h 5 can be con figu red as either Gener ic memory or DR AM interfaces. The

size of each bank can be 4K, 8K, ... , 8 MBytes, and the base address for each bank is

programmable.

For Bank i (i = 1...5), the size is determined by the 4-bit field BiCFG[3:0].

If the size chosen for Bank i is either 4K, 8K, 16K, or 32K Bytes, then Bank i resides in

the same segment (A23-A16) as the Memory Mapped Registers. In this case, the Bank i

base address is formed as follows:

If the size chosen for Bank i is 64 KBytes or greater, then the Bank i base address is

formed as follows:

In both cases, low order bits in the BiAM register that are less significant than the bank

size selected, are ignored in forming the base address. Bank size and base address

formation is summarized in Table 3-3.

Table 3-3 Banks 1-5 Size and Base Address Select

a23-a16 a15-a12 a11-a8 a7-a0

MRBH[7:0] BiAM[7:4] 0h 00h

a23-a16 a15-a12 a11-a8 a7-a0

BiAM[7:0] 0h 0h 00h

BiCFG[3:0] Bank Size

Logical Address Bi t

a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11-a0

00xx Reserved

0100 4 KBytes MRB23 MRB22 MRB21 MRB20 MRB19 MRB18 MRB17 MRB16 Bi AM7 BiAM6 BiAM5 BiAM4 0

0101 8 KBytes MRB23 MRB22 MRB21 MRB20 MRB19 MRB18 MRB17 MRB16 Bi AM7 BiAM6 BiAM5 0 0

0110 16 KBytes MRB23 MRB22 MRB21 MRB20 MRB19 MRB18 MRB17 MRB16 BiAM7 BiAM6 0 0 0

0111 32 KBytes MRB23 MRB22 MRB21 MRB20 MRB19 MRB18 MRB17 MRB16 BiAM7 0 0 0 0

1000 64 KBytes BiAM7 BiAM6 BiAM5 BiAM4 BiAM3 BiAM2 BiAM1 BiAM0 0 0 0 0 0

1001 128 KBytes BiAM7 BiAM6 BiAM5 BiAM4 BiAM3 BiAM2 BiAM1 0 0 0 0 0 0

1010 256 KBytes BiAM7 BiAM6 BiAM5 BiAM4 BiAM3 BiAM2 0 0 0 0 0 0 0

1011 512 KBytes BiAM7 BiAM6 BiAM5 BiAM 4 BiAM3 0 0 0 0 0 0 0 0

1100 1 MBytes BiAM7 BiAM6 BiAM5 BiAM4 0 0 0 0 0 0 0 0 0

1101 2 MBytes BiAM7 BiAM6 BiAM5 0 0 0 0 0 0 0 0 0 0

1110 4 MBytesBiAM7BiAM600000000000

1111 8 MBytesBiAM7000000000000

Chapter 3: Memory Interface (MIF) and DRAM Controller 31

MIF Memory Banks

Note that DRAMs smaller than 256 KBytes are not supported, so only Generic Memory

Interface banks can be configured for sizes 128 KBytes and below.

Example: Configure Bank 5 for 256 KByte size with base address = 380000h.

• Write 1010b to B5CFG[3:0] (B5MS3-B5MS0). Chooses 256 KByte size.

• Write 001110xx to B5AM[7:0] (B5AM7-B5AM0). Sets base address to 380000h.

Notice that bits B5AM[1:0] are ignored in this case and zeros are used in forming the

base address.

3.3.3 Bank 0 / Bank 1 Swapping

For many applications, Bank 0 will be Flash or ROM-based boot code, and Bank 1 will

be DRAM or SRAM. After boot-up, the application code will be written into the DRAM

(or SRAM) for subsequent execution. The application code can be executed from the

DRAM (or SRAM), but with a base address of 000000h, if the DRAM (or SRAM) is

remapped to Memory Bank 0, using Bank 0 / Bank 1 Swapping.

After Bank 0 / Bank 1 Swapping, accesses to Bank 0 address space (including Code

space and Data space qualifiers) will activate CS1, with Bank 1 timing. Conversely,

accesses to Bank 1 address space (including Code space and Data space qualifiers) will

activate CS0, with Bank 0 timin g.

The selection of Bank 0 is still determined by the address range chosen for Bank 0

(B0CFG[3:0]) , and the Code and Data memo ry enables chosen for Bank 0 ( B0CFG[ 7:6]) .

The base address for Bank 0 remains 000000h. Similarly, the selection of Bank 1 is still

determined by the address range chosen for Bank 1 (B1CFG[3:0]), and the Code and

Data memory enables chosen for Bank 1 (B1CFG[7:6]). The base address chosen for

Bank 1 remain s th e sa me.

Bank 0 / Bank 1 Swapping allows the interrupt vectors, which are in low memory

between 000000h and 00011Bh, to be write accessed. It also allows an 8 MByte DRAM

bank to be based at 000000h. Bank 0 / Bank 1 Swapping can only take place the next

time a non-burst, even-byte or word access occurs.

32 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Memory Banks

Example: Assume CS0 is physically connected to a 128K x 8 ROM, and CS1 is

connected to a 256K x 16 DRAM. The following sequence typifies the use of Bank 0 /

Bank 1 Swappin g.

• On reset, Bank 0 will have address range 000000h - 7FFFFFh, and Bank 1 will be

disabled.

• Unlock the Configuration Locks for Banks 0 and 1 in the MBCL Register.

• Change Bank 0 size to 128 KBytes.

• Configure Bank 1 size to 512 KBytes (256K x 16), Bank 1 base address to 400000h

(which yields address range 400000h - 47FFFFh), Bank 1 timing as required by the

physical DRAM, and enable both code and data accesses for Bank 1.

• Configure refres h time r and enable refresh.

• Move code to the DRAM in Bank 1.

• Change Bank 1 size to 128 KBytes (the size of the ROM).

• Change Bank 0 size to 512 KBytes (256K x 16, the size of the DRAM) and enable

both code and data accesses for Bank 0.

• Swap Banks 0 and 1 (write a one to MBCL[7]) and lock the Configuration Locks for

Banks 0 and 1 in the MBCL Register.

Now, the address range for Bank 0 is 000000h - 07FFFFh (base address 000000h and

size 512 KBytes), but accesses to Bank 0 will be redirected to the DRAM via

CS1_RAS1.

The address range for Bank 1 is now 400000h - 41FFFFh (bas e address 400000h and

size 128 KBytes), but accesses to Bank 1 will be redirected to the ROM via CS0.

• Code still executes from Bank 0 (low mem ory), but physically from the DRAM via

CS1_RAS1.

The Bus Width, Memory Type, and Bus Timing control bits for the physical memory

attached to CS0 are always in the Bank 0 Register set. Similarly, the Bus Width, Memory

Type, and Bus T iming con tr ol bits for the physical memory attached to CS1 are always in

the Bank 1 Register set. Those control bits which “swap” (relate to their own CS before

the swap, and the other CS after the swap) are summarized in Table 3-4 for the case of

DRAM attached to CS1, and in Table 3-5 for the case of Generic Memory attached to

CS1.

Chapter 3: Memory Interface (MIF) and DRAM Controller 33

MIF Memory Banks

There are two very important items of note in Table 3-4:

1. The two least significant bits of the Bank 1 base address after the swap (which will

activate CS0), will always be 00, regardless of the values previously stored in

B1AM[1:0]. If B1AM1 and B1AM0 were relevant bits in forming the Bank 1 base

address before the swap (see the “64K Bytes” and “128K Bytes” rows in Table 3 -3),

then the base address after the swap could be different from that which was

programmed.

2. The shaded row in Table 3-4 shows that the Address Multiplexer contro l bits for the

DRAM connected to CS1 are always B1AM[1:0] = B1MX1 B1MX0.

Table 3-4 CS0 (ROM) and CS1 (DRAM) Control Bits Before and After Swapping

Table 3-5 CS0 (ROM) and CS1 (Generic) Control Bits Before and After Swapping

Parameter

Control bits for accessing the physical memory connected to

CS0 (ROM ) CS1 (DRAM) CS0 (ROM ) CS1 (DRAM)

Before Swapping After Swapping

Code Memory

Enable B0CFG[7] B1CFG[7] B1CFG[7] B0CFG[7]

Data Memory Enable B0CFG[6] B1CFG[6] B1CFG[6] B0CFG[6]

Size B0CFG[3:0] B1CFG[3:0] B1CFG[3:0] B0CFG[3:0]

Base Address bits B0AM[7:0]

hard wired to

00000000 B1AM[7:0] B1AM[7:2][00] B0AM[7:0]

hard wired to

00000000

DRAM Address Mul-

tiplexer control bits not applicable B1AM[1:0] not applicable B1AM[1:0]

Parameter

Control bits for accessing the physical memory connected to

CS0 (ROM ) CS1 (Generic) CS0 (ROM) CS1 (Generic)

Before Swapping After Swapping

Code Memory

Enable B0CFG[7] B1CFG[7] B1CFG[7] B0CFG[7]

Data Memory Enable B0CFG[6] B1CFG[6] B1CFG[6] B0CFG[6]

Size B0CFG[3:0] B1CFG[3:0] B1CFG[3:0] B0CFG[3:0]

Base Address bits B0AM[7:0]

hard wired to

00000000 B1AM[7:0] B1AM[7:0] B0AM[7:0]

hard wired to

00000000

34 Chapter 3: Memory Interface (MIF) and DRAM Controller

Generic Memory Interface

3.4 Generic Memory Interface

Each of the six memory banks can be configured as a Generic Memory Interface, by

clearing the BiTYP bit in that bank’s Bank Configuration Register (BiTYP = BiCFG[4]).

A Generic Memory Interface bank can be used to interface with external ROM, EPROM,

EEPROM, Flash Memory, SRAM, and most peripheral I/O chips.

3.4.1 Generic Memory Interface Addressing

For banks configured as Generic Memory Interfaces, BiAM[7:0] hold values relevant to

forming the base address for the bank. See Sections 3.3.1 and 3.3.2. for details.

• The base address is hard wired to 000000h for Bank 0.

• The base address is given in Table 3-3 for Banks 1-5 (logical addresses a19-a0 appear

on address pin s A19-A0).

3.4.2 Generic Memory Interface Timing

The Timing Configuration Registers (BiTMG) for Banks 1, 2, 3, 4, 5 must be configured

before the corr esponding banks are enabled for code or data accesses. Bank 0 comes out

of a hardware reset containing the value 7Ah, which sets up the access times to their

maximum, and can be reconfigured later by the processor. All changes in timing

configuration occur AFTER the current access cycle is over.

For Generic Memory Interface banks, the bit functions in the BiTMG Register differ

from those for DR AM Interface B ank s. The bit fun ctions for both ty pes of mem ory b ank s

are detailed in Section 3 .12.3.

For timing examples which demonstrate how the bits in the BiTMG Register affect a

Generic Memory Interface Bank’s read and write timing, see Appendix B, “Bus Timing

Examples.”

3.5 DRAM In terface

MIF Memory Banks 1-5 can be configured as DRAM Interfaces, by setting the BiTYP

bit in that bank’s Bank Configuration Register (BiTYP = BiCFG[4]). Ba nk 0 cannot be

configured as a DRAM Interface.

3.5.1 DRAM Burst Reads

Burst reads are supported for Code Memory accesses only. Burst reads are not supported

for Data Memory reads, and burst is never used during write cycles (except for a word

write on an 8-bit bus).

Chapter 3: Memory Interface (MIF) and DRAM Controller 35

DRAM Interface

Code Memory accesses to sequential addresses, with address bits a23-a4 in common, are

made with burst reads. Burst reads cannot be interrupted by DRAM Refresh Request,

DMA or CPU bus request. The longest burst is 16 bytes.

Fast Page Mode (FPM) and EDO DRAM burst reads differ only in regard to the ClkOut

cycle when the Data Bus is sampled (See Section 3.5.3 DRAM Interface Timing for

details).

3.5.2 DRAM Interface Addressing

For banks configured as DRAM Interfaces, the bank’s Address Multiplexer Control

bank. See Sections 3.3.1 and 3.3.2. for details.

• The base address is hard wired to 000000h for Bank 0.

• The method for assigning the base add ress for Ba nks 1 - 5, is given in Table 3 -3.

BiAM[1:0] are the Row/C olumn Address Multiplexer Control Bits, BiMX1 and BiMX0,

respectively. These bits must be configured for the specific physical DRAM to be used.

The choices for BiMX1 and BiMX0 are based on the number of Bytes in the DRAM, and

the bus width to be used for that bank. Configuration of BiMX1 and BiMX0 is

summarized in Table 3-6.

Table 3-6 BiMX1 and BiMX0 Configuration

The row and column address multiplexing scheme implemented during the RAS and

CAS cycles of a DRAM access is dependent on the states of BiMX1 and BiMX0, as well

as the Data Bus Width. The assignment of logical addresses a23-a0 to pins A17-A6

during the row and column address phases of a DRAM access are shown in Table 3-7.

FPM DRAM The data bus is sampled on the risin

e of ClkOut whil e BLE/BHE (CAS) is

active.

EDO DRAM The data bus is sampled on the next risin

e of ClkOut after BLE/BHE

(CAS) has been ne

ated.

Data Bus Width Number of Bytes BiMX1 BiMX0 Address Mux Scheme

8-Bit Bus 256 KBytes 00 A

1 MBytes 01 B

4 MBytes 10 C

8 MBytes 11 D

16-Bit Bus 256K deep (512 KBytes total) 00 E

1M deep (2 MBytes total) 01 F

4M deep (8 MBytes total) 10 G

Reserved 11 -

36 Chapter 3: Memory Interface (MIF) and DRAM Controller

DRAM Interface

Note that Address pins A23-A18 and A5-A0 are not used during DRAM access, and that

“u” denotes unused pins for the corresponding address phase.

Table 3-7 DRAM Row and Column Address Multiplexing

3.5.3 DRAM Interface Ti ming

The Timing Configuration Registers (BiTMG) for Banks 1, 2, 3, 4, 5 must be configured

before the corr esponding banks are enabled for code or data accesses. Bank 0 comes out

of a hardware reset containing the value 7Ah, which sets up the access times to their

maximum, and can be reconfigured later by the processor. All changes in timing

configuration can only occur AFTER the current access cycle is over.

Bank 0 / Bank 1 Swapping can only take place the next time a non-burst even-byte or

word access occurs.

For DRAM Interface banks, the bit definitions in the BiTMG Register differ from those

for Generic Memory Interface Banks. The bit functions for both types of MIF Memory

Banks are detailed in Section 3.12.3.

Address

Mux

Scheme

Address Pin

A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6

Arow a17 a16 a15 a14 a13 a12 a11 a10 a9 u u u

column a8 a7 a6 a5 a4 a3 a2 a1 a0 u u u

Brow a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 u u

column a18 a7 a6 a5 a4 a3 a2 a1 a0 a19 u u

Crow a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 u

column a18 a20 a6 a5 a4 a3 a2 a1 a0 a19 a21 u

Drow a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6

column a18 a20 a22 a5 a4 a3 a2 a1 a0 a19 a21 u

Erow a17 a16 a15 a14 a13 a12 a11 a10 a9 u u u

column a8 a7 a6 a5 a4 a3 a2 a1 a18 u u u

Frow a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 u u

column a19 a7 a6 a5 a4 a3 a2 a1 a18 a20 u u

Grow a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 u

column a19 a21 a6 a5 a4 a3 a2 a1 a18 a20 a22 u

Note 1. Use Table 3-6 to determine Address Mux Scheme and [BiMX1 BiM X0] values.

Note 2. Durin

RAS, the lo

ical address and the address pin are always identical.

Chapter 3: Memory Interface (MIF) and DRAM Controller 37

DRAM Refresh

Note: For DRAM Interface Banks, the value 000 can not be used for the Bank’s Access

Time. That is BiAC[5:3] = BiAC2 BiAC1 BiAC0 can assume only the binary values 001

through 111.

For timing examples which demonstrate how the bits in the BiTMG Register affect a

DRAM Interface Bank’s read and write timing, please see Appendix B, “Bus Timing

Examples.”

3.6 DRAM Refr esh

The XA-SCC only supports CAS before RAS refresh. The interval separating DRAM

refresh cycles is timed by the MIF’s Refresh Timer. The time-out interval is programmed

into bits [6:0] of the Refresh Timing Register (RFSH[6:0]), and th e tim e r wil l tim e out

once every 8 × RFSH[6:0] system clock cycles. On each Refresh Timer time out, a

Refresh Request is sent to the Arbiter. The Arbiter always assigns the highest priority to a

Refresh Request. However, DRAM burst accesses (Fast Page Mode and EDO Page

Mode) will not be interrupted by a refresh. The maximum burst is 16 bytes.

The Refresh Timer is enabled by setting RFSH[7] to one. RFSH[7] is cleared by a

hardware reset, disabling the Refresh Timer, so that code can execute from the boot

memory (Bank 0) without interference from Refresh Requests. The Refresh Timer must

be programmed and enabled before the first access to any DRAM Interface memory

banks. If no memory banks are configured as DRAM Interfaces, the R efresh Timer

should remain disabled.

DRAM refresh cannot be disabled during Idle mode, if there are any banks configured as

DRAM Interfaces. In Power-Down mode, with no clock present, no refresh is possible

and data will b e los t.

3.6.1 DRAM Refresh Cycle Ti ming

All banks configured as DRAM Interfaces are refreshed simultaneously. The duration of

the refresh RAS cycle is determined by the values stored in B5CBL and B5AC0 in the

B5TMG Register (B5TMG[6] and B5TMG[3] respectively). The Recovery Time is

specified by the values stored in B5EC1 and B5EC0 (B5TMG[2:1]). No bus accesses can

occur until the Refresh Recovery Time elapse s, when the Refresh Request is removed.

Refresh RAS and Rec overy timing are always determined by thes e bit s in the B5TM G Register,

regardless of wheth er CS5 is actual ly being used. If there are any banks configured as DRAM

Interfaces, Bank 5 must be one of them. If there are multiple DRAM banks, Bank 5 must be the

slowest DRAM bank.

38 Chapter 3: Memory Interface (MIF) and DRAM Controller

WA IT and Size8

The timing diagram below (Figure 3-2) demonstrates a typical DRAM Refresh cycle, in

which the following occurs:

1. BLE and BHE (CASL and CASH) are asserted with WE and OE negated.

2. One ClkOut cycle later CSi (RASi) is asserted for all memory banks configured as

DRAM Interfaces.

3. B5CBL + B5AC0 + 3 ClkOut cycles after the falling edge of CSi (RASi), all CSi

(RASi) and BLE /BHE (CASL/CASH) are negated.

4. The two-bit field in B5TMG[1:0] [BiEC1 BiEC0] determin es the Recovery Time for

the Refresh Cycle. The case shown is 4 ClkOut cycles Recovery Time, or

B5TMG[1:0] = [BiEC1 BiEC0] = 11.

Figure 3-2 DRAM Refresh Cycle

3.7 WAIT and Size8

3.7.1 WAIT

External circuitry can extend the bus cycle of a memory ban k by pulling the WAIT_Size8

pin (pin 52) high. However, external WAIT states will only have an effect on memory

banks which are configured as Generic Memory Interfaces. Bus accesses by memory

banks configured as DRAM Interfaces will not be affected by the state of WAIT_Size8.

When a memory bank is accessed, internal wait states might or might not be generated,

depending on the state of that bank’s BiTMG Register . Additional external wait states can

be inserted by holding WAIT_Size8 high, but the bank’s BiEC1 Bi EC0 = BiTMG[2:1]

must be set to 00 to enable the external WAIT feature.

The WAIT_Size8 pin can be used as DTACK with a 68000 type of device.

ClkOut

12345678910

B5CBL+B5AC0+3 Cycles

CS (RAS)

BLE/BHE (CAS)

[B5EC1:B5EC0]+1 Cycles

Chapter 3: Memory Interface (MIF) and DRAM Controller 39

WAIT and Size8

XA- SCC WA IT differs from XA-G3 WAIT. For deta ils on X A-G3 WAIT, please see

XA-G3 CMOS single-chip 16-bit microcontroller, in Section 4 of 16-Bit 80C51XA

Microcontrollers (eXtended Architecture) Data Handbook IC25.

3.7.2 External WAIT Timing

WAIT_Size8 is sampled on the rising edge of ClkOut. WAIT_Size8 must go high before

the rising edge of the ClkOut cycle that triggers the assertion of BLE/BHE. The

termination of the external WAI T begins on the rising edge of ClkOut when the

WAIT_Size8 pin is sampled as a zero. The next rising edge of ClkOut triggers the

negation of all strobes and chip selects, and the bus cycle is complete.

A typical Generic Memory Interface bus cycle with two external wait states is shown in

Figure 3-3. The bus cycle proceeds as follows:

1. Sample WAIT_Size8 = 1, insert WAIT state.

2. Sample WAIT_Size8 = 1, insert WAIT state.

3. Sample WAIT_Size8 = 0, terminate bus cycle on the next rising edge of ClkOut.

4. Bus cycle is complete.

Figure 3-3 External WAIT States

3.7.3 Size8

The state of the WAIT_Size8 pin (Pin 52) immediately after reset (when ResetIn goes

high) det ermi n es th e dat a b us widt h of Mem ory Bank 0 , t he boo t ban k. L ogic ‘0’ selects a

16-bit data bus, and logic ‘1’ selects 8-bit. The Bank 0 bus width selected MUST match

the bus width of the boot ROM (or Flash, etc.) memory being used.

WAIT_Size8 will be sam pled during the first ten CClk (system clock) cycles after

ResetIn goes high, and so the logic state of Pin 52 must remain unchanged during that

time. Later, external circuitry can use Pin 52 as the external WAIT input, as described in

Sections 3.7.1 and 3.7.2 above.

ClkOut

123

34567

BLE/BHE

WAIT

40 Chapter 3: Memory Interface (MIF) and DRAM Controller

WA IT and Size8

For a given appli cation, the external circuitry connected to Pin 52 will normally be

designed for one of the four following scenarios:

1. Boot ROM is 16 bits wide, external WAIT function not used.

2. Boot ROM is 8 bits wide, external WAIT function not used.

3. Boot ROM is 16 bits wide, external WAIT function is used.

4. Boot ROM is 8 bits wide, external WAIT function is used.

A typical circuit for each of these cases appears in Figure 3-4.

Figure 3-4 Ty pical circuits for WAIT_Size8 pin

The simplest and least expensive way to implement the 10 or more CClk delay shown in

cases 2, 3, and 4 is with a simple RC circuit. The important point is that the logic state of

the WAIT_Size8 pin (Pin 52) must remain unchanged for at least ten CClks after the

rising edge of ResetIn.

Minimum Delay

10 CClks

Case 1: Boot ROM is 16 bits wide, and WAIT function NOT used. Case 2: Boot ROM is 8 bits wide, and WAIT function NOT used.

ResetIn Pin 55

Pin 52

GND

ResetIn

WAIT_Size8

Reset

Pin 55

Pin 52

Minimum Delay

10 CClks

Case 3: Boot ROM is 16 bits wide, and WAIT function IS used. Case 4: Boot ROM is 8 bits wide, and WAIT function IS used.

ResetIn

WAIT_Size8

Pin 55

Pin 52

Minimum Delay

10 CClks

ResetIn

WAIT_Size8

WAIT WAIT

Pin 55

Pin 52

Chapter 3: Memory Interface (MIF) and DRAM Controller 41

MIF Arbiter

3.8 MIF Arbiter

The MIF Arbiter arbitrates bus grants between DRAM Refresh (assuming at least one

memory bank is configured as a DRAM interface), CPU bus access, and DMA bus

access. If no memory banks are configured as DRAM interfaces, the refresh timer should

be turned off by writing 00h to the RFSH Register.

If a Refresh Request, a DMA bus request, and a CPU bus request are all pending at the

same time, the Refresh Request always has the highest priority for the next bus access.

Any burst access currently in progress will not be interrupted by a refresh. The Arbiter

prioritization sch e me is shown in the follow ing table.

Table 3-8 MIF Arbiter Priority Rankings

3.8.1 DMA Channel High Pri ority Override (DMA CHPO)

When a DMA channel is in greater than normal need of bus access, it asserts its DMA

High Priority signal to the MIF Arbiter. The Arbiter then g iv es that DMA channel a High

Priority Override, and that channel’s priority becomes second only to DRAM Refresh.

Tx DMA channels assert their High Priority signal when there is only one (or no) valid

byte remaining in the channel’s Data FIFO registers. Rx DMA channels assert their High

Priority signal when there are three valid bytes waiting in th e chan nel’s DATA FIFO

Registers.

Current Access Prioritization of Next Access

CPU Refresh (hi

hest)

DMA (lower)

CPU (lowest)

DMA Refresh (hi

hest)

DMA CHPO (lower)

CPU (lower still)

DMA (lowest)

Refresh DMA CHPO (hi

hest)

DMA (lower)

CPU (lowest)

42 Chapter 3: Memory Interface (MIF) and DRAM Controller

XA-SCC Memory Mapped Register Relocation

3.9 XA-SCC Memory Mapped Register Relocation

3.9.1 MRBH and MRBL

The Memory Mapped Registers of the XA-SCC can be located anywhere in the 24-bit

address space, with the base address for the MMR space always on a 4 KByte address

boundary. Memory Mapped Registers are addressed by their offset from the base address.

The base address for the XA-SCC MMRs is stored in two Special Function Registers

(SFRs), MRBH (address 497h) and MRBL (address 496h). The MMR base address is

formed by appending 12 zero bits to the concatenation of MR BH[7:0] with MRBL[7:4],

as follows:

Formation of the Memory Mapped Register (MMR) Base Address

MRBH[7:0] MRBL[7:4] are compared to A23-A12 from the CPU to initiate MMR

accesses. DMA cannot access the MMRs. The least significant bit of MRBL is called

MRBE. A zero in MRBE disables access to MMRs and a one in MRBE enables access.

3.10 MIF Configuration Example

This example demonstrates the procedure for assigning, initializing, enabling, and bank

swapping th e X A -S CC MIF in the following configuration (see Figu re 3-5):

• 128K x 8, 200ns Boot ROM attached to CS0.

• 256K x 16, FPM DRAM (HM514260DI Series, 70ns access time, 8ms 512 cycle

refresh) attached to CS1, for swapping with Bank 0.

• 1M x 16, FPM DRAM (MT4C1M16C3, 60ns access time, 16ms 1024 cycle refresh)

for general purpose use, attached to CS2.

• 2K x 16 SRAM (20ns access time) attached to CS3.

• The frequency of CClk and ClkOut is 29.4912 MHz.

• Memory Mapped Register (MMR) Space will be located in address range FFF000h -

FFFFFFh.

• Boot Code resides in ROM (CS0). App lication code will be loaded into the Bank 1

DRAM (CS1), and will be executed from the DRAM with base address 000000h after

swapping.

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

MRBH[7:0] MRBL[7:4] 000000000000

On reset, MRBE is cleared and access to MMRs is disabled.

Chapter 3: Memory Interface (MIF) and DRAM Controller 43

MIF Co nfigur ation Ex ample

Figure 3-5 Interconnections for MIF Configuration Example

Banks 0 and 1 will first be configured as follows (initial setup, before swappin g):

Bank Memory Type Size Address Range Remarks

0 ROM 128K x 8 000000h - 01FFFFh This address ran

e activates

ROM on CS0.

1 DRAM 256K x 16 100000h - 17FFFFh This address ran

e activates

DRAM on CS1.

RAS

CASL

CASH

A8-A0

D15-D0

XA-SCC

128K x 8 ROM

256K x 16 FPM DRAM

(HM514260DI)

1M x 16 FPM DRAM

(MT4C1M16C3)

2K x 16 SRAM

RAS

CASL

CASH

A9-A0

D15-D0

BLE

BHE

A15-A1

D15-D0

A16-A0

D7-D0

D15-D0

A17-A9

A16-A0

CS0

CS1

CS2

A17-A8

A15-A1

CS3

BLE

BHE

A21-A19

D15-D0

44 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Con figu ration Exa mpl e

The final state of the MIF, after all banks have been configured and Bank 0 / Bank 1

Swapping has been executed, will be as follows:

Configur at ion Sequence:

• Execute hardware reset with WAIT_Size8 (Pin 52) pulled high to ensure a logic ‘1’

(even though Pin 52 has a weak internal pull-up). As a result, Memory Bank 0 is

configured to 8-bit bus width during reset. Pin 52 can be used as the External WAIT

input later.

• Program the MIF SFRs:

MMR Base Address High Byte. Write MRBH = FFh.

MMR Base Address Low Byte, and Enable. Write MRBL = F1h.

• Do not update the MICFG SFR. Leave ClkOut enabled.

• Unlock Configuration, Base Address, and Timing Registers for Banks 0 - 3.

Memory Bank Configuration Lock Register. Write MBCL = 30h.

Bank Memory Type Size Address Range Remarks

1 unchan

ed 128K x 8 100000h - 11FFFFh This address ran

e activates

ROM on CS0.

0 unchan

ed 256K x 16 000000h - 07FFFFh This address ran

e activates

DRAM on CS1.

2 DRAM 1M x 16 200000h - 3FFFFFh 60ns FPM DRAM on CS2.

3SRAM

(or other Generic)

2K x 16 FFE000h - FFEFFFh Less than 64K Bytes, must be

in same data se

ment as

MMRs. T wo-cycle access time,

on CS3.

(unused)

-- - -

5 DRAM Don’t care Don’t care Refresh timin

confi

uration.

MRBH Bits Value(s) Comment(s)

MRBH[7:0] 11111111 MMR Base Address bits a23-a16.

MRBL Bits Value(s) Comment(s)

MRBL[7:4] (MRB15-MRB12) 1111 Base address bits a15-a12.

MRBL[3:1] xxx Don’t care, use 000 for example.

MRBL[0] (MRBE) 1 Enable MMR access.

MBCL Bit(s) Value(s) Comment(s)

MBCL[7] (SWP01) 0 Do not swap yet.

MBCL[6] 0 Reserved.

MBCL[5:4] 11 Lock re

isters for banks 5 and 4.

MBCL[3:0] 0000 Unlock re

isters for Banks 3 - 0.

Chapter 3: Memory Interface (MIF) and DRAM Controller 45

MIF Co nfigur ation Ex ample

• Configure Bank 0:

Bank 0 Timing Register. Write B0TMG = 28h.

Bank 0 Configuration Register. Write B0CFG = 89h.

B0TMG Bit(s) Value(s) Comment(s)

B0TMG[7] (B0RWT) 0 Not applicable for ROM.

B0TMG[6] (B0CBL) 0 No CS to BLE/BHE delay.

B0TMG[5:3] (B0AC2-B0AC0) 101 Access Time = 5+1 = 6 cycles = 204ns for 200ns ROM.

B0TMG[2:1] (B0EC1-B0EC0) 0 Recovery Time = 2 clock cycles, shortest possible.

B0TMG[0] (B0WEX) 0 Not applicable for ROM.

B0CFG Bit(s) Value(s) Comment(s)

B0CFG[7] (B0CE) 1 H ardwired to ’1’ for Bank 0. Code accesses always

enabled.

B0CFG[6] (B0DE) 0 Data accesses disabled.

B0CFG[5] (B0BW) 0 Not applicable for Bank 0.

B0CFG[4] (B0TYP) 0 Hardwired to ’0’ for Bank 0. Must be Generic Memory

Interface.

B0CFG[3:0]

(B0MS3-B0MS0) 1001 Size = 128 Kbytes, from Table 3-2.

46 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Con figu ration Exa mpl e

• Configure Bank 1:

Bank 1 Timi ng Register. Write B1TMG = 08h .

Bank 1 Configuration Register. Write B1CFG = FBh.

Bank 1 Base Address/DRAM Address Mux. Control Reg. Write B1A M = 10h.

B1TMG Bit(s) Value(s) Comment(s)

B1TMG[7] (B1RWT) 0 FPM DRAM.

B1TMG[6] (B1CBL) 0 Two cycle (68ns) RAS-to-CAS delay, shortest possible.

B1TMG[5:3] (B1AC2-B1AC0) 001 Two cycle (68ns) delay from data strobes low to

samplin

of the data bus or latchin

data into memory,

shortest possible.

B1TMG[2:1] (B1EC1-B1EC0) 00 Two- cycle (68ns) Recovery (RAS prechar

e) Time,

shortest possible.

B1TMG[0] (B1WEX) 0 BLE/BHE used as CASL/CASH (not as WEL/WEH).

B1CFG Bit(s) Value(s) Comment(s)

B1CFG[7] (B1CE) 1 Code accesses enabled.

B1CFG[6] (B1DE) 1 Data accesses enabled.

B1CFG[5] (B1BW) 1 16-bit bus width.

B1CFG[4] (B1TYP) 1 DRAM Interface.

B1CFG[3:0]

(B1MS3-B1MS0) 1011 Size 512 Kbytes (256 Kwords), from Table 3-3.

B1AM Bit(s) Value(s) Comment(s)

B1AM[7:3] 00010 Base address for Bank 1 = 100000h. B1AM bits [7:3] =

a23-a19 of base address. See Table 3-3.

B1AM[2] 0 When formin

the base address for Bank 1 with size

512 Kbytes, hardware will use a ‘0’ for a18, i

norin

the

value in this bit position. See Table 3-3.

B1AM[1:0] (B1MX1-B1MX0) 00 Address multiplexin

for 256K x 16 DRAM. Address

Mux Scheme E, see Table 3-6.

Chapter 3: Memory Interface (MIF) and DRAM Controller 47

MIF Co nfigur ation Ex ample

• Configure Bank 2:

Bank 2 Timing Register. Write B2TMG = 08h.

Bank 2 Configuration Register. Write B2CFG = FDh.

Bank 2 Base Address/DRAM Address Mux Control Reg. Write B2AM = 21h.

B2TMG Bit(s) Value(s) Comment(s)

B2TMG[7] (B2RWT) 0 FPM DRAM.

B2TMG[6] (B2CBL) 0 Two cycle (68ns) RAS-to-CAS delay, shortest possible.

B2TMG[5:3] (B2AC2-B2AC0) 001 Two cycle (68ns) delay from data strobes low to

samplin

of the data bus or latchin

data into memory,

shortest possible.

B2TMG[2:1] (B2EC1-B2EC0) 00 Two-cycle (68ns) Recovery (RAS prechar

e) Time,

shortest possible.

B2TMG[0] (B2WEX) 0 BLE/BHE used as CAS L/CASH (not as WEL/WEH).

B2CFG Bit(s) Value(s) Comment(s)

B2CFG[7] (B2CE) 1 Code accesses enabled.

B2CFG[6] (B2DE) 1 Data accesses enabled.

B2CFG[5] (B2BW) 1 16-bit bus width.

B2CFG[4] (B2TYP) 1 DRAM Interface.

B2CFG[3:0]

(B2MS3-B2MS0) 1101 Size 2 Mbytes (1 Mwords), from Table 3-3.

B2AM Bit(s) Value(s) Comment(s)

B2AM[7:5] 001 Base address for Bank 2 = 200000h. B2AM bits [7:5] =

a23-a21 of base address. See Table 3-3.

B2AM[4:2] 000 When formin

the base address for Bank 2 with size 2

Mbytes, hardware will use zeros for a20-a18, i

norin

the values in these bit positions. See Table 3-3.

B2AM[1:0] (B2MX1-B2MX0) 01 Addr ess multiplexin

for 1M x 16 DRAM. Address Mux

Scheme F, see Table 3-6.

48 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Con figu ration Exa mpl e

• Configure Bank 3:

Bank 3 Timing Register. Write B3TMG = 48h.

Bank 3 Configuration Register. Write B3CFG = 64h.

Bank 3 Base Address/DRAM Address Mux Control Reg. Write B3AM = E0h.

• Banks 4 and 5 will no t be enabled. However, the refresh timing configuration needs to

be programmed in Bank 5 (B5TMG). Bank 5 timing must be configured the same as

the slowest DRAM Bank, which is Ba nk 1. So configure B5TMG the same as

B1TMG.

Bank 5 Timing Register. Write B5TMG = 08h.

B3TMG Bit(s) Value(s) Comment

B3TMG[7] (B3RWT) 0 WE asserted same cycle as CS.

B3TMG[6] (B3CBL) 1 BLE/BHE asserted one cycle after CS.

B3TMG[5:3] (B3AC2-B3AC0) 001 CS, BL E /BHE ne

ated two cycles after the assertion of

BLE/BHE.

B3TMG[2:1] (B3EC1-B3EC0) 00 Minimum two cycle (68ns) CS hi

h time.

B3TMG[0] (B3WEX) 0 BLE/BHE not used as WEL/WEH.

B3CFG Bit(s) Value(s) Comment(s)

B3CFG[7] (B3CE) 0 Code accesses disabled.

B3CFG[6] (B3DE) 1 Data accesses enabled.

B3CFG[5] (B3BW) 1 16-bit bus width.

B3CFG[4] (B3TYP) 0 Generic Memory Interface.

B3CFG[3:0]

(B3MS3-B3MS0) 0100 Size 4 Kbytes (2 Kwords), from Table 3-3.

B3AM Bit(s) Value(s) Comment

B3AM[7:4] 1110 Because Bank 3 is smaller than 64 Kbytes, the base

address is formed by concatenatin

MRBH[7:0]B3AM[7:4][0h][00h] = FFE000h. See Section

3.3.2 on pa

e 30.

B3AM[3:0] 0000 Not used.

B5TMG Bit(s) Value(s) Comment(s)

B5TMG[7] (B5RWT) 0 FPM DRAM.

B5TMG[6] (B5CBL) 0 Two cycle (68ns) RAS-to-CAS delay, shortest possible.

B5TMG[5:3] (B5AC2-B5AC0) 001 Two cycles (68ns) delay from data strobes low to

samplin

of the data bus or latchin

data into memory,

shortest possible.

B5TMG[2:1] (B5EC1-B5EC0) 00 Two-cycle (68ns) Recovery (RAS prechar

e) Time,

shortest possible.

B5TMG[0] (B5WEX) 0 BLE/BHE used as CAS L/CASH (not as WEL/WEH).

Chapter 3: Memory Interface (MIF) and DRAM Controller 49

MIF Co nfigur ation Ex ample

• Configure the Refresh Timing Register. The two DRAMs have the same refresh cycle

timing requirement (8ms/512 = 16ms/1024 = 15.625 µs). If they were different, we

would have to choose the shortest cycle. In that case, all DRAM Banks would be

refreshed at the rate required by the bank which needs refresh most often.

In this case, 15.625 µs = 460.8 ClkOut cycles at 29.4912 MHz. Therefore, the refresh

timer shou ld time out at a rate equal t o or fast er than 46 0.8 ClkOut cycl es, but we must

choose a multiple of 8. Since 8 × 57 = 456 is the largest multiple of 8 less than 460. 8,

let RFSH[6:0] = 57 (decim a l).

Refresh Timing Register. Write RFSH = B9h.

• Do wnload the application program, and any other data, to the DRAM in Ba nk 1.

• Now get ready to execute Bank 0 / Bank 1 Swapping. Change the size of Bank 1 to

128 Kbytes (the physical size of the ROM), and change the size of Bank 0 to 512

Kbytes (the physical size of the DRAM). Enable Data Memory Access for Bank 0

(which will be the DRAM on CS1).

Bank 1 Configuration Register. Write B1CFG = F9h .

Bank 0 Configuration Register. Write B0CFG = CBh .

RFSH Bit(s) Value(s) Comment(s)

RFSH[7] (RFEN) 1 Refresh enabled.

RFSH[6:0] (RFTM6-RFTM0) 0111001 0111001 = 57 (decimal).

B1CFG Bit(s) Value(s) Comment(s)

B1CFG[7] (B1CE) 1 Code accesses enabled, same as before.

B1CFG[6] (B1DE) 1 Data accesses enabled, same as before.

B1CFG[5] (B1BW) 1 16-bit bus width.

B1CFG[4] (B1TYP) 1 DRAM Interface.

B1CFG[3:0]

(B1MS3-B1MS0) 1001 Size 128K Bytes, from Table 3-3. Address ran

100000h - 11FFFFh redirected to ROM via CS0.

B0CFG Bit(s) Value Comment

B0CFG[7] (B0CE) 1 Hardwired to ’1’ for Bank 0. Code accesses always

enabled.

B0CFG[6] (B0DE) 1 Data accesses enabled.

B0CFG[5] (B0BW) 0 Not applicable for Bank 0.

B0CFG[4] (B0TYP) 0 Hardwired to ’0’ for Bank 0. Must be Generic Memory

Interface.

B0CFG[3:0]

(B0MS3-B0MS0) 1011 Size 512K Bytes, from Table 3-2. Address ran

000000h - 07FFFFh redirected to DRAM via CS1.

50 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Special Function Register Descriptions

• Execute Bank 0 / Bank 1 Swap, while simultaneously locking all Memory Bank

Configuration, Base Address, and Timing Registers.

Memory Bank Configuration Lock Registe r. Write MBCL = BFh.

• Banks 0 and 1 will swap immediately (the next time a non-burst even-byte or word

access occurs) after the SWP01 bit is set. Memory accesses to Bank 0 address space

(including Code and Data enable qualifiers for Bank 0) will be redirected to the

DRAM via CS1, using the DRAM’s timing as configured in the Bank 1 Timing

qualifiers for Bank 1) will be redirected to the ROM via CS0, using the ROM’s timing

as configured in the Bank 0 Timing Register.

3.11 MIF Special Function R egister Descriptions

3.11.1 BTRH: Bus Timing Register High Byte (SFR 469h)

BTRH (Bus Timing Register High Byte) comes out of reset containing the value FFFFh.

Before programming any other MIF registers, 01010001b = 51h must be written to this

(eXtended Architect ure) Data Handbook IC25, and should never be written with any

other value.

3.11.2 BTRL: Bus Timing Register Low Byte (SFR 468h)

BTRL (Bus Timing Register Low Byte) comes out of reset containing the value EFh.

Before programming any other MIF registers, 01000000b = 40h must be written to this

(eXtended Architect ure) Data Handbook IC25, and should never be written with any

other value.

MBCL Bit(s) Value(s) Comment(s)

MBCL[7] (SWP01) 1 Swap Banks 0 and 1.

MBCL[6] 0 Reserved.

MBCL[5:4] 11 Lock re

isters for banks 5 and 4.

MBCL[3:0] 1111 Lock re

isters for Banks 3 - 0.

Warning! BTRH and BTRL do not function as described in 16 -bit 80 C 51 XA Mic r oc on tr ol ler s

(eXtended Architecture) Data Handbook IC25, and must be written with the values 51h and 40h

respectively. Furthermore, it is recommended that BTRH b e initialized first, then BTRL,

followed by at least five NOPS.

Chapter 3: Memory Interface (MIF) and DRAM Controller 51

MIF Special Function Register Descriptions

3.11.3 MRBH: MMR Base Address High Byte (SFR 497h)

MRBH contains the high order byte of the MMR base address: Address bits A23-A16.

The register res ets to 0Fh.

3.11.4 MRBL: MMR Base Address Low Byte (SFR 496h)

MRBL contains the lowest 4 bits of the MMR base address: Address bits A15-A12.

Bit[0] of MRBL is called MRBE. A zero in MR BE disabl es access to MMRs and a one in

MRBE enables access. On reset, MRBE is cleared and access to MMRs is disabled. The

MRBL register resets to F0h.

The MMR base address is formed as follows:

MRBH[7:0] MRBL[7:4] are compared to a23-a12 from the CPU to initiate MMR

accesses. DMA cannot access the MMRs.

3.11.5 MICFG: Memory Interface Configuration (SFR 499h)

MICFG[0] - CLKOE (ClkOut Enable)

The MICFG Register contains only on e functional bit, bit 0, which is called CLKOE

(ClkOut Enab le). I f an I n-C ircuit Em ulator is being used , Cl kOut must rem ain en abled, as

emulators use this clock.

The reset value of CLKOE is 1, ClkOut enabled.

76543210

MRB23 MRB22 MRB21 MRB20 MRB18 MRB18 MRB17 MRB16

76543210

MRB15 MRB14 MRB13 MRB12 x x x MRBE

a23 a16 a15 a12 a11 a8 a7 a0

MRBH[7:0] MRBL[7:4] 000000000000

76543210

xxxxxxxCLKOE

0 ClkOut disabled.

1 ClkOut enabled.

52 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Memory Mapped Register Descriptions

3.12 MIF Memory Mapped Register Descriptions

3.12.1 BiCFG: Bank i Configuration

BiCFG[7] - BiCE ( Bank i Co de Mem ory En able)

This bit determines whether the corresponding Memory Bank is enabled for Code

Memory access (code space, read enabled).

This bit is hard wired to one for Bank 0, and resets to zero for Bank s 1 - 5.

BiCFG[6] - BiDE ( Bank i Da ta Mem ory En able )

This bit determines whether the corresponding Memory Bank is enabled for Data

Memory access (data space, write enabled). This bit resets to zero for Banks 0 - 5.

BiCFG[5] - BiBW (Bank i Bus Width)

This bit determines the data bus width for the corresponding Memory Bank.

This bit has no effect on Bank 0, whose data bus width is determined by the state of Pin

52 immediately after the rising edge of ResetIn. This bit resets to zero for Banks 1 - 5.

76543210

BiCE BiDE BiBW BiTYP BiMS3 BiMS2 BiMS1 BiMS0

0 Code Memory access disabled.

1 Code Memory access enabled.

0 Data memory access disabled.

1 Data memory access enabled.

0 8-bit data bus.

1 16-bit data bus.

Chapter 3: Memory Interface (MIF) and DRAM Controller 53

MIF M emory Map ped Re gister D escr iptions

BiCFG[4] - BiTYP ( Ba nk i Type)

This bit determines whether the corresponding Memory Bank is configured as a Generic

Memory Interface, or DRAM Interface.

This bit is hard wired to zero for Bank 0, and resets to zero for Banks 1 - 5.

0 Generic Memory Interface.

1 DRAM I nterf ace.

54 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Memory Mapped Register Descriptions

BiCFG[3:0] - BiMS3 BiMS2 Bi MS1 BiMS0 ( Bank i Memory Size)

This four-bit field determines the size of Memory Bank 0 and Banks 1-5 as shown in the

two tables below. Note that B0CFG[3] is hard wired to ‘1’, so Bank 0 must be 64 Kbytes

or greater.

B0CFG[3:0] Bank 0 Size

1000 64K Bytes

1001 128K Bytes

1010 256K Bytes

1011 512KBytes

1100 1M Bytes

1101 2M Bytes

1110 4M Bytes

1111 8M Bytes

BiCFG[3:0] Banks 1 - 5 Size

00xx Reserved

0100 4K Bytes

0101 8K Bytes

0110 16K Bytes

0111 32K Bytes

1000 64K Bytes

1001 128K Bytes

1010 256K Bytes

1011 512KBytes

1100 1M Bytes

1101 2M Bytes

1110 4M Bytes

1111 8M Bytes

Chapter 3: Memory Interface (MIF) and DRAM Controller 55

MIF M emory Map ped Re gister D escr iptions

3.12.2 BiAM: Bank i Base Address/DRAM Address Multiplexer Control

BiAM[7:0]

These bits have different functions depending on the memory interface type and memory

size.

• Generic Memory Interface of size 64K Bytes or larger

BiAM7 - BiAM0 form th e most significant byte (a23-a16) of the base address for the

memory bank. In this case, the Bank i base address is formed as follows:

• Generic Memory Interface of size 32K Bytes or smaller

BiAM7 - BiAM4 are used as address bits a15-a12 of the base address for the memory

bank. In this case, Bank i resides in the same segment (A23-A16) as the Memory

Mapped Registers, and the Bank i base address is formed as follows:

• DRAM Interface

BiAM7 - BiAM2 are used as address bits a23-a18 of the base address for the memory

bank. BiAM1 and BiAM0 are the row/column address multiplexer control bits BiMX1

and BiMX0 (see Section 3.5.2. for details).

3.12.3 BiTMG: Bank i Timing

Please refer to the timing examples in Appendix B, “Bus Timing Examples,” in reference

to the following bit descriptions.

76543210

BiAM7 BiAM6 BiAM5 BiAM4 BiAM3 BiAM2 BiAM1 BiAM0

a23-a16 a15-a12 a11-a8 a7-a0

MRBH[7:0] BiAM[7:4] 0h 00h

a23-a16 a15-a12 a11-a8 a7-a0

BiAM[7:0] 0h 0h 00h

76543210

BiRWT BiCBL BiAC2 BiAC1 BiAC0 BiWEX

2-cycle (not 1) minimum Recovery Time

2-cycle minimum Recovery Time

3-cycle minimum Recovery Time

4-cycle minimum Recovery Time

56 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Memory Mapped Register Descriptions

BiTMG[7] - BiRWT (Bank i Rea d/Write Timing)

• For DRAM Interface Banks - Fast Page Mode or EDO DRAM

For DRAM Interface Banks, if BiRWT = 0 then FPM DRAM is selected, and the Data

Bus is sampled (for a Read) on the clock cycle before BLE/BHE (C ASL/CASH) go

high (see Figure B-22). If BiRWT = 1 then EDO DRAM is selected, and the Read data

are sampled on the clock cycle after BLE/BHE (CASL/CASH) go high, except on the

last Read of the Burst (see Figure B-26).

• For Generic Memory Interface Banks - CS to WE delay.

For Generic memory interface banks, if BiRWT = 0, then the WE signal (and BLE/

BHE if they have been converted to WEL/WEH by setting BiWEX = 1) is asserted on

the same clock cycle as CSi (see Figure B-5). If BiRWT = 1, then the WE signal (and

BLE/BHE if they have been converted to WEL/WEH) is asserted one clock cycle

after CSi (see Figure B-9).

BiTMG[6] - BiCBL (Bank i CS to BLE/BHE delay)

• For DRAM Interface Banks - RAS to CAS del ay

For DRAM Interface Banks, if BiCBL = 0 then BLE/BHE (CASL/CASH) are asserted

2 clock cycles after CSi (RASi ). If BiCBL = 1 then BLE/BHE (CASL /CASH) are

asserted 3 clock cycles after (CSi) RASi.

• For Generic Memory Interface Banks - CS to BLE delay

For Generic memory interface banks, if BiCBL = 0 then BLE/BHE are asserted on the

same clock cycle as CSi. If BiCBL = 1 then BLE/BHE are asserted one clock cycle

after CSi.

0 Selects FPM (Fast Pa

e Mode) DRAM

1 Selects EDO DRAM

0 No delay

1 1 clock cycle delay

0 2 clock cycle delay

1 3 clock cycle delay

0 No delay

1 1 clock cycle delay

Chapter 3: Memory Interface (MIF) and DRAM Controller 57

MIF M emory Map ped Re gister D escr iptions

BiTMG[5:3] - Bi AC2 BiA C1 Bi AC0 (Ban k i BLE/BHE Access Time)

The code written to this three-bit field specifies the duration of the interval from the

assertion of the data strobes (BLE/BHE) to the latching of data into memory (Write), or

sampling of the Data Bus (Read). The duration of the interval will be th e number of clock

cycles specified by the binary number in these three bits, plus one. See Figure B-2 and

Figure B-6 for the effects of Access Time on Generic Memory, and see Figure B-24 and

Figure B-28 for the effects on DRAM.

Code 000 is reserved for DRAM Interface banks and therefore should never be used.

BiTMG[2:1] - Bi EC1 B iEC0 ( Ba nk i Recover y Time)

•For DRAM interface banks. The code written to this bit field s pecifies the shortest

allowable interval that can elapse between the rising edge of RASi (CSi) at the end of

one read or write cycle, and the next falling edge of RASi (CSi) at the beginning of the

next read or write cycle.

•For Generic memory interface banks. The code written to this bit field specifies the

shortest allowable interval that can elapse between the rising edge of CSi (at the end

of one read or write cycle) and the next falling edge of CSi (at the beginning of the

next read or write cycle).

000 1 clock cycle (Don’t use)

001 2 clock cycles

010 3 clock cycles

011 4 clock cycles

100 5 clock cycles

101 6 clock cycles

110 7 clock cycles

111 8 clock cycles

00 2 (sic) clock cycles (enables WAIT input for

eneric accesses)

01 2 clock cycles

10 3 clock cycles

11 4 clock cycles

58 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Memory Mapped Register Descriptions

BiTMG[0] - BiWEX (B ank i B LE /BHE Conversion to WEL/WEH)

• For DRAM Interface Banks

For DRAM Interface banks, BiTMG[0] is reserved and must remain 0.

• For Generic Memory Interface Banks

For Generic memory interface banks, if BiWEX = 0 then BLE and BHE are the

normal data strobes. If BiWEX = 1 then (externally) BLE is converted to WEL, and

(externally) BHE is converted to WEH. In this case, BLE and BHE will only go active

during writes, for this bank (see Figure B-15).

3.12.4 MBCL: Memory Bank Configuration Lock

MBCL [7] - SWP01 (Swap Banks 0 and 1)

This bit resets to 0.

MBCL [6] - Reserved

MBCL [5] - MBCL5 (Memor y Bank 5 C onfig uratio n Lo ck)

This bit resets to 1.

MBCL [4] - MBCL4 (Memor y Bank 4 C onfig uratio n Lo ck)

Same as MBCL[5], but for Memory Bank 4.

MBCL [3] - MBCL3 (Memor y Bank 3 C onfig uratio n Lo ck)

Same as MBCL[5], but for Memory Bank 3.

76543210

SWP01 Rsvd MBCL5 MBCL4 MBCL3 MBCL2 MBCL1 MBCL0

0 Disable Bank 0 / Bank 1 Swappin

1 Enable Bank 0 / Bank 1 Swappin

0 Memory Bank 5 Confi

uration, Base Address, and Timin

isters (B5CFG,

B5AM, and B5TMG) are unlocked, and can be chan

ed by writin

to these

isters.

1 Memory Bank 5 Confi

uration, Base Address, and Timin

isters (B5CFG,

B5AM, and B5TMG) are locked. Writin

to these re

isters will have no effect

when locked.

Chapter 3: Memory Interface (MIF) and DRAM Controller 59

MIF M emory Map ped Re gister D escr iptions

MBCL [2] - MBCL2 (Memor y Bank 2 C onfig uratio n Lo ck)

Same as MBCL[5], but for Memory Bank 2.

MBCL [1] - MBCL1 (Memor y Bank 1 C onfig uratio n Lo ck)

Same as MBCL[5], but for Memory Bank 1.

MBCL [0] - MBCL0 (Memor y Bank 0 C onfig uratio n Lo ck)

Same as MBCL[5], but for Memory Bank 0.

3.12.5 RFSH: Refresh Timing

RFSH[7 ] - RFEN (Ref resh E nabl e)

This bit resets to zero.

RFSH[6 :0] - RFTM6 through R FT M0

The seven-bit time constant for the Refresh Timer is stored in this bit field. The timer will

time out once every 8 × RFSH[6:0] system clock cycles. On each Refresh Timer time out,

a Refresh Request is sent to the Arbiter.

These bits reset to zero.

76543210

RFEN RFTM6 RFTM5 RFTM4 RFTM3 RFTM2 RFTM1 RFTM0

0 Disable Refresh Timer

1 Enable Refresh Timer

60 Chapter 3: Memory Interface (MIF) and DRAM Controller

MIF Memory Mapped Register Descriptions

Chapter 4: Direct Memory Access (DMA) Controller 61

Chapter 4

Direct Memor

Access

(

DMA

)

Controller 4

Contents

4.1 Introductio n..................................................................................................................................................62

4.2 DMA Channel Architecture..........................................................................................................................62

4.3 Data Buffer Mana

ement in Main Memory..................................................................................................63

4.4 Serial Transmit DMA T ransfer Process (Tx DMA) .................. ............. ............ ............. ............. ................. 65

4.5 Serial Receive DMA Transfer Process (Rx DMA)....................... ............. ............. ............ ............. .............74

4.6 DMA Interrupts............................................................................................................................................84

4.7 DMA Re

ister Descriptions.........................................................................................................................86

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

62 Chapter 4: Direct Memory Access (DMA) Controller

Introduction

4.1 Introduction

The XA-SCC DMA Controller has been designed to efficiently implement circular

buffering in main memory. There are eight DMA channels; one Rx DMA channel

dedicated to each SCC Receive (Rx) channel, and one Tx DMA channel dedicated to

each SCC Transmit (Tx) channel. The detailed operation of Transmit DMA and Receive

DMA will be covered in sep a rate sections.

4.2 DMA Channe l Architecture

In addition to the 16-bit Global DMA Interrupt Register (which is shared by all eight

DMA channels), each DMA channel has seven control registers and a four-byte Data

FIFO. The four Rx DMA channels h ave one additional register, the Rx Char Time Out

These registers, shown in Figure 4-1, are summarized below.

Table 4-1 DMA Registers

Global DMA Interrupt Re

ister

(not shown in Fi

ure 4-1) All DMA interrupt fla

s are in this re

ister.

DMA Control Re

ister Contains the master mode select and interrupt enable bits for

the channel.

ment Re

ister Holds A23-A16 (the current se

ment) of the 24-bit data buffer

address.

Buffer Base Re

ister Holds A15-A8 of the address of the lowest byte in the circular

buffer.

Buffer Bound Re

ister Points to the first out-of-bounds address above a circular buffer.

Address Pointer Re

ister Points to a sin

le byte or word in the data buffer in memory. The

24-bit DMA address is formed by concatenatin

the contents of

the Se

ment Re

ister [A23-A16] with the contents of the

Address Pointer Re

ister [A15-A 0 ].

Byte Count Re

ister Holds the initial number of bytes to be transferred.

FIFO Control & Status Re

ister Holds the queuin

order and full/empty stat us for the Data FIFO

isters.

Data FIFO Re

isters A four-byte data FIFO buf fer internal to the DMA channel.

Rx Char Time Out Re

ister

(RxCTOR, Rx DMA only) Holds the initial value for an 8-bit character timeout countdown

timer which can

enerate an interrupt.

Chapter 4: Direct Memory Access (DMA) Controller 63

Data Buffer Management in Main Memory

Figure 4-1 DMA Register Set

4.3 Data Buffer Management in Main Memory

Each of the eight DMA channels can be programmed to use a portion of main memory as

a circular bu ffer. Although circular buffers are not mandatory, the relaxation of processor

interrupt service requirements that results from their use makes them preferable in most

applications. Once initialized, the operation of a DMA channel circular buffer req uires no

further allocation/de-allocation of memory by the processor.

A segment in memory is a 64K Byte address space which begins on a 64K Byte

boundary. There are 256 segments in the XA-SCC 16M Byte address space. These

segments are point ed to by the DMA 8-bit Segm ent Register s, which provi de A23-A16 of

the 24-bit memory address.

Data FIFO 3 Data FIFO 2 8

Data FIFO 1 Data FIFO 0

DMA Control

Segment

Buffer Base

To Tx SCC

Channel

From MIF 16

Data FIFO 3 Data FIFO 2 8

Data FIFO 1 Data FIFO 0

DMA Control

Segment

Buffer Base

Buffer Bound

Address Pointer

Byte Count

FIFO Control & Status

RxCTOR RX DMA Channel

From Rx SCC

Channel

To MIF 8 or 16

64 Chapter 4: Direct Memory Access (DMA) Controller

Data Buffer Management in Main Memory

4.3.1 Circular Buffer s

Circular Buffers are enabled by setting the Wrap bit (DMA Control Register bit [2]) to

one.

For each DMA channel, the circular buffer is bounded on the bottom by the contents of

the Buffer Base Register, which points to the lowest byte address in the circular buffer.

The Buffer Bound Register determines the upper bound of the circular buffer. It contains

the highest byte address + 1.

Figure 4-2 Circular Buffer

Circular Buffer Operation

• Data are transferred to or from main memory at the 24 bit address determined by the

concatenation [Segment Register][Address Pointer Register].

• After the transfer, the Address Pointer Register is incremented by one for a byte

transfer (Rx only) or by two for a word transfer (Rx or Tx).

A DMA channel circular buffer can occupy as little as 1 byte in memory, and may

occupy up to 65,536 (64K) contiguous bytes. A circular buffer must reside entirel y

within a single segment of memory; thus it cannot cross a segme nt boundary. All

circular buffers start on 256-byte boundaries, with the low order byte of the base address

forced to 00h by hardware.

Segment Register

1AC000

Circular

Buffer

24-bit even or odd byte address, points to

first out-of-bounds location

Segment Register Buffer Base Register

1A8000

FFFFFF

000000

00h

24-bit even byte address, points to

first data location in buffer

Buffer Bound Register

Chapter 4: Direct Memory Access (DMA) Controller 65

Serial Transmit DMA Transfer Process (Tx DMA)

• If the new value of th e Addres s Pointer Register is equal to the value of the Bu ffer

Bound Register, the highest byte of the circular buffer has just been used. In this case,

the Address Pointer Register is reloaded with the concatenation [Buffer Base

• Memory access proceeds at the address given by the concatenation

[Segment Register][Address Pointer Register].

Example: To maintain a 16,384 byte (16K) circular buffer in data segment 1A hex, ba sed

at 1A 80 00 hex, set the Wrap Bit, and load the Segment, Buffer Base, and Buffer Bound

Registers as shown:

The circular buffer now occupies 16 Kbytes from 1A 80 00 to 1A BF FF (inclusive).

Note that the Buffer Bound Register points to the highest byte address + 1

(i.e., BFFF +1 = C000), and that when the Addres s Pointer Register increments from

BFFFh to C000h it will be reloaded (by hardware) with 8000h.

4.3.2 Linear Buffers

DMA channels can also be configured to access main memory in the typical, linear

manner. In this case, the maintenance of the linear buffer must be overseen by the

processor. Linear Buf fers are enabled by clearing the W rap bit (DMA Control Register bit

[2]) to zero.

4.4 Serial Transmit DMA Trans fer Process (Tx DMA)

This section describes the operation of a typical Transmit DMA channel in synchronous

operation. The various transmit modes and their requ ired data structure s in main memory,

as well as the Tx DMA interrupts , will be described in the following sub-sections.

DMA Control [2] (Wrap Bit) 1

ment Re

ister 1Ah

Buffer Bound Re

ister C000h

Buffer Base Re

ister 80h

If for some reason a DMA channel i s set up to use a portion of main memory as a linear

buffer, care must be taken so that the DMA channel never tries to access memory across

a segment boundary. When the Address Pointer Register rolls over from FFFF h to

0000h the Segment Register does not get automaticall y i ncremented. Therefore, the

next memo ry access for that channel wi ll occur at 0000h of the same segment. The

details of main mem ory d ata structures fo r th e vario us Tx a nd Rx mo de s will be cov ered

in Sections 4.4 and 4.5.

66 Chapter 4: Direct Memory Access (DMA) Controller

Serial Transmit DMA Transfer Process (Tx DMA)

4.4.1 Gener al Principles of Tx DMA

A block of data (1 byte or more) in memory to be transmitted is referred to as a fragment.

All fragments begin at an even address. A fragment can have an even or odd number of

bytes. The byte count can be stored in memory with the fragment (Tx Chaini ng mod e), or

can be written into the Byte Co unt Register (Stop on TC and Peri odic Interrupt modes).

If an SDLC/HDLC Packet is being sent, it can consist of one or more fragments.

Tx DMA channels always fetch two bytes at a time from an even address in main

memory. If an odd byte count is specified, the last byte of the fragment is a pad byte,

which will be discarded by the DMA controller, and not passed along to the SCC.

The processor mu st initialize the control registers in the SCC Tx channel and the

corresponding DMA Tx channel before the channel is turned on. The Tx DMA channel’s

Segment Register and Address Pointer Register must be loaded with the address of the

beginning of the fragment. When a channel stops and is later restarted, the contents of

these registers remains unchanged. When the channel is on, Tx DMA proceeds as

follows:

• The DMA channel fetches 2 b y tes from memory, transfers them to its Data FIFO

registers, and increments its Address Pointer Register by 2 (in Tx Chaining mode, the

first 2 bytes are used for Byte Count).

• When the SCC channel’s Tx shift register becomes empty, it is reloaded with the

current byte in the SCC channel’s Tx Data Buffer (WR8), and the SCC channel signals

the DMA channel that its buffer is empty.

• The DMA channel then transfers the next byte in its FIFO queue, on the internal 8-bit

wide bus, to the SCC channel’s WR8.

• After transfer, the DMA channel’s Byte Counter is decremented.

• When the Byte Counter reaches zero, the action taken by the DMA channel depends

on which of the three distinct DMA transmit modes the channel is operating in:

1. Tx Chaining

–Non-SDLC/HDLC T x Chaining

–SDLC/HDLC Tx Chaining

2. Stop on TC (Terminal Count)

3. Periodic Interrupt

The following table summarizes byte count source, and the interrupt generated for each

of the modes. Details of Tx DMA operation in each of these modes are presented in the

following sub-sections:

Chapter 4: Direct Memory Access (DMA) Controller 67

Serial Transmit DMA Transfer Process (Tx DMA)

Table 4-2 Tx DMA Modes

4.4.2 Tx Chaining

Tx Chaining provides high throughput by allowing multiple fragments (and packets if

using SDLC/HDLC mode) to be sent without direct processor intervention. Tx Chaining

operates slightly differently for non-SDLC/HDLC operation than it does for SDLC/

HDLC operation, so they will be presented separately.

4.4.3 Non-SDLC/HDLC Tx Chaining

The non-SDLC/HDLC Tx Chaining Mode Fragment Format in Memory is shown in

Figure 4-3. Tx Chaining mode for non-SDLC/HDLC operation proceeds as follows:

• The SCC Tx channel is programmed for non-SDLC/HDLC operation; either

Asynchronous mode, or one of the non-SDLC/HDLC synchronous modes.

• The 24-bit (even) address of the first byte of the first packet is written by the processor

into the Tx DMA channel’s Segment Register [A23-A16] and Address P ointer

• The Tx DMA channel is put into Tx Chaining Mode by writing 01b into bits [1:0] of

its DMA Control Register.

• The first two bytes (the b yte count) pointed to in memory by the Address Pointer

the Address Pointer Register is incremented by 2. The actual byte count is a 15-bit

number, represented by bits [14:0] . Bit [15] is called the LastFrag bit.

• Bytes are transferred to the SCC, and the Byte Counter decremented, in the normal

manner.

• When the Byte Counter decrements to zero, the DMA channel continues to pass data

to the SCC, as it is needed , un til the DMA’s Data FIFO is empty. When th e FIFO is

empty, the DMA channel’s Tx Interrupt, if enabled, is sent to the processor.

Mode Byte Count Source Interrupt Generated

Non-SDLC/HDLC Tx Chainin

Header in memory

SDLC/HDLC Tx Chainin

Header in memory End of packet

(not end of fra

ment)

Stop on TC Processor loads Byte Count

ister (for each fra

ment) Byte count completed

(Tx DMA stops)

Periodic Interrupt Processor loads Byte Count

ister (only once) Each time byte count completed

(Tx DMA continues)

68 Chapter 4: Direct Memory Access (DMA) Controller

Serial Transmit DMA Transfer Process (Tx DMA)

• the DMA channel fetches the next two bytes, pointed to by the Address Pointer

on the value of the byte count and the LastFrag Bit, the DMA channel can take one of

the following three courses of action:

1. If the new byte count is greater than zero, it is loaded into the Byte Count Register

and the Byte Counter, and transmission of the new fragment begins.

2. If the new byte count equals zero and LastFrag equals zero, the Tx DMA channel

stops (bits [1:0] of DMA Control Register are cleared by hardware).

3. If the new byte count equals zero and LastFrag equals one, the byte count is

fetched from memory repeatedly. This p rocess continues until either a non-zero

byte count is fetched, or software disables the DMA channel. If a non-zero byte

count is fetched, it is loaded into the Byte Count Regis ter and the Byte C ounter,

and tra nsmission of the new fragment begins.

Figure 4-3 Non-SDLC/HDLC Tx Chaining packet format in memory

For non-SDLC/HDLC Tx Chaining, the Tx DMA channel generates an interrupt at the end of

each fragm ent.

Odd Byte Address Even Byte Address

Data Byte 0

BC Lo = 08h

Data Byte 2

Data Byte 0

BC Lo = 04h

Data Byte 2

Data Byte 0

BC Lo = 03h

etc.

BC Hi = 00h

Data Byte 3

Data Byte 1

BC Hi = 00h

(Pad Byte) XXh

Data Byte 1

BC Hi = 00h

Ascending

Address

...

Byte Count, Fragment 2

Data, Fragment 2

Byte Count, Fragment 1

Byte Count, Fragment 3

Data, Fragment 1

etc.

Chapter 4: Direct Memory Access (DMA) Controller 69

Serial Transmit DMA Transfer Process (Tx DMA)

The possible actions taken by the DMA channel when the Byte Counter reaches zero,

based on the value of the new by te count and the LastFrag Bit, are summarized in

Table 4-3.

Table 4-3 Byte Count and LastFrag Bit Options, non-SDLC/HDLC Tx Chaining

4.4.4 SDLC/HDLC Tx Chaining

The Packet format in memory for SDLC/HDLC Tx Chaining operation is shown in

Figure 4-4. The SDLC/HDLC Tx Chaining sequence is shown graphically in the

flow-chart of Figure 4-5, and proceeds as follows:

• The SCC Tx channel is programmed for SDLC/HDLC operation (see Chapter 5,

“Serial Communications Controller (SCC),” fo r details).

• The 24-bit (even) address of the first byte of the first packet is written by the processor

into the Tx DMA channel’s Segment Register [A23-A16] and Address P ointer

• The Tx DMA channel is put into Tx Chaining Mode by writing 01b into bits [1:0] of

its DMA Control Register.

• The first two bytes (the b yte count) pointed to in memory by the Address Pointer

the Address Pointer Register is incremented by 2. The actual SDLC/HDLC byte count

is a 15-bit number, represented b y bits [14:0]. Bit [15] of the byte co unt is the Last

Fragment indicator (LastFrag). Bit [15] = 0 signifies Last Fragment of the current

Packet. Conversely, bit [15] = 1 signifies Not Last Fragment.

• Bytes are transferred to the SCC, and the Byte Counter decremented, in the normal

manner.

• When the Byte Counter decrements to zero, the DMA channel continues to pass data

to the SCC, as it is needed , un til the DMA’s Data FIFO is empty.

If LastFrag Bit

equals... 0 1

...and new byte

count is

reater

than zero.

When FIFO empty,

enerate Tx

Interrupt and start sendin

Fra

ment usin

new byte count.

When FIFO empty,

enerate Tx

Interrupt and start sendin

Fra

ment usin

new byte count.

...and new byte

count equals zero. When FIFO empty,

enerate Tx

Interrupt and DMA stops. When FIFO empty,

enerate Tx

Interrupt and repeatedly fetch new

byte count until either non-zero byte

count or DMA disabled.

70 Chapter 4: Direct Memory Access (DMA) Controller

Serial Transmit DMA Transfer Process (Tx DMA)

• The DMA channel fetches the next two bytes, pointed to by the Address Pointer

on the value of the LastFrag bit and the byte count, the DMA channel can take one of

the following four courses of action:

1. If LastFrag = 1 and the new byte count is greater than zero, then it is loaded into

the Byte Count R e gister and the Byte Counter, the Address Pointer Register is

incremented by 2, and transmission of the new fragment begins in the normal

manner.

2. If LastFrag = 1 and the new byte count equals zero, then Tx Underrun is

beginning to occur. That is, the SCC channel’s Tx Data Buffer is empty, the DMA

needs another Fragment, but the next Fragment is not yet available in main

memory. There is a time period equal to two serial Byte times (one Byte in the

SCC’s Tx Shift Register, and one in the SCC’s Tx Data Buffer) before Tx

Underrun occurs. The DMA channel repeatedly fetches the next byte count (note

long delay before byte count is fetched again), waiting for it to become non-zero.

If non-zero byte count occurs before Tx Underrun (before the SCC channel Tx

shift register is empty), it is lo aded into the Byte Count Register and the Byte

Counter, and transmission of the new fragment begins in the normal manner.

3. If LastFrag = 1 and Tx Underrun occurs before non-zero byte count, the SCC

channel sends an Abort due to Underrun. The DMA channel’s Tx Er Status bit is

set (Global DMA Interrupt Register bits [15:12]), and a Tx Interrupt is generated,

if enabled (Global DMA Interrupt Register bits [11:8]). The DMA channel stops

(bits [1:0] of DMA Control Register are cleared by hardware).

4. If LastFrag = 0, then the last Fragment of the current Packet has been fed to the

SCC, and the SCC will do a “Normal Ending.”

• When the final bit of the (“Normal Ending”) Closing Flag has been transm itted, the

DMA channel’s Tx Interrupt is asserted, if enabled (Glo bal DMA In terrupt Reg ister

bits [11:8]).

• The DMA channel fetches the next two bytes, pointed to by the Address Pointer

– If the new byte count is greater than zero, it is loaded into the Byte Count Register

and the Byte Counter, the Address Pointer Register is incremented by 2, and

transmission of the new fragment begins in the norm al manner.

– If the new byte count equals zero, then no more packets are waiting in memory, and

the DMA channel stops (bits [1:0] of DMA Control Register are cleared by

hardware).

In SDLC/HDLC Tx Chai ning, the Tx DMA channel generates an interrupt at the end of each

packet, not each fragment.

Chapter 4: Direct Memory Access (DMA) Controller 71

Serial Transmit DMA Transfer Process (Tx DMA)

The possible actions taken by the DMA channel when the Byte Counter reaches zero,

based on the value of the new by te count and the LastFrag Bit, are summarized in

Table 4-4.

Table 4-4 Byte Count and LastFrag options, SDLC/HDLC Tx Chaining

Figure 4-4 SDLC/HDLC Tx Chaining Packet format in memory

If LastFrag

equals... 0 1

...and new byte

count is

reater

than zero.

When FIFO empty,

enerate Tx

Interrupt when Packet has been

completely sent, then start sendin

next Packet usin

new byte count.

When FIFO empty, continue sendin

next Fra

ment as part of current

Packet.

...and new byte

count equals zero. When FIFO empty,

enerate Tx

Interrupt when Packet has been

completely sent, then DMA stops.

When FIFO empty,

enerate Tx

Interrupt and repeatedly fetch new

byte count until either non-zero byte

count or SCC sends Abort.

...

Odd Byte Address Even Byte Address

LastFrag

Ascending

Address

Data Byte 0

Data Byte 2

Data Byte 0

Data Byte 2

Data Byte 0

Data Byte 4

Data Byte 2

Data Byte 0

not LastFrag

Byte Count, Frag 3

Data, Frag 3

Byte Count, Frag 2

Byte Count, Frag 1

Byte Count, Frag 1 of Next Packet

etc.

Data, Frag 2

Packet

Data, Frag 1

etc.

(Pad Byte) XXh

Data Byte 1

Data Byte 3

Data Byte 1

(Pad Byte) XXh

Data Byte 3

Data Byte 1

72 Chapter 4: Direct Memory Access (DMA) Controller

Serial Transmit DMA Transfer Process (Tx DMA)

Figure 4-5 SDLC/HDLC Tx Chaining Flow-Chart

Start

Fetch BC (Byte Count) from Memory

Fetch Data Bytes from Memory

Go to next if Byte Counter = 0

Go to next if FIFO is Empty Wait

approx.

1 Byte

Time

Old "Frag Bit" = 0

New BC > 0

Yes

Pass Data from FIFO to SCC

as needed, decrement Byte Counter.

If Byte Counter > 0 keep FIFO Full.

Pass Data to SCC as needed until

FIFO empty.

Fetch New Byte Count from Memory

SCC

finished sending

Flag?

New BC = 0

Interrupt Processor

Is there

another packet to

send?

Stop DMA

Interrupt Processor

Set Error Bit

Old LastFrag = 1 &

SCC sent Abort

because of data

underrun.

Old LastFrag = 1 &

New BC = 0 &

SCC not abort yet

(fetch BC again in

case software has

changed it)

Old LastFrag = 1 &

New BC > 0

Chapter 4: Direct Memory Access (DMA) Controller 73

Serial Transmit DMA Transfer Process (Tx DMA)

4.4.5 Stop on TC (Ter minal Count)

In Stop on TC mode one fragment is transmitted, an interrupt is gen erated if enabled, and

the Tx DMA channel stops. The Tx DMA channel is put into Stop on TC mode by

writing 11b into bits [1:0 ] of its DMA Control Register, after the SCC chann el and the

DMA channel’s Segment Register, Address Pointer Register, and Byte Count Register

have been initialized b y the processor.

When the Byte Counter decrements to zero, the DMA channel stops (bits [1:0] of DMA

Control Register are cleared by hardware) and the channel’s Tx Interrupt is asserted, if

enabled (Global DMA Interrupt Register bits [11:8]).

4.4.6 Periodic Interrupt

Periodic Interrupt mode provides a periodic interrupt to the processor while streaming

data. The period is defined as the number of byte transfers specified in the Byte Count

The Tx DMA channel is put into Periodic Interrupt mode by writing 10b into bits [1:0] of

its DMA Control Register, after the SCC channel and the DMA channel’s Segment

In Periodic Interrupt mode, whenever the Byte Counter reaches zero, the DMA channel

will assert a Tx Interrupt (Global DMA Interrupt Register bits [11:8]), but will not stop.

The Byte Counter automatically reloads itself from the Byte Count Register, and

transmission continues.

74 Chapter 4: Direct Memory Access (DMA) Controller

Serial Receive DMA Transfer Process (Rx DMA)

4.5 Serial Receive DMA Transfer Process (Rx D MA)

This section describes the operation of a typical Receive DMA channel. The various

receive modes, their associated data structures in main memory, and their interrupts , will

be described in the following sub-sections.

4.5.1 Gener al Principles of Rx DMA

An Rx DMA channel and its associated Rx SCC channel require initialization by the host

processor. The full 24-bit starting address for the data b uffer in main memory must be

written to the Rx DMA channel’s Segment Register [A23-A16] and Address Poin ter

registers remains unchanged. Once the receive channel has been started, the following

sequence moves data from the SCC channel’s RxD input to main memory:

• When the SCC channel’s Rx shift register has assembled a byte, the byte is transferred

to the Receive Data Buffer (RR8), and a signal is sent to the Rx DMA channel.

• The Rx DMA transfers the byte from the SCC channel’s RR8 to its Data FIFO

Registers along the internal 8-bit wide bus.

• When the DMA channel has assembled the specified number of bytes (one or two,

specified in DMA Control Register bi t [4]) in its Data FIFO Registers, it asserts bus

request to the Memory Interface (MIF).

• When bus grant is returned to this DMA channel, the DMA output address is mapped

into row and column addresses (if DRAM) by the memory controller, the data are

written to memory, and the bus is released.

• The Address Pointer Register increments by 1 or 2 after the transfer, and the Byte

Counter decrements by 1 or 2, depending upon the number of bytes transferred.

The following modes for Rx DMA will be treated in separate sub-s ections:

1. Rx SDLC/HDLC

2. Periodic Interrupt

3. Asynchronous Character Time Out

4. Asynchronous Character Match

Chapter 4: Direct Memory Access (DMA) Controller 75

Serial Receive DMA Transfer Process (Rx DMA)

4.5.2 Rx SDLC/HDLC

In Rx SDLC/HDLC mode, the Rx DMA channel stores the SDLC/HDLC packet in

memory as follows:

• The first two bytes will h old the 15-bit Packet Byte Count. The most significant bit

holds “Abort” status: 1 = packet was aborted, 0 = packet was NOT aborted (Normal

Ending). Upon reception of a Closing Flag, the Rx SCC channel passes the final byte

count (number of data bytes plus 2 bytes of CRC if applicable) to the Rx DMA, at

which time they are written here. A 32 Kbyte packet is represented by Packet By te

Count = 0.

• The data bytes begin on the next even address above the byte count, and are followed

by two bytes of CRC and a Packet Status Byte.

• If the Packet Status Byte falls on an even address, then the next (odd address) byte will

be a pad byte (the contents are meaningless).

To start the Rx DMA channel in SDLC/HDLC mode, the processor should do the

following:

1. Set up the associated Rx SCC channel to receive in SDLC/HDLC mode (see SCC

chapter for details). Do not yet enable the Rx SCC channel.

2. Initialize the Rx DMA channel’s Segment Register, Buffer Base Register, and Buffer

Bound Register, if necessary, to set up a circular buffer.

3. Write a 16-bit even address into the Rx DMA channel’s Address Pointer Register.

This points to the location where the Rx DMA channel will store the first packet’s

byte count, after the packet has been transferred to memory.

4. Start the Rx DMA channe l in SDLC/HDLC mode by setting the channel’s DMA

Control Register bits [1:0] = 01b.

5. Set WR3 bit [0] = 1 in the Rx SCC channel (Rx Enable). This starts the SCC

receiver.

When the packet has been completely stored in memory, the Rx DMA channel’s Rx

Interrupt gets asserted, if enabled (Global DMA Interrupt Register bits [3:0]).

76 Chapter 4: Direct Memory Access (DMA) Controller

Serial Receive DMA Transfer Process (Rx DMA)

Figure 4-6 Rx SDLC/HDLC packet format in main memory.

4.5.3 Packet Status Byte

The information contained in the Packet Status Byte is generated by the Rx SCC channel

and passed to the Rx DMA channel for storage in memory. Note that the order of the bits

and their functions are not the same as in RR1 of the SCC channel.

Packet Status Byte[7:6] - Reserved

Packet Status Byte[5] - Rx Overrun Error

A one in this bit indicates that the SCC channel’s Rx Data Buffer has overflowed, and at

least one byte in the packet was written over while waiting to be fetched by the DMA.

76543210

Reserved Reserved Rx Over-

run Error CRC/Fram-

ing Error Reserved Residue

Code 0 Residue

Code 1 Residue

Code 2

Rx SDLC/HDLC Buffer Image in Memory

(Even Byte Count = 4) Rx SDLC/HDLC Buffer Image in Memory

(Odd Byte Count = 5)

Ascending

Address

The M.S. Bit in the "BC Hi" byte is the "Abort Status bit"; 1 = packet was aborted, 0 = packet was

not aborted.

Even Byte Count uses a Pad byte to word align the next packet.

Byte Count[14:0] = All zeroes = 32K Bytes (after interrupt is generated)

BC is Byte Count, and its value only counts the data bytes (including CRC bytes) not PAD bytes, nor Status

bytes, nor Byte Count bytes.

Odd Byte Address Even Byte Address

Pkt 1, Data Byte 0

Pkt 1, BC Lo

Pkt 0, Status Data Byte

CRC (or data byte 2 if no CRC)

Pkt 0, Data Byte 0

Pkt 0, BC Lo = 04h

etc.

Pkt 1, BC Hi

(Pad Byte) XXh

CRC (or last data byte if no CRC)

Pkt 0, Data Byte 1

Pkt 0, BC Hi = (0)0000000

...

Odd Byte Address Even Byte Address

Pkt 1, Data Byte 0

Pkt 1, BC Lo

CRC (or last data byte if no CRC)

Pkt 0, Data Byte 2

Pkt 0, Data Byte 0

Pkt 0, BC Lo = 05h

etc.

Pkt 1, BC Hi

Pkt 0, Status Data Byte

CRC (or data byte 3 if no CRC)

Pkt 0, Data Byte 1

Pkt 0, BC Hi = (0)0000000

...

Note 0

Note 1

Note 2

Note 3

Chapter 4: Direct Memory Access (DMA) Controller 77

Serial Receive DMA Transfer Process (Rx DMA)

Packet Status Byte[4] - CRC/Framing Error

In the Rx SDLC/HDLC Packet Status Byte, a one in this bit indicates a CRC Error was

detected when comparing the CRC check value to the received CRC. Note that in the

SCC channel’s RR1, this b it has a distinctly different meaning in the case of

Asynchronous communication.

Packet Status Byte[3] - Reserved

Packet Status Byte[2:0] - Residue Code bits

See “Rx SDLC/HDLC Partial Byte” below.

4.5.4 Rx SDLC/HDLC Partial Byte

If the Rx SCC channel is operating in 8 bits/character mode (as specified by

WR3 [7:6] = 11b), then the last byte received can be a partial byte. The number of valid

bits in the last byte is encoded by the three Residue Code Bits in the Packet Status Byte

[2:0]. The last byte received is stored in memory according to the bit positions shown in

Table 4-5.

If no CRC is received, then the partial byte is stored in memory as the last byte of the

packet in the manner of Figure 4-7 top diagram.

If a CRC is received, then the valid bits of the partial byte (in normal order) are

concatenated with the low order bits of the CRC, and the high order bits of the CRC are

stored in memory as the last byte of the packet as if it were the partial byte. In other

words the 16-bit CRC is passed to the Rx DMA channel, and the Rx DMA stores it in

memory the same as if it were data (see Figure 4-7 bottom diagram).

78 Chapter 4: Direct Memory Access (DMA) Controller

Serial Receive DMA Transfer Process (Rx DMA)

Figure 4-7 SDLC/HDLC Residue Bits - Rx DMA Memory Images for

“Partial Byte”

Table 4-5 SDLC/HDLC Residue Bits and Data Bit Positions of Last Byte of packet

Number of valid

Bits Received in

the Last Byte

Packet Status

Byte bits [2:0]

(Residue Bits) Data Bit Position s in Last Byte of Received Packet

R0 R1 R2 B7 B6 B5 B4 B3 B2 B1 B0

8 0 1 1D7D6D5D4D3D2D1D0

7 1 0 1D6D5D4D3D2D1D0 X

6 0 0 1D5D4D3D2D1D0 X X

5 1 1 0D4D3D2D1D0 X X X

4 0 1 0D3D2D1D0 X X X X

3 1 0 0D2D1D0 X X X X X

2 0 0 0D1D0 X X X X X X

1 1 1 1D0 X X X X X X X

Notes: 1 . Residue bits are NOT defined the same as in the 85C30.

2. This table is true for 8 Rx bits/character ONLY (WR3[7:6]=11).

3. In 8 bits/char mode, only the last byte can contain less than 8 bits.

4. If a CRC was transmitted, then these are the last bits of the CRC; in other

words the CRC is passed to the DMA, and the DMA stores it in memory the

same as if it were data (see “Residue Bits” Memory Ima

e fi

ure below).

Ascending

Address

Odd Byte Address

11-Bit Data Packet with no CRC,

8 Bits/Character

Even Byte Address

Data Byte 0

BC Lo for next packet

XXX 00 100

D7,6,5,4,3,2,1,D0

BC Lo = 02h

...

Odd Byte Address

11-Bit Data Packet with CRC,

8 Bits/Character

Even Byte Address

Data Byte 0

BC Lo for next packet

XXX 00 100

CRC[12:5]

D7,6,5,4,3,2,1,D0

BC Lo = 04h

etc.

BC Hi for next packet

(Pad Byte) XXh

D10,D9,D8,XXXXX

BC Hi = 00h

etc.

BC Hi for next packet

(Pad Byte) XXh

CRC[15:13],XXXXX

CRC[4:0],D10,D9,D8

BC Hi = 00h

...

Chapter 4: Direct Memory Access (DMA) Controller 79

Serial Receive DMA Transfer Process (Rx DMA)

4.5.5 Periodic Interrupt

Rx DMA Periodic Interrupt mode allows an interrupt to be generated upon the reception

of every N bytes, where N is the 16-bit constant stored in the Rx DMA channel’s Byte

Count Register.

To operate in Rx DMA Periodic Interrupt mode proceed as follows:

1. Initialize the Rx SCC channel (see SCC chapter for details).

2. Initialize the Rx DMA channel’s Segment Register, Buffer Base Register, and Buffer

Bound Register to set up a circular buffer, and initialize the Address Pointer Register.

3. Load a 16-bit value into the Rx DMA channel’s Byte Count Register.

4. Enable the Rx DMA chan nel’s Rx Interrupt (DMA Contro l Reg ister bits [6:5] see 4.6

for details).

5. Start the Rx DMA channe l in Periodic Interrupt mode by setting th e channel’s DMA

Control Register bits [1:0] = 10b.

6. Enable the Rx SCC channel.

Each time the Rx DMA Channel’s Byte Counter decrements to zero, the Rx Interrupt is

asserted (Global DMA Interrupt Register bits [3:0]) and the Byte Counter is

automatically reloaded from the Byte Count Register, resulting in an interrupt every N

bytes.

4.5.6 Asynch ronous Character T ime Out

Each of the four Rx DMA channels has an 8-bit Rx Character Time Out Register

(RxCTOR) and an associated countdown timer. The purpose of this timer is to generate

an interrupt if a pre-selected interval elapses between the reception of successive

characters during Asynchronou s communication.

If the RxCTOR is loaded with zero, the coun ter never starts, and does not generate an

interrupt. If the RxCTOR is loaded with any non-zero value (1-255), the down-counter

starts upon reception of the first character, but gets reloaded with the value in the

RxCTOR every time a new character is received. If the down-counter reaches zero, that

channel’s Rx Char Time Out Interrupt gets asserted (Global DMA Interrupt Register bits

[7:4]).

The timer counts once every “crude character time” (Bit Clock divided by 8). The “SCC

Bit Clock” is brought out of the associated Rx SCC channel in order to clock the timer.

This bit clock is divided by 8 (1/8 prescaler in hardware) before being passed to the

down -counte r (see Figu re 4-8).

80 Chapter 4: Direct Memory Access (DMA) Controller

Serial Receive DMA Transfer Process (Rx DMA)

For example: To get an interrupt when 200 crude character times elapse between

received characters, load the RxC TOR with 200d, where:

{200 crude char. times}∗{8 SCC Bit Clocks/crude char. time} = 1600 SCC Bit Clocks.

Figure 4-8 Rx Character Time Out Timer

4.5.7 Asynch ronous Character Match

If (and only if) the Rx SCC chann e l is in Asynchronous mode, then four of its Write

Registers (WR6, WR7, WR16, and WR17) can be used to monitor the incoming data

stream for control, or match, characters. If MCIPEnable in the Rx SCC channel has been

turned on (WR1[5] = 1), then after a match character has been written to externa l

memory by the Rx DMA channel, it generates a Match Character Interrupt (MCIP =

Global DMA Interrupt Regis ter bits [15 :12]) .

Since there are four match registers, up to four control characters can be watched for

simultaneously. However, whenever MCIPEnable is on, all four match registers are

always active. Therefore, in order to watch for fewer than four control characters, the

extra match register( s) must c ontain a co py o f on e of the control ch aracters. To search for

no control characters, simply turn off MCIPEnable (WR1[5] = 0) in the Rx SCC channel.

Also in the SCC channel is a 2-bit field in RR10[3 :2] that indicates which of the four

match registers was matched last. This “Last Matched Code” is used by the processor to

determine which match register holds the character to be searched for in memory. The

Last Matched Codes are given in Table 4-6.

BRGClk

BRGTC

WR13[1:0]WR12[7:0]

/ 10 Reload every Rx Char

Rx Char

Time Out

Interrupt

/ 8

WR11[6:5] WR4[7:6]

RxClk SC_BitClk ByteClk

BRGOut

SCCi DMAi

BRG

Divdr

RxCTOR

00 = /1

01 = /4

10 = /8

11 = /16

/8 Programmable

Char Time Out

Down Counter

Chapter 4: Direct Memory Access (DMA) Controller 81

Serial Receive DMA Transfer Process (Rx DMA)

Table 4-6 Last Matched Codes

Remember, sometimes more than one match register will contain the same value in order

to “de-activate” an unused match register(s). In that case, several match registers will

match the received control character simultaneously. If more than one match register

matches, the value in RR10[3:2] will be the lowest binary value fro m among the

matching regi sters.

It is important to note that the DMA’s MCIP Interrupt bit will be set immediately after the

first matching control character has been written to external memory, but the Last

Matched Code can continue to change as additional matching control characters are

received by the SCC. Therefore, the last control character stored in memory by the DMA

can differ from that indicated by the Last Matched Code. This can only occur if software

has paused the DMA (while servicing the MCIP Interrupt), but additional, different

control characters have already been received by the SCC and possibly transferred to the

DMA’s Data FIFO. A prog ramming strategy for handling this predicament is included in

the “Typical Response to an MCIP Interrupt” example below.

The Rx DMA channel’s FIFO Control & Status Register bit [5] is the “Two or More

Control Characters” (TCC) bit. If MCIPEnable in the Rx SCC channel is on and 2 or

more match characters were written to external memory before the interrupt was

serviced, then the TCC bit will go to 1. The interrupt service routin e is responsible for

clearing the TCC bit. CAUTION! The TCC bit must be read by the interrupt service

routine before the MCIP Interrupt bit is cleared, because clearing the MCIP Interrupt bit

also clears the TCC bit.

RR10[3:2] Last Matched

00 WR6

01 WR7

10 WR16

11 WR17

82 Chapter 4: Direct Memory Access (DMA) Controller

Serial Receive DMA Transfer Process (Rx DMA)

Figure 4-9 Relevant MMRs for Asynchronous Character Match

SCC 7023

WR6 RR10

Match Char

WR7

WR16

WR17

WR1

MCIPEnable = 1 Enables the match feature for this SCC. WARNING: Only enable in Async mode.

WR6 matched last

WR7 matched last

WR16 matched last

WR17 matched last

DMA

131415 12 0 Global DMA Interrupt Register

MCIP_0

MCIP_1

MCIP_2

MCIP_3

Match Character Interrupt Pending bit for SCC0

Match Character Interrupt Pending bit for SCC1

Match Character Interrupt Pending bit for SCC2

Match Character Interrupt Pending bit for SCC3

Rx DMA FIF0 Control & Status Register

TCC = 1

TCC = 0Two or more control characters stored in memory since this bit was cleared.

ne or zero control

characters stored in memory since this bit was cleared.

Chapter 4: Direct Memory Access (DMA) Controller 83

Serial Receive DMA Transfer Process (Rx DMA)

4.5.8 Typical Response to an MCIP Interrupt

The following sequence illustrates a typical response to an MCIP Interrupt, in which the

matched character is to be removed from the buffer in external memory:

1. Read the Global DMA Interrupt Register and determine that this is an MCIP

Interrupt.

2. Pause (Stop) the relevant Rx DMA channel by writing 00b to its DMA Control

3. Read the TCC bit, FIFO Control & Status[5]. This indicates whether to search for

one, or more th an one, contro l character( s) in external mem ory. It does NOT indicate

whether one or more additional control characters are in the DMA’s Data FIFO, and/

or in the SCC’s Rx Data Buffer (RR8).

4. Read the Rx DMA’s Address Pointer Register to find out approximately where in

memory to search for the control character(s). The scope of the search will depend

on how long it took to res pond to the interrupt, but will normally be very small.

5. Read the Last Matched Code in the SCC’s RR10[3:2] to determine which character

is being searched fo r. For unusu ally long interrupt service respon se times, the Last

Matched Code may have changed after DMA was paused, due to the reception of an

additional, different control character.1

6. Find the control character in memory and remove it, if desired. It may then be

necessary to shift any subsequent bytes that were stored by the DMA. Since the

DMA is now paused, no new bytes will be stored while servicin g the buffer.

7. Adjust the Rx DMA’s Address Point er Register, if necessary, to compensate for the

deleted control character.

8. Clear the MCIP Interrupt bit and the TCC bit by writing ‘1’ (not ‘0’) to the MCIP

Interrupt bit’s position in the DMA Global Interrupt Register (while writing zeroes to

the other 15 bits, 0 = NOP).

9. Restart the Rx DMA channel by writing 10b to its DMA Con trol Register bits [1:0].

10. Return from interrupt.

11. If there were additional control characters in the DMA’s Data FIFO and/or the SCC’s

RR8, the DMA will now store them in external memory and a new MCIP Interrupt

will be generated.

1 In this case, compare the most recent character in memory to the character indicated by the

Last Matched Code. If they are different, compare the most recent character to the contents of

the other match registers. If again they are different, compare the next oldest character in

memory, and so on. The upper bound on the search regi on is based on the incoming data rate

and the interrupt response latency (i.e., how many characters could have been received before

the DMA channel was paused).

84 Chapter 4: Direct Memory Access (DMA) Controller

DMA Interrupts

4.6 DMA Int errupts

All DMA interrupts (Global DMA Interrupt Register [15:0]) appear to the XA as the two

maskable Event interrupts “DMAL” and “DMAH,” which are enabled by setting either

the EDMAL (hex 426[5]) or the EDMAH (hex 426[6]) bits in the IEH SFR (See

Figure 4-10).

• Match Character Interrupt Pending (MCIP) interrupts (if in Asynchronous mode), can

only appear on the DMAH interrupt.

• Rx Char Time Out Interrupts can only appear on the DMAL interrupt.

• Standard Tx and Rx Interrupts can be routed to either the DMAH or DMAL interrupt.

Routing is accomplished by writing the appropriate code to bits [6:5] of the channel’s

DMA Control Register as follows:

DMA Control[6:5] = 00 - Disabled

DMA Control[6:5] = 01 - Reserved

DMA Control[6:5] = 10 - Enabled and steered to “DMAL”

DMA Control[6:5] = 11 - Enabled and steered to “DMAH”

Example: Steer Tx DMA channel 0’s Tx Interrupt to DMAH interrupt: Write 11b to Tx

DMA channel 0’s DMA Control Register bits [6:5].

Example: Steer Rx DMA chann el 3’s Rx Interrupt to DMAL interrupt: Write 10b to Rx

DMA channel 3’s DMA C ontrol Register bits [6:5].

Note that bit pattern 0 1b is reserved. Always use bit pattern 00b to disable the Tx or Rx

Interrupts.

As is the case with all oth er XA Event Interrupts, the prio rity levels for DMAL and

DMAH must be initialized up on reset. The Interru pt Priority Register fields for DMAL

and DMAH are PDMAL and PDMAH, respectively. The priorities assigned to DMAH

and DMAL are up to the programmer, but by convention DMAH should be assigned a

higher priority than DMAL. Also, the EA (Enable All) bit in the IEL SFR must be set

before any Event Interrupts will be serviced.

The relevant addresses in SFR space for initializing DMA interrupts in the XA are given

in Table 4- 7.

Chapter 4: Direct Memory Access (DMA) Controller 85

DMA Interrupts

Figure 4-10 DMA Interrupt Structure

DMA

Controller

MCIP Interrupts go to DMAH

MCIP

Interrupts

Character

Time Out

Interrupts

All Tx and Rx Interrupts can be routed to either the DMAL or DMAH Interrupt using their respective DMA Control

Note:

Rx Interrupts

XA Interrupt

Controller

DMAH Interrupt

DMAL Interrupt

Tx Interrupts

Tx0 DMA Control[6] Tx0 to DMAL

Tx0 to DMAH

Tx1 to DMAL

Tx2 to DMAL

Tx3 to DMAL

Rx0 to DMAL

Rx1 to DMAL

Rx2 to DMAL

Rx3 to DMAL

Rx3 to DMAH

Rx2 to DMAH

Rx1 to DMAH

Rx0 to DMAH

Tx3 to DMAH

Tx2 to DMAH

Tx1 to DMAH

Tx0 DMA Control[5]

Char Time Out Interrupts go to DMAL

86 Chapter 4: Direct Memory Access (DMA) Controller

DMA Register Descriptions

Table 4-7 DMA Interrupt Bits

4.7 DMA Registe r Descriptions

After system reset, the DMA controller is in the Stop mode (DMA Control Register bits

[1:0] = 00). All registers are reset to logic 0 and the DMA controller is in the IDLE state.

All DMA interrupts are cleared.

In this section, the function of each DMA Register will be explained. Where appropriate,

individual bit functionality will be presented.

Bit/Field Name

SFR Bit(s)

Byte Address (hex)

Bit Address (hex) Description

EDMAL IEL.5

426[5]

335

Enable bit for DMAL interrupt

EDMAH IEL.6

426[6]

336

Enable bit for DMAH interrupt

EA IEL.7

426[7]

337

Master Enable bit

PDMAL IPA2[6:4]

4A2[6:4]

Priority Re

ister field for DMAL interrupt

PDMAH IPA3[2:0]

4A3[2:0]

Priority Re

ister field for DMAH interrupt

Chapter 4: Direct Memory Access (DMA) Controller 87

DMA Register Descriptions

4.7.1 Global DMA Interrupt Register

The 16 bit Global DMA Interrupt Register serves all 8 DMA channels. When a DMA

channel needs to request an interrupt, the appropriate bit in the Global DMA Interrupt

by the processor. Writing a logical one (not a zero) to a bit position clears that bit. In

the event that a bit (or bits) is being cleared by software on the same PClk cycle that it is

being set by hardware, the bit will be set.

Global DMA Interrupt Register [15:12] - Tx Er (SDLC/HDLC) or MCIP

(Asynchronous) Interrupts

These bits have distinctly differ ent meanin gs depending on whet her the channel is doing

Asynchronous or SDLC/HDLC communication:

Global DMA Interrupt Register [11:8] - Tx Interrupts

For non-SDLC/HDLC operation, Tx Interrupt bits are set whenever the Tx DMA

channel’s Byte Counter reaches zero, and the interrupt is enabled. For SDLC/HDLC

operation, a Tx Interrupt is asserted when the Tx SCC channel has sent either the Closing

Flag or an Abort.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMA

3DMA

2DMA

1DMA

0DMA

3DMA

2DMA

1DMA

0DMA

3DMA

2DMA

1DMA

0DMA

3DMA

2DMA

1DMA

Tx Er or MCIP Interrupts Tx Interrupts Rx Char Time Out

Interrupts Rx Interrupts

SDLC/HDLC Tx Er Status bits are set to 1 when an “underrun abort” occurs in SDLC/HDLC

Tx Chainin

mode. That is, data underrun caused the Tx SCC channel to

issue an abort on the serial Tx line. When in SDLC/HDLC mode, these bits

not

enerate an interrupt, they are merely status bits.

Asynchronous Match Character Interrupt Pendin

(MCIP) bits are set when the Rx SCC

channel has detected the first match character in the incomin

data stream. If

CCIPEnable in the Rx SCC channel has been turned on (WR1[5] = 1), then

when a match character has been written to memory by the Rx DMA channel,

that channel’s MCIP bit is set to 1.

88 Chapter 4: Direct Memory Access (DMA) Controller

DMA Register Descriptions

Global DMA I nterru pt Re gis ter [7: 4] - (A syn chron ous ) Rx Ch ar Time Ou t

Interrupts

These bits are set whenever the Rx DMA ch annel’s Rx Character Time Out down-counter

reaches zero during asynch ronous com mun ication. If the Rx Character Time Out Register

(RxCTOR) is loaded with zero, the counter never starts, and does not generate an

interrupt. If the RxCTOR is loaded with any non-zero value, the down-counter starts

upon reception of the first character, but gets reloaded with the value in the RxCTOR

every time a new character is received. If the down-counter reaches zero, that channel’s

Rx Char Time Out Interrupt gets asserted. The down-counter decrements once every 8

bit-times, and measures “dead air” time between characters.

Global DMA I nterru pt Re gis ter [3: 0] - R x Inter rup ts

In Rx SDLC/HDLC mode, when an SDLC/HDLC packet has been completely stored in

memory by the Rx DMA channel, that channel’s Rx Interrupt gets asserted. In Periodic

Interrupt mode, an Rx Interrupt is generated upon the reception of every N bytes, where

N is the 16-bit constant stored in the Rx DMA channel’s Byte Count Register.

4.7.2 DMA Control Register

This register contains the mode select and control bits for the DMA channel.

DMA Control Register [7] - Reserved (Write zero)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Wrap

AdrFrz

Interrupt disa bled

Reserved

Interrupt enabled, steer to DMAL

Interrupt enabled, steer to DMAH

Rx 2By te or Tx Async/Sync m ode

Reserved, write 0

Stop

Tx Chaining or Rx SDLC/HDLC mode

Periodic Interrupt mode (T x and Rx)

Stop on TC (Tx)

Chapter 4: Direct Memory Access (DMA) Controller 89

DMA Register Descriptions

DMA Control Register [6:5] - Interrupt Enable

These bits refer to the Tx and Rx Interrupts only (Global DMA Interrupt Register bits

[11:8] and [3:0]).

DMA Control Register [4] - (Rx) 2Byte mode or (Tx) Async/Sync mode

This bit has distinctly different functions for Rx and Tx DMA channels.

DMA Control Register [3] - AdrFrz

This bit disables the automatic incrementation of the Address Pointer Register. To

repetitively write o r read an I/O port, its ad dress should be written to the Address Pointer

allows normal auto-increment.

DMA Control Register [2] - Wrap

This is the circular buffer on/off bit for the DMA channel. If set, the circular buffer

function is enabled (i.e., when the Address Pointer Register matche s the Buffer Bound

00h). If clear, the circular buffer function is disabled (i.e., Address Pointer Register will

increment indefinitely, eventually rolling over from FFFFh to 0000h).

00 Interrupt Disabled

01 Reserved

10 Interrupt Enabled, steer to DMAL

11 Interrupt Enabled, steer to DMAH

Rx DMA channels If set, memory writes will only occur after every second byte has arrived in the

Data FIFO Re

isters, and one word (2 bytes) will be transferred with each

write. If clear, memory writes will occur upon the reception of each byte, and

one byte will be transferred with each write. 2Byte mode can reduce an Rx

DMA channel’s memory access bandwidth requirement by up to 50%, but will

leave the last byte of an odd byte count Asynchronous mo de transfer in the

Data FIFO. From there, it must be retrieved by the processor. However, in Rx

SDLC/HDLC mode, the Data F IF O is flushed to memory at the end of a

packet.

Tx DMA channels For Tx Interrupts to function properly, this bit must reflect the SDLC/HDLC

status of the associated Tx SCC channel. If the SCC channel is in SDLC/

HDLC mode, clear this bit to 0. If the SCC channel is not in SDLC/HDLC

mode, set this bit to 1.

90 Chapter 4: Direct Memory Access (DMA) Controller

DMA Register Descriptions

DMA Control Register [1:0] - DMA Enable and Mode Select

These bits start and stop the channel, and select the operating mode. In Tx Chaining and

Stop on TC modes, the DMA hardware clears these two bits when it has reached a

stopping point. If the processor is writing a one to either (or both) of these bits on the

same PClk cycle that the hardware is clearing them, the result will be a one.

4.7.3 Segment Register

The DMA channel Segment Register contains the upper eight address bits in a 24-bit

memory address. This regist er is never incremented by hardware, and is only written to

by the processor. In most applications, it will simply be written once to point to the

segment where the circular buffer is maintained.

4.7.4 Buffer Base Register

The DMA channel Buffer Base Register contains the middle 8 address bits of a 24-bit

memory address. The concatenation [Segment Register][Buffer Base Register][00h]

forms the address of the bottom of a circular buffer.

4.7.5 Buffer Bound Register

The DMA channel Buffer Bound Register contains the low 16 address bits of a 24-bit

memory address. It points to one byte above the highest byte address in a circular buffer

(top + 1).

00 Stop

01 Tx Chainin

mode or Rx SDLC/HDLC mode

10 Periodic Interrupt mode (T x and Rx channels)

11 S top on TC mode (Tx channel)

76543210

A23 A22 A21 A20 A19 A18 A17 A16

76543210

A15 A14 A13 A12 A11 A10 A9 A8

1514131211109876543210

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Chapter 4: Direct Memory Access (DMA) Controller 91

DMA Register Descriptions

4.7.6 Address Pointer Register

The DMA channel Address Pointer Register contains the low 16 address bits of a 24-bit

memory address. All DMA memory or I/O access for the channel occurs at the address

formed by the concatenation [Segment Register][Address Pointer Register].

4.7.7 Byte Count Register

The DMA channel Byte Count Register is a 16-bit register which is used to pre-load and

re-load the Byte Counter (a 16-bit do wn-counter) in Periodic Interrupt mode (Tx and Rx

channels), and Stop on TC mode (Tx channels).

4.7.8 FIFO Control & Status Register

The DMA channel FIFO Control & Status Register is an 8-bit register which contains the

queuing information for the data bytes in the Data FIFO Registers (B it 5, however, is

unrelated to the Data FIFO Registers, and is associated with Rx Match Characters).

1514131211109876543210

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1514131211109876543210

16-bit Byte Count

The FIFO Con tro l and St atus Re gi ster sho uld n ev er be wri tte n wh ile th e DMA chan ne l i s runni ng ,

as the results of such a write are undefined.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Byte 0 is valid

Byte 1 is va lid

Byte 2 is valid

Byte 3 is valid

Byte Order Status

TCC

Reserved

92 Chapter 4: Direct Memory Access (DMA) Controller

DMA Register Descriptions

FIFO Control & Status Register [7:6] - Reserved

FIFO Control & Status Register [5] - Tw o or Mor e Cont ro l Char act ers

This bit is used only when an Rx DMA and Rx SCC channel are operating in

Asynchronous Character Match mode. If MCIPEnable in the Rx SCC channel has been

turned on (WR1[5] = 1), then when a match character has been written to memory by the

Rx DMA channel, it gen erates an MCIP Interrupt (Global DMA Interrupt Register bits

[15:12]). If a second match character is written to memory before the MCIP Interrupt bit

is cleared, then the TCC bit gets set to 1. The MCIP Interrupt bit and the TCC bit are

cleared by writing a 1 (not a zero!) to the MCIP Interrupt bit’s posit ion in the DMA

Global Interrupt Register (usually while writing zeroes to the other 15 bits, 0 = NOP).

FIFO Control & Status Register [4] - Byte O rder Stat us

The Byte Order Status bit is only valid wh en bits [3:0] = 1111b (i.e., when the Data FIFO

is full). Using this bit, the processo r can determine whether bytes 0 and 1 are older than

bytes 2 and 3, or vice versa. When this bit is set, bytes 2 and 3 are older than bytes 0 and

1. When this bit is clear, bytes 0 and 1 are older than bytes 2 and 3. When there are on e or

more empty bytes, the temporal order can always be determined. The FIFO always fills

and empties in ascending order: 0 1 2 3 0 1 2 3 ... etc.

FIFO Control & Status Register [3:0] - FIFO Byte St atus

FIFO Control & Status Register bits [3:0] (FIFO BS) indicate whether the corresponding

byte in the Data FIFO Register set contains valid or invalid data. For example, a 1 in bit

[3] means that there is valid data in byte 3, while a 0 in bit [2] means that b yte 2 is

“empty ” (contains in valid data).

4.7.9 Data FIFO Registers

These four registers constitute the 4-byte data FIFO buffer internal to the DMA channel.

The FIFO always fills and empties in ascending order: 0 1 2 3 0 1 2 3 ... etc. (See FIFO

Control and Status Register)

7654321076543210

Data FIFO R egister 3 Data FIFO R egister 2

Data FIFO R egister 1 Data FIFO R egister 0

Chapter 4: Direct Memory Access (DMA) Controller 93

DMA Register Descriptions

4.7.10 Rx Character Time Out Regist er (RxCTOR)

The RxCTOR holds the starting value for the Receive Character Time Out Timer

(down-counter) for use in Asynchronous communication only. If the RxCTOR is loaded

with zero, the counter never starts, and does not generate an interrupt. If the RxCTOR is

loaded with any non-zero value, the down-counter starts when the first character is

received, but gets reloaded with the value in the RxCTOR every time a new character is

received. If the down-counter reaches zero, that channel’s Rx Char Time Out Interrupt

gets asserted (Global DMA Interrupt Register b its [7 :4]).

76543210

Starting Value for Rx Character Time Out Timer

94 Chapter 4: Direct Memory Access (DMA) Controller

DMA Register Descriptions

Chapter 5: Serial Communications Controller (SCC) 95

Chapter 5

Serial Communications Controller

(

SCC

)

Contents

5.1 Introductio n..................................................................................................................................................96

5.2 Features of the SCC....................................................................................................................................96

5.3 SCC Architecture.........................................................................................................................................97

5.4 Communication Modes................................................................................................................................99

5.5 Baud Rate Generator................................................................................................................................111

5.6 SCC Clocks...............................................................................................................................................115

5.7 SCC Interrupts...........................................................................................................................................123

5.8 SCC Write Re

isters.................................................................................................................................129

5.9 SCC Read Re

isters.................................................................................................................................156

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

96 Chapter 5: Serial Communications Controll er (SCC)

Introduction

5.1 Introduction

The XA-SCC has four independent, full duplex serial communication channels, designed

to work seamlessly with the eight channels of on-chip DMA. Each SCC channel is a full

function, multiprotocol, data communications controller, which functions simultaneously

as a serial to parallel (receive) and parallel to serial (transmit) converter. The SCC

handles Asynchronous communication (UART), Synchronous bit oriented protocols such

as SDLC/HDLC, and Synchronous character oriented protocols such as Monosync,

Bisync, and Extern al Sync. The SCC also handles Synchronous bit-streaming

applications fully au tomatically (in conjunction with the XA-SCC’s on-chip DMA) by

virtue of its Transparent mode.

The SCC both generates and checks CRC in all of its Synchronous modes, and can

provide and accept hardware modem control signals in all of its channels.

5.2 Features of the SCC

• Asynchronous features:

– 5, 6, 7, or 8 data bits per character.

– 1, 1.5, or 2 Stop bits per character.

– Even or Odd parity generate and check.

– Parity, Rx Overrun, and Framing Error detection.

– Break detection.

– Supports hardware Autobaud detection.

• SDLC/HDLC features:

– Automatic Flag and Abort Character generation and recogniti on.

– Automatic CRC generation and checking.

– Automatic zero-bit insertion and stripping.

– Automatic partial byte residue code generation.

– 14-bit Packe t byte count.

• Synchronous character oriented protocol features:

– Automatic CRC generation and checking.

– One (Monosync) or two (Bisync) sync characters option.

– Exter nal Sync option.

• Transparent mode for bit -s tr eaming appl i cati on s.

Chapter 5: Serial Communications Controller (SCC) 97

SCC Architecture

• Data encoding/decoding options:

– FM0 (Biphase Space)

– FM1 (Biphase Mark)

–NRZ

–NRZI

• Programmable Baud Rate Generator.

• Auto Echo and Local Loopback modes.

• Supports hardware V.54/2047 generation and reception.

• IDL supported on three SCC channels.

5.3 SCC Architecture

A simplified block diagram of a representative SCC channel appears in Figure 5-1, and

shows the following major architectural components:

• Receive (Rx) data is clocked bit-by-bit into the Rx Shift Register, from the external

RxD signal. Each byte, when complete, is transferred to the Rx Data Buffer (RR8)

from where it is fetched by Rx DMA.

• When Tx DMA places a byte of data into the Tx Data Buffer (WR8), it is transferred

to the Tx Shift register and clocked bit-by-bit onto TxD.

• External clock input RTClk can be used as the master clock for either Rx, Tx, or both

sections of the SCC. When an SCC is connected to IDL, RTClk is provided by the IDL

Interface.

• External clock input TRClk can be used as the master clock for either Tx, Rx, or bo th

sections of the SCC. When an SCC is con nected to IDL, TRClk is provided by the IDL

Interface.

• PClk is an internal XA-SCC clock, whose frequency equals one-half that of CClk, the

system clock. PC lk is normally used as the master clock input to the Baud Rate

Generator for non-IDL applications.

•ComClk

is an external clock in put which is available to all four SCCs.

•DCD

is the standard Data Carrier Detect modem control input signal.

•RTS

is the standard Request To Send modem control output signal.

•CTS

is the standard C lear To Send modem control input signal.

•Sync

is the external sync input to the SCC which is used in bot h External Sync and

Transparent modes. BRG, the clock output from the Baud Rate Generator, can be

programmed to appear as an XA-SCC output signal, and shares a physical pin with

Sync.

• SCC interrupts are multiple OR’d be fore being presented to the XA Interrupt

Controller.

98 Chapter 5: Serial Communications Controll er (SCC)

SCC Archit e c tur e

Figure 5-1 Block Diagram of a Typical SCC Channel

RTClk

TRClk

PClk

ComClk

ComClk goes to all 4 SCCs.

RxDMA 8

RR8

Rx Data Buffer

SCC

RxD

TxDMA

Pad Logic

WR8

Tx Data Buffer

Interrupts

TxD

DCD

RTS

Sync or BRG

Pad Logic

CTS

Pad Logic

Tx Shift Register

Rx Shift Register

Chapter 5: Serial Communications Controller (SCC) 99

Comm unicatio n Mo des

5.4 Communication Modes

5.4.1 Asynch ronous Mode

The Asynchronous mode character format is shown below, for 8 data bits / character with

parity.

In Asynchronous mode, the idle state of the transmission line between characters is logic

1 (Mark Idle). Any amount of time can elapse between trans m itted characters. Each

character is preceded by a start bit (always logic 0) and followed by at least one stop bit

(always logic 1). Asyn chronous serial protocol normally requires data to be transmitted

least significant bit first. Characters can be from 5 to 8 data b its in length. Optionally, a

parity bit can be appended to each character, fol lowing the last (most significant) bit.

Receiver operation

Synchronization is established at the receiv er for each character when the 1 to 0 transition

of the start bit is detected on RxD. One half bit-time after the falling edge, RxD is

sampled to insure that the 1 to 0 transition was indeed due to a valid start b it. The first

data bit (the least significant bit) is sampled one bit-time later, and successive data bits

are sampled every bit-time. Thus, sampling occurs near the middle of each bit.

When the full character has been assembled, RxD is sampled for the expected stop bit. If

RxD is Low, then a Framing Error condition exists for that character, and the Framing

Error bit (RR1[6]) gets set to one. This can generate a Special Cond ition Interrupt, if

enabled. If R xD is High, then it is assu med to be a valid stop bit. The assembled character

is transferred to the Rx Data Buffer (RR8) and the DMA Controller is notified that a byte

is ready.

Regardless of the communication mode being employed for a given application, it is always

recommende d that DMA be used.

D0 D1 D2 D3 D4 D5 D6 D7 P

Stop

Start

D0 D1 D2 D3 D4 D5 D6 D7 P

Stop

Start

100 Chapter 5: Serial Communications Controller (SCC)

Communication Modes

A Break condition occurs when a character consisting of all zeroes (Null Character) is

received, followed by a Framing Error. When a Break condition is detected, the Break/

Abort status bit (RR0[7]) is set, generating an External/Status interrupt, if enabled. The

Break condition is removed when a one is received on RxD. However, if the Break/Abort

interrupt is enabled the status bit in RR0 is latched, and must be cleared by the processor

using the Reset External/Status Interrupts command (WR0[5:3] = 010). At the

termination of a Break, the Rx Data Buffer contains a Null Character which will cause a

Parity Error if Odd Parity has been selected and enabled.

In Asynchronous mode with either 7 or 8 data bits, each SCC supports Autobaud

detection via a dedicated on-chip, hardware Autobaud circuit. For a complete discussion

of XA-SCC Autobaud, see Chapter 6, “Autobaud.”

Transmitter operation

The TxD pin is initially in the idle (High) state. When the Tx DMA chan nel writes the

first character to the Tx Data Buffer (WR8), it is transferred to the Tx Shift Register, and

the Tx Buffer Empty bit (RR0[2]) goes high. This signals the Tx DMA channel to write

another byte to the Tx Data Buffer. The start bit, a parity bit (if enabled), and the chosen

number of stop bits are appended to the character, and it is shifted least significant bit

first onto TxD. When the character has been completely sent , the next character is fetched

from WR8 to the Tx Shift Register, and the process continues. When the Tx DMA

channel stops putting characters in WR8, and the last character has been sent,

transm ission stops.

Initializing an SCC channel for Asynchronous mode operation

1. Set up the Tx DMA channel for any of the three DMA transmit modes. Set up the Rx

DMA channel for Periodic Interrupt mode.

2. Select clocking structure using WR0[1], WR14[1], WR0[0], WR11[6:5][4:3] (see

Sections 5.5 and 5.6 for details).

3. Store the BRG Time Constant in WR13 and WR12.

4. Select Asynchronous mode by choosing 1, 1.5, or 2 Stop Bits per Character using

WR4[3:2]. This only effects the Stop Bits for the Transm itter. The Receiver always

checks for one Stop Bit.

5. Choose either 1x, 4x, 8x, or 16x Clock mode using WR4[7:6]. The Clock mode

chosen will be common to both the Receiver and Transmitter. Rule: RxClk and

TxClk must be at least 2.5 times slower than PClk. This can be achieved by using

PClk as the input to the Baud Rate Generator, and using BRGOut to drive RxClk and

TxClk (see Sections 5.5 and 5.6 for details).

6. If desired, choose parity sense and enable parity using WR4[1:0].

Chapter 5: Serial Communications Controller (SCC) 101

Comm unicatio n Mo des

7. Choose number of data bits per Rx character using WR3[7:6].

8. Choose number of data bits per Tx character using WR5[6:5].

9. Enable the SCC channel’s Receiver using WR3[0] = 1.

10. Enable th e SCC channel’s Transmitter using WR5[3] = 1.

5.4.2 SDLC/HDLC Mode

When an SCC channel is operating in SDLC/HDLC mode, the following operations are

handled autom a tically at the hardware level:

• Openi ng Flag and Cl os i ng Fl ag tr ans mi ss i on and detect io n.

• Abort signal transmission and detection.

• Transmit zero stuffing and Receive zero stripping.

• Transmit CRC generating and Receive CRC checking if enabled.

If the SCC is operated in the normal manner in conjunction with DMA, then all SDLC/

HDLC data are sent in Packets, and a Packet can consist of one or more Fragments.

Packets begin and end with the eight bit SDLC/HDLC Flag character 01111110b = 7Eh,

which is appended automatically by the SCC. Data between Flags never consist of greater

than five consecutive ones, regardless of character boundaries. The sequence of six or

more consecutive one bits is reserved for the SDLC/HDLC Flag and Abort (01111111b =

7Fh) characters.

The SDLC/HDLC Packet format is shown below.

There are two SDLC/HDLC symbols (bit patterns) that can end a Packet:

01111110 = Flag (Normal Ending)

01111111 = Abort.

Both symbols consist of at least six consecutive ones. In order to prevent the receiver

from detecting these patterns in the normal incoming data stream, the process of “zero

insertion” a.k.a. “zero stuffing” is used.

For zero insertion, the tran sm itter inserts a zero after every fifth consecutive one in the

data stream. The receiver removes a zero, if it was preceded by five ones. When the

transmitter is send ing a Closing Flag or an Abort, it does not insert a zero after the fifth

one. Thus, the receiver will always recognize either 01111110 (Flag) or 01111111 (Abort)

as a terminating symbol.

Opening

Flag

01111110 Data 16 bits of CRC

(if enabled)

Closing

Flag

01111110

102 Chapter 5: Serial Communications Controller (SCC)

Communication Modes

SDLC/HDLC Transmit sequence

Between packets , the SC C Transmitter is in th e idle s tate, transm itting either continuous

ones (Mark Idle) or continuous Flag characters (Flag Idle) depending on the state of

WR10[3]. When the first byte of a new Packet is written to the Tx Data Buffer (WR8) by

the Tx DMA channel, the transmit sequence proceeds as follows:

• The Flag charact er from WR7 is transferred to the Tx Shift Register, and transmitted

on TxD.

• The first character (in WR8) is transferred to the Tx Shift Register, and the Tx Buffer

Empty bit (RR0[2]) goes high. This signals the associated Tx DMA channel to write

another byte to the Tx Data Buffer (WR8).

• The byte in the Tx Shift Reg ister is shifted most significant bit first onto Tx D.

• When the character has been completely sent, the next character is fetched from WR8

to the Tx Shift Register, and the process continues.

• Eventually, the Tx DMA chann e l will have no more data for the SCC. When the SCC

has transmitted th e final data byte, it decides, based on the val ue of the LastFrag bit

(see Chapter 4 for details), whether to do a Normal Ending or issue an Abort.

•If LastFrag

= 0, then this was a Normal Ending, and the SCC transmits the CRC (if

enabled) followed by a Closing Flag.

•If LastFrag

= 1, then a transmit underrun error has occurred, and the SCC transmits an

Abort.

• In either case, once the final bit of the Closing Flag or Abort has been sent, the SCC

signals the DMA, so that the DMA can issue a Tx Interrupt (if enabled) to the

processor.

• If the DMA channel do es not immediately start a new packet, the transmitter reverts to

the idle state.

SDLC/HDLC Receive sequence

When the transmission line is in the idle (Mark Idle or Flag Idle) state between packets,

the receiver is normally in a watching state, monitoring RxD for an Opening Flag (Flag

character followed by data) which marks the beginning of a new Packet. When the

receiver is enabled in SDLC/HDLC mode, it always starts in this watching state.

When the Opening Flag is detected, the following occurs:

• The Receiver leaves the watching state, clearing the Sync/Hunt bit and generating an

External/Status Interrupt, if enabled. For normal D MA operation, this interrupt has no

value.

• Characters are assembled one byte at a time from the RxD bit stream most significant

bit first, using the number of Rx Bits/Character specified in WR3[7:6].

• Reception continues until either a Closing Flag or an Abort character is detected.

Chapter 5: Serial Communications Controller (SCC) 103

Comm unicatio n Mo des

• If an Abort character is detected, the Receiver reverts to the watching state, setting

RR0[4], and generating an External/Status Interrupt, if enabled.

• If a Closing Flag is detected, an Rx (Special Condition) Interrupt is generated, if

enabled, and the receiver reverts to the watching state. With normal DMA operation,

this interrupt has no value.

Initializing an SCC channel for SDLC/HDLC mode operation

1. Enable the Rx DMA channel in SDLC/HDLC mode. Enable the Tx DMA channel in

Tx Chaining mode (See DMA chapter for details).

2. Enable Synchronous modes using WR4[3:2] = 00.

3. Select SDLC/HDLC mode using WR4[5:4] = 10.

4. Select clocking structure (See Section 5.6 SCC Clocks for details).

If using IDL

WR0[1] = 0 (RClk from IDL via RTClk)

WR11[6:5] = 00 (RxClk from RClk)

WR11[4:3] = 01 (TxClk from IDL via TRClk)

WR4[7:6] = 00 (1x Clock Mode)

WR14[1], WR13, WR12 = X (not using BRG)

If using non-IDL (for example, clock coming in on TRClk)

WR11[4:3] = 01 (TxClk from TRClk)

WR11[6:5] = 01 (RxClk from TRClk)

WR4[7:6] = 00 (1x Clock Mode)

WR14[1], WR13, WR12 = X (not using BRG)

5. Select the CRC Preset mode, the CRC Polynomial, the Data Encoding mode, the

SDLC/HDLC Idle mode, and the Bit Order.

WR10[7] = 1 (CRC checker and generator preset to all ones)

WR5[2] = 0 (Select SDLC/HDLC polynomial)

WR10[6:5] = 00 (Select NRZ encoding)

WR10[3] = 1 (Select Mark Idle)

WR14[7] = 1 (Select MSbit First)

6. Write the SDLC/HDLC Flag character (7Eh) to WR7.

7. Select the Rx Bits/Character using WR3[7:6],

8. Select the Tx Bits/Character using WR5[6:5].

9. Enable or disable Rx CRC using WR3[3] = 1 or 0.

10. Enable the Receiver using WR3[0] = 1.

11. Enable the Transmitter using WR5[3] = 1.

104 Chapter 5: Serial Communications Controller (SCC)

Communication Modes

5.4.3 Monosync Mode

The message block format for Monosync mode is shown below.

When an SCC channel is operating in Monosync mode, the following operations are

handled autom a tically at the hardware level:

• Receive Sync character detection and Transmit Sync character transmission.

• Receive CRC checking and Transmit CRC generating, if enabled.

• Receive Sync character stripping, if enabled (Sync Char Load Inhibit).

Monosync mode transmit sequence

The state of the transmission line with the Transmitter disabled is TxD high. When the

Transmitter is enabled in Monosync mode, the following occurs:

• The Sync character, which has been previously stored in WR6, is continuously

transmitted until the first data character is written to the Tx Data Buffer (WR8).

• The first character (in WR8) is transferred to the Tx Shift Register, and the Tx Buffer

Empty bit (RR0[2]) goes high. This signals the associated Tx DMA channel (or the

processor) to write anot her byte to the Tx Data Buffer.

• The b yte is shifted most significa nt bit first ont o TxD.

• When the character has been completely sent, the next character is fetched from WR8

to the Tx Shift Register, and the process continues.

• When the last character has been sent (i.e., the Tx Shift Register is empty AND Tx

Buffer Empty = 1), the Tx Underrun/EOM bit (RR0[6 ]) gets set, and generates an

External/Status Interrupt if enabled.

• If the Tx CRC Enable bit (WR5[0]) = 0, then no CRC is sent.

• If the Tx CRC Enable bit (WR5[0]) = 1, then CRC is transm itted.

Monosync mode receive seq uence

When the transmission line is in the idle state (TxD high) between m e ssages, the

Receiver is normally in Hunt mode, monitoring RxD for the Receive Sync character,

which has previously been stored in WR7.

The Receiver is put into Hunt mode b y setting WR3[4] = 1 (Enter Hunt Mo de com mand),

by a channel reset, or by enabling the Receiver (WR3[0] = 1). When a Sync character is

detected, the Receiver automatically leaves Hunt mode, and will remain out of Hunt

mode for the duration of the message.

Sync

8 bits Data 16 bits of

CRC

Chapter 5: Serial Communications Controller (SCC) 105

Comm unicatio n Mo des

The Hunt mode status of the Receiver is reported via RR0[4], the Sync/Hunt bit. A one in

this bit means that the Receiver is in Hunt Mode. The Sync/Hunt bit gets cleared when

the Receiver leaves Hunt mode.

Both state transitions of the Sync/Hunt bit will generate an External/Status Interrupt, if

enabled. Therefore, issuing the Enter Hunt Mode command with the Sync/Hunt Interrupt

enabled will cause an immediate External/Status Interrupt.

When a Sync character is detected, the foll owing occurs:

• The Receiver leaves Hunt mode, clearing the Sync/Hunt bit and generating an

External/Status Interrupt, if enabled.

• Characters are assembled one byte at a time from the RxD bit stream most significant

bit first, using the number of Rx Bits/Character specified in WR3[7:6].

• Reception continues until the entire message has b een received, at which time the

Receiver is typically put back into Hunt mode.

Initializing an SCC channel for Monosync mode operation

1. Enable Synchronous modes using WR4[3:2] = 00.

2. Select Monosync mode using WR4[5:4] = 00.

3. Select clocking structure WR0[1], WR14[1], WR0[0], WR11[6:5][4:3]

4. In Monosync mode, the 1x clock mode is forced internally, so WR4[7:6] are ignored.

5. Select the CRC Preset mode, the Data Encoding mode, and the Sync character length

using WR10[7][6:5][0].

6. Store the Transmit Sync character in WR6.

7. Store the Receive Sync character in WR7.

8. Select the Rx Bits/Character using WR3[7:6], Rx CRC Enable using

WR3[3] = 1, and Sync Char Load Inhibit using WR3[1] = 1.

9. Select the Tx Bits/Ch a ract er using WR5[6:5], select the CRC polynomial using

WR5[2], and Tx CRC enable using WR5[0] = 1.

10. Put the Receiver into Hunt mode using WR3[4] = 1.

11. Enable the Receiver using WR3[0] = 1.

Note: If the 6-bit Sync character option is selected (WR10[0] = 1), only the low order 6 bits of

WR6 are used by the Transmitter, and only the high order 6 bits of WR7 are used by the rece iver.

WR6 and WR7 must be preloaded as indicated in Table 5-5 and Table 5-6.

106 Chapter 5: Serial Communications Controller (SCC)

Communication Modes

12. Enable the Transmitter using WR5[3] = 1.

13. Reset the Tx CRC Generator using WR0[7:6] while the Transm itter is enabled and

sending Sync characters.

5.4.4 Bisync Mode

The message block format for Bisync mode is shown below.

When an SCC channel is operating in Bisync mode, the following operations are handled

automatically at the hardware level:

• Receive Sync character detection and Transmit Sync character transmission.

• Receive CRC checking and Transmit CRC generating, if enabled.

• Receive Sync character stripping, if enabled (Sync Char Load Inhibit).

Bisync mode transmit sequence

The state of the transmission line with the Transmitter disabled is TxD high. When the

Transmitter is enabled in Bisync mode, the following occurs:

• The 12 or 16-bit Sync character, which is formed by the concatenation of

[WR7][WR6], is contin uously transmitted until the first data character is writ ten to the

Tx Data Buffer (WR8).

• The first character (in WR8) is transferred to the Tx Shift Register, and the Tx Buffer

Empty bit (RR0[2]) goes high. This signals the associated Tx DMA channel (or the

processor) to write anot her byte to the Tx Data Buffer.

• The b yte is shifted most significa nt bit first ont o TxD.

• When the character has been completely sent, the next character is fetched from WR8

to the Tx Shift Register, and the process continues.

• When the last character has been sent (i.e., the Tx Shift Register is empty AND Tx

Buffer Empty = 1), the Tx Underrun/EOM bit (RR0[6 ]) gets set, and generates an

External/Status Interrupt if enabled.

• If the Tx CRC Enable bit (WR5[0]) = 0, then CRC is not transmitted.

• If the Tx CRC Enable bit (WR5[0]) = 1, then CRC is transm itted.

Bisync mode receive sequence

When the transmission line is in the idle state (TxD high) between m e ssages, the

Receiver is normally in Hunt mode, monitoring RxD for the Sync character, which is

formed by the concatenation of [WR7][WR6].

Sync

8 bits Sync

8 bits Data 16 bits of

CRC

Chapter 5: Serial Communications Controller (SCC) 107

Comm unicatio n Mo des

The Receiver is put into Hunt mode b y setting WR3[4] = 1 (Enter Hunt Mo de com mand),

by a channel reset, or by enabling the Receiver (WR3[0] = 1). When a Sync character is

detected, the Receiver automatically leaves Hunt mode, and will remain out of Hunt

mode for the duration of the message.

The Hunt mode status of the Receiver is reported via RR0[4], the Sync/Hunt bit. A one in

this bit means that the Receiver is in Hunt Mode. The Sync/Hunt bit gets cleared when

the Receiver leaves Hunt mode.

Both state transitions of the Sync/Hunt bit will generate an External/Status Interrupt, if

enabled. Therefore, issuing the Enter Hunt Mode command with the Sync/Hunt Interrupt

enabled will cause an immediate External/Status Interrupt.

When a Sync character is detected, the foll owing occurs:

• The Receiver leaves Hunt mode, clearing the Sync/Hunt bit and generating an

External/Status Interrupt, if enabled.

• Characters are assembled one byte at a time from the RxD bit stream MSbit first, using

the number of Rx Bits/Character specified in WR3[7:6].

• Reception continues until the entire message has b een received, at which time the

Receiver is typically put back into Hunt mode.

Initializing an SCC channel for Bisync mode operation

1. Enable Synchronous modes using WR4[3:2] = 00.

2. Select Bisync mode using WR4[5:4] = 01.

3. Select clocking structure WR0[1], WR14[1], WR0[0], WR11[6:5][4:3].

4. In Bisync mode, the 1x clock mode is forced internally, so WR4[7:6] are ignored.

5. Select the CRC Preset mode, the Data Encoding mode, and the Sync character length

using WR10[7][6:5][0]. Note: If the 12-bit Sync character option is selected

(WR10[0] = 1), the Receiver will recognize the 12-bit character, but the Transmitter

will still send a 16-bit Sync character. The Sync character m ust be stored in WR6 and

WR7 as outlin ed in Table 5-5 and Table 5-6.

6. Store the low order byte of the Sync character in WR6.

7. Store the high order byte of the Sync character in WR7.

8. Select the Rx Bits/Character using WR3[7:6], Rx CRC Enable using

WR3[3] = 1, and Sync Char Load Inhibit using WR3[1] = 1.

9. Select the Tx Bits/Ch a ract er using WR5[6:5], select the CRC polynomial using

WR5[2], and Tx CRC enable using WR5[0] = 1.

10. Put the Receiver into Hunt mode using WR3[4] = 1.

108 Chapter 5: Serial Communications Controller (SCC)

Communication Modes

11. Enable the Receiver using WR3[0] = 1.

12. Enable the Transmitter using WR5[3] = 1.

13. Reset the Tx CRC Generator using WR0[7:6] while the Transm itter is enabled and

sending Sync characters.

5.4.5 External Sync Mode

The External Sync mode message format is shown below.

In External Sync mode, external logic delivers the character synchronization signal to the

Receiver by means of the Sync input function o n the appropriate multifunction pin. If the

multifunction pin h as been p rop erly con figu red as an in put, an d a zer o has been written to

WR0[2], then the Sync signal will appear (inverted) as the SCC channel’s Sync input

(See Chapter 11, “XA-SCC Pins,” for details). The inverted state of the Sync input is

reported in RR0[4], the Sync/Hunt bit.

There are two varieties of External Sync mode:

• SDLC External Sync mode

Both the receiver and transmitter operate in SDLC/HDLC mode. The only difference

from normal SDLC/HD L C operation is that the Sync pin is used to begin and end the

reception of a Packet, in lieu of the Flag character. The transmitter’s SDLC/HDLC

operation is norma l.

• Monosync External Sync mode

Both the receiver and transmitter operate in Monosync mode. Either the Sync input, a

match with the character stored in WR7, or both, will start the reception of a message.

External Sync mode receive sequence

To begin character reception in External Sync mode, the receiver must be in Hunt mode.

The receiver is put into Hunt mode by setting WR3[4] = 1 (Enter Hunt Mode command),

by a channel reset, or by enabling the receiver (WR3[0] = 1).

The Hunt mode status of the receiver is reported via RR0[4], the Sync/Hunt bit. A one in

this bit means that the Receiver is in Hunt Mode. The Sync/Hunt bit gets cleared when

the receiver leaves Hunt mode.

Don’t Care X

Don’t Care Data Data Data Data CRC Low

8 bits CRC High

8 bits

Sync goes low

Chapter 5: Serial Communications Controller (SCC) 109

Comm unicatio n Mo des

Both state transitions of the Sync/Hunt bit will generate an External/Status Interrupt, if

enabled. Therefore, issuing the Enter Hunt Mode command with the Sync/Hunt Interrupt

enabled will cause an immediate External/Status Interrupt.

When the receiver is in Hunt mode, and the SYNC pin is driven lo w, the following

occurs:

• The Receiver leaves Hunt mode, clearing the Sync/Hunt bit and generating an

External/Status Interrupt, if enabled.

• Character assembly begins on the next rising edge of RxClk.

• Characters are assembled one byte at a time from the RxD bit stream most significant

bit first, using the number of Rx Bits/Character specified in WR3[7:6].

• Reception continues until the entire message has b een received, at which time the

Enter Hunt Mode command is issued, forcing the Receiver back into Hunt mode.

Initializing an SCC channel for External Sync mode operation

1. Enable Synchronous modes using WR4[3:2] = 00.

2. Select External Sync mode using WR4[5:4] = 11.

3. Select either SDLC/HDLC or Monosync External Sync mode using WR4[7:6].

WR4[7:6] = 00: Monosync External Sync Mode, using SYNC input only.

WR4[7:6] = 01: Monosync External Sync Mode, using SYNC input only.

WR4[7:6] = 10: Monosync External Sync Mode, using WR7 or SYNC input .

WR4[7:6] = 11: SDLC/HDLC External Sync Mode.

4. Proceed with initialization as per SDLC/HDLC mode or Monosync mode operation.

5.4.6 Transparent Mode

The Transparent mode message format is shown below.

In Transparent mode, a bit is received (and transmitted) on every clock cycle, regardless

of Sync characters or Flags. No Sync input is required, and reception (and/or

transmission) continues indefinitely. Transparent mode is ideal for bit-streaming

applications. This mode is also sometimes called “Clear Channel.”

Data Data Data Data Data Data Data Data

110 Chapter 5: Serial Communications Controller (SCC)

Communication Modes

Transparent Mode receive sequence

Transparent mode reception begins the same way as Monosync External Sync mode,

during which the receiver must be in Hunt mode. The receiver is put into Hunt mode by

setting WR3[4] = 1 (Enter Hunt Mode command), by a channel reset, or by enabling the

receiver (WR3[0] = 1).

The receiver is initialized as per Monosync External Sync mode, the Enter Hunt mode

command is issu ed, and then Transparent mode is enabled by writing a one to WR0[2],

the Force Sync bit (this forces the SCC channel’s Sync signal active high). The following

then occurs:

• The Receiver leaves Hunt mode, clearing the Sync/Hunt bit and generating an

External/Status Interrupt, if enabled.

• Character assembly begins on the next rising edge of RxClk.

• Characters are assembled one byte at a time from the RxD bit stream MSbit first, using

the number of Rx Bits/Character specified in WR3[7:6].

• Reception continues indefinitely, until the processor disables Transparent mode by

writing a zero to WR3[0], disabling the receiver.

Initializing an SCC channel for Transparent mode operation

1. Enable Synchronous modes using WR4[3:2] = 00.

2. Select External Sync mode using WR4[5:4] = 11.

3. Select M onosync External Sync mode using WR4[7:6] = 00.

4. Select clocking structure WR0[1], WR14[1], WR0[0], WR11[6:5][4:3] (the 1x clock

mode is forced inte rnally, so W R4 [ 7:6] are ignored).

5. Select the Data Encoding mode using WR10[6:5].

6. Select the Rx Bits/Character using WR3[7:6].

7. Select the Tx Bits/Character using WR5[6:5].

8. Put the Receiver into Hunt mode using WR3[4] = 1.

9. Enable the Receiver using WR3[0] = 1.

10. Enable the Transmitter using WR5[3] = 1.

11. Force Sync active by setting WR0[2] = 1.

Chapter 5: Serial Communications Controller (SCC) 111

Baud Rate Generator

5.5 Baud Rate Generator

5.5.1 BRG and Autobaud

For each SCC channel, the Autobaud block, when enabled, automatically sets up the

channel’s Ba ud Rate Generator. The initialization of the SCC for Autobaud is covered in

Chapter 6, “Autobaud.”

5.5.2 The SCC Baud Rate Generator

Each SCC channel contains a programmable Baud Rate Generator (BRG) for use in

Asynchronous mode communications. The BRG is shown in Figure 5-2.

Figure 5-2 Baud Rate Generator

Each BRG uses a 10-bit downcounter (BRGDivdr), in conjunction with a 10-bit Baud

Rate Generator Time Constant (BRGTC), and an optional 7/8 prescaler.

BRGOut is always in the high logic state on s tart-up. Each time the downcounter reaches

zero, the BRGOut flip flop toggles, and BRGDivdr is automatically re-loaded with

BRGTC. BRGTC is formed by the concatenation WR13[1:0]WR12[7:0].

The BRGTC can only be changed while the Baud Rate Generator is disabled (not

running).

RTClk

ComClk

PClk

RClk

WR0[1]

7/8 Prescaler

WR14[1]

7/8Clock BRGClk Clock

BRGOut

1Clock

WR0[0]

/ 10

BRG

Divdr

BRGTC

WR13[1:0]WR12[7:0]

11Clock 234567812345678 1

17/8Clock 234567 1234567 1

112 Chapter 5: Serial Communications Controller (SCC)

Baud Rate Generator

For most Asynchronous applicati ons , t he best way to generate the Bit Clocks for t he SCC

shift registers is by using PClk to clock the Baud Rate Generator’s downco unter. There

are three layers of clock selection that must be programmed in order to generate the

BRGClk signal, which is the clock input to the downcounter. The procedure used for

selecting the clock at each layer can best be followed while referring to Figure 5-2.

WR0[1] selects either RTClk or Co mCl k to be RClk.

WR14[1] selects either RClk o r PClk to feed BRGClk.

WR0[0] selects either 1Clock or 7/8Clock (optional 7/8 prescaler) as

BRGClk signal.

The formulas relating the BRGClk and BRGOut frequencies to the BRGTC time constant

are:

The final step in bau d rate gene ration involves selecting BRGOut as the RxClk and

TxClk signals , and selecting the Clock mode using WR4[7:6]. Although these topics will

be covered in the following section on SCC Clocks, the result is included here for

completeness (see Figure 5-4).

WR11[ 6:5] = 10 selects BRGOut as RxClk

WR11[ 4:3] = 10 selects BRGOut as TxClk

0 selects RTClk.

1 selects ComClk.

0 selects RClk.

1 selects PClk.

0 selects 1Clock as BRGClk.

1 selects 7/8Clock as BRGClk.

BRGOut BRGClk

2 BRGTC 2+

()

-------------------------------------=

BRGTC BRGClk

2 BRGOut

()

----------------------------- 2–

Chapter 5: Serial Communications Controller (SCC) 113

Baud Rate Generator

WR4[7:6] selects Clock mode (common to Rx and Tx)

Although the names imply multiplication, the Clock mo de is actuall y a further “divide

by” stage that is applied to RxClk and TxClk in generating the bit clock rate.

In general, for Asynchronous applications, the final divisor (WR4[7:6]) should be kept as

high as possible (“divide by 16” whenever possible), and must never be “divide by 1.”

The following table lists the recommended values for BRGTC and Clock mode when

BRGClk = PClk = 14.7456 MHz. Notice that the optional 7/8 prescaler is not selected.

(00) selects 1x Clock mode (divide by 1)

(01) selects 4x Clock mode (divide by 4)

(10) selects 8x Clock mode (divide by 8)

(11) selects 16x Clock mode (divide by 16)

Table 5-1 BRG Programming for BRGClk = PClk = 14.7456 MHz

(CClk = 29.4912 MHz)

BPS rate... ...is PClk divided by

BRGTC

WR13 WR12

Clock mode

WR4[7:6]

921,600 16 00 00h (÷ 4) 01 (÷ 4)

460,800 32 00 00h (÷ 4) 10 (÷ 8)

307,200 48 00 01h (÷ 6) 10 (÷ 8)

230,400 64 00 00h (÷ 4) 11 (÷ 16)

153,600 96 00 01h (÷ 6) 11 (÷ 16)

115,200 128 00 02h ( ÷ 8) 11 (÷ 16)

76,800 192 00 04h (÷ 12) 11 (÷ 16)

57,600 256 00 06h (÷ 16) 11 (÷ 16)

38,400 384 00 0Ah (÷ 24) 11 (÷ 16)

28,800 512 00 0Eh (÷ 32) 11 (÷ 16)

19,200 768 00 16h (÷ 48) 11 (÷ 16)

14,400 1,024 00 1E h (÷ 64) 11 (÷ 16)

9,600 1,536 00 2Eh (÷ 96) 11 (÷ 16)

7,200 2,048 00 3Eh (÷ 128) 11 (÷ 16)

4,800 3,072 00 5Eh (÷ 192) 11 (÷ 16)

3,600 4,096 00 7Eh (÷ 256) 11 (÷ 16)

Warnings: PClk must always be at least 2.5 tim es faster than RxClk and TxClk. Always let

WR4[7:6] = 11 for BPS rat es of 230,400 and slower.

114 Chapter 5: Serial Communications Controller (SCC)

Baud Rate Generator

5.5.3 Baud Rate Genera tor Example

This example can best be followed while referring to Figure 5-2.

Problem: Initialize the SCC0 Baud Rate Generator to transmit and receive at 921.6 K

bits/second.

Solution:

• The System Clock on the XA-SCC chip is CClk = 29.4912 MHz. The SCC uses PClk,

which is CClk divided by 2. Therefore PClk = 14.7456 MHz.

• PClk is routed to the input of the BRG:

WR0[1] = don’t care, in this case.

WR14[1] = 1.

• The optional 7/8 prescaler is bypassed:

WR0[0] = 0.

Desired BPS rate ( 921.6 K) is P Clk divided by 16, so first divide by 4 with the Baud

Rate Generator Time Constant. Set BRGTC = 00 00h (divides by 4):

WR13[1:0] = 00b

WR12 = 00h.

• BRGOut is routed to both the Tx and Rx clock dividers:

WR11[4:3] = 10 (BRGOut is TxClk, goes to Tx clock divider)

WR11[6:5] = 10 (BRGOut is RxClk, goes to Rx clock divider).

• The Tx and Rx clock dividers are also programmed to divide by 4:

WR4[7:6] = 01 (“4x Clock Mode”).

• Enable Baud Rate Generator:

WR14[0] = 1.

2,400 6,144 00 BEh (÷ 384) 11 (÷ 16)

1,800 (not auto) 8,192 00 FEh (÷ 512) 11 (÷ 16)

1,200 12,288 01 7Eh (÷ 768) 11 (÷ 16)

Table 5-1 BRG Programming for BRGClk = PClk = 14.7456 MHz

(CClk = 29.4912 MHz) (continued)

BPS rate... ...is PClk divided by

BRGTC

WR13 WR12

Clock mode

WR4[7:6]

Warnings: PClk must always be at least 2.5 tim es faster than RxClk and TxClk. Always let

WR4[7:6] = 11 for BPS rat es of 230,400 and slower.

Chapter 5: Serial Communications Controller (SCC) 115

SCC Cl ocks

5.6 SCC Clocks

The System Clock on the XA-SCC chip is called CClk. The SCCs have a slower main

clock, called PClk, which is CClk divided by 2 (PClk = CClk / 2). In most Asynchronous

applications, the SCC channel shift regi ster cl ock s (bit clocks ) wi ll be de rived from PClk.

It is recommended that CClk = 29.4912 MHz. which res ults in PClk = 14.7456 Mhz. The

industry standard baud rates are sub-multiples of 14.745 6 MHz. In any case, the

following two ru les apply at all times:

• CClk must not exceed 30 MHz. (and therefore PClk must not exceed 15MHz.).

• The Clock mode circuits sample RxClk and TxClk using PClk. Hence, it is essential

that PClk always be at least 2.5 times faster than RxClk and TxClk.

The maximum allowable clock frequencies for the SCC are summarized in Table 5-2.

Table 5-2 Maximum SCC Clock Frequencies

5.6.1 SCC Clock Issues When (and when not) Using IDL

Clocks for Synchronous, non-IDL applications can be brought to an SCC channel on the

channel’s RT Cl k and/or TRClk pins. If an SCC chan nel i s not bei n g us ed wi th IDL, and i t

needs to get its clocks from RTClk and TRClk, then the RTClk and TRClk pins for that

SCC must be configured as inputs. See Chapter 11, “XA-SCC Pins,” for details.

If IDL is going to be used at all, then the L1Clk pin (Pin 95) must be configured as an

input. See Section 11.5.31, “Pin 95: P0.5_RTClk 0_L1Clk” for details.

Clock Description

Maximum for SDLC/

HDLC and other

Synchronous modes Maximum for

Asynchronous mode

CClk System Clock

(pins XTALin and

XTALout)

30 MHz.

(29.4912 MHz.

recommended)

30 MHz.

(29.4912 recommended)

PClk PClk = CClk / 2 15 MHz.

(14.7456 MHz.

recommended)

15 MHz.

(14.7456 MHz.

recommended)

RTClk, TRClk,

and ComClk Si

nals that can be used

as clock inputs to the

SCC.

PClk / 2.5 15 MHz.

(14.7456 MHz.

recommended)

Must be routed throu

BRG if

reater than PClk

/ 2.5 .

RxClk, TxClk Inputs to final clock

dividers for shift

isters.

PClk / 2.5 PClk / 2.5

116 Chapter 5: Serial Communications Controller (SCC)

SCC Clocks

If an SCC channel is being used with IDL, then the IDL Interf ace will automatically

supply the RTClk and TRClk clock inputs to that SCC channel.

There are certain constraints placed on SCC usage when the IDL Interface is being used.

Details can be found in Chapter 8, “IDL Interface,” and are summarized below. Typical

SCC assignments for two common applications can be seen in Section 1.4 of Chapter 1,

“Introduction.”

• If the IDL block as a whole is “on,” then SCC0 is automatically connected to IDL.

– SCC0 is the only SCC which can be assigned to the D Channel. So in order to use

IDL with D Channel, SCC0 must be assigned to it. In that case, SCC1 and SCC2

can be assigned to the B1 and B2 Channels respectively, or either can be assigned

to both the B1 and B2 Channels.

– To use IDL without D Channel, SCC0 can be assig ned to either the B1 Channel, the

B2 Channel, or both.

• SCC3 can never be connected to IDL.

Chapter 5: Serial Communications Controller (SCC) 117

SCC Cl ocks

Figure 5-3 SCC clock options when (and when not) using IDL

5.6.2 SCC0 Clock Discussion

The four figures, Figure 5-4 through Figure 5-7, show the clock structures for the four SCC

channels, including the signal paths through the Pin Mux and IDL blocks. The internal cl ock

structure of all four SCCs is identical. The fol lowing discussion of SCC0 cl ocks is exemplary of

all SCC channels, and can best be followed while referring to Figure 5-4.

IDL

TRClk0

RTClk0

Pad Logic

SCC0

SCC1

TRClk1

RTClk1

Pad Logic

PClk

Clocks In

ComClk

TRClk2

RTClk2

Pad Logic

TRClk3

ComClk

RTClk3

Pad Logic

PClk

Clocks In

ComClk

L1Clk

Pad Logic

SCC2

PClk

Clocks In

ComClk

SCC3

PClk

Clocks In

ComClk

118 Chapter 5: Serial Communications Controller (SCC)

SCC Clocks

5.6.3 SCC0 Clock Inpu ts

There are four clock inputs available to SCC0: RTClk0, TRClk0, ComClk, and PClk.

•RTClk0

and TRClk0: Clocks that can be routed to SCC0 via the Multifunction Pin

Multiplexer (Pin Mux) and IDL blocks.

•ComClk

: Some applications will need to derive a clock from a source external to the

XA-SCC chip. Since one external clock of ten suffices for several or all SCCs, ComClk

is routed to all four SCC channels.

• PClk: The main on-chip clock for all four SCC channels, used in most Asynchronous

applications to driv e the Baud Rate Generato r’s d owncounter. PC lk = CClk / 2.

Either RTClk0 or C omC lk can be used to form the signal RClk. WR0[1] is used to select

the source for RClk.

Either RClk or PClk can be selected to feed the Baud Rate Generator, using WR14[1].

See Section 5.5 for details.

To the right of BRGDivdr, notice the four signals from which TxClk and RxClk can be

formed: RClk, TRClk, BRGOut, and BRGClk. The TxClk source signal is selected using

WR11[4:3] and the RxClk source signal is selected using WR11[6:5].

WR0[1] Description

0 selects RTClk0 as RClk.

1 selects ComClk as RClk.

WR11[43] Description

00 selects RClk as TxClk

01 selects TRClk as TxClk.

10 selects BRGOut as TxClk.

11 selects BRGClk as TxC lk.

WR11[6:5] Description

00 selects RClk as RxClk

01 selects TRClk as RxClk.

10 selects BRGOut as RxClk.

11 selects BRGClk as RxClk.

Chapter 5: Serial Communications Controller (SCC) 119

SCC Cl ocks

The final stage of the SCC input clock selection process is to select the SCC channel’s

“Clock mode.” This inserts a divider onto the TxClk and RxClk signals, in order to

generate the Bit Clocks th at actually drive the Tx and Rx Shift Registers. The Clock

mode is common to both the Tx and Rx sections of the SCC channel, and is selected

using WR4[7:6].

5.6.4 SCC0 Clock Outputs

Two of the clock signals generated in SCC0 can be programmed to appear (inverted) on

the BRG0 output: TxClk, and BRGOut. The S YNCOut sign al can also be pr ogr ammed t o

appear (inverted) on BRG0. The BRG0 signal is selected using WR11[1:0]. Use

WR11[1:0] = 00 if not using o ne of the othe r three func tions.

The BitClk0 ou tput from SCC0 is driven by the same sig nal that clocks the Rx Shift

output is used by the DMA channel 0 Rx Character Time Out Timer (see Chapter 4,

“Direct Memory Access (DMA) Contro ller,” for details).

WR4[7:6] Description

00 selects 1x Clock mode (divide by 1)

01 selects 4x Clock mode (divide by 4)

10 selects 8x Clock mode (divide by 8)

11 selects 16x Clock mode (divide by 16)

WR11[1:0] Description

00 forces BR G0 hi

01 selects TxClk (inverted) as BRG0.

10 selects BRGOut (inverted) as BRG0.

11 selects SYNCOut (inverted) as BRG 0.

120 Chapter 5: Serial Communications Controller (SCC)

SCC Clocks

Figure 5-4 SCC0 Clocks (see Sections 5.6.3 and 5.6.4)

P0[5]

P0[4]

P0CFGA[5]

P0CFGB[5]

P0.5_RTClk0_L1Clk

PIN 95

Pads

ComClk

PClk

SDS2

BRG0

Sync0

RTClk0

P0CFGA[0]

P0CFGB[0]

P0[0]

P0.0_Sync0_BRG0_SDS2

PIN 90

P0CFGA[4]

P0CFGB[4]

P0.4_TRClk0_SDS1

PIN 94

IDL Rx

ClkGen 1

IDLOn

IDLOff

IDL Tx

ClkGen

IDL

TRClk0

IDLOn

1Clock

SCC0

BRG

Divdr

x7/8 BRGClk BRGOut

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

WR13[1:0]

WR[12]

/10

WR0[0]

WR14[1]

WR0[1]

ByteClk

DMA0

Char Time Out 0

Programmable

Char Time Out

TxClk

BRGOut

SyncOut

Sync

WR11[1:0]

WR11[4:3]

BRGClk

BRGOut

TRClk

RClk Tx Shift

Reg

RxClk SC_BitClk0

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

To TxD0

RxClk

WR11[6:5]

BRGClk

BRGOut

TRClk

RClk Rx Shift

Reg

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

From RxD0

P0[5] DataIn

P0[0] DataIn

P0[4] DataIn

Chapter 5: Serial Communications Controller (SCC) 121

SCC Cl ocks

Figure 5-5 SCC1 Clocks

P3[7]

P3.0_CS4_RAS4_RTClk1

PIN 56

Pads

ComClk

PClk

RTClk1

P3CFGA[3]

P3CFGB[3]

P3[3]

from

Timer1

P3.3_Timer1_BRG1_Sync1

PIN 63

P3CFGA[7]

P3CFGB[7]

P3.7_Int1_TRClk1

PIN 67

IDL Rx

ClkGen 1

SC1isIDL

IDL Tx

ClkGen

IDL

TRClk1

BRG1

SC1isIDL

P3CFGA[0]

P3CFGB[0]

P3[0]

CS4

Sync1

1Clock

SCC1

BRG

Divdr

x7/8 BRGClk BRGOut

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

WR13[1:0]

WR[12]

/10

WR0[0]

WR14[1]

WR0[1]

ByteClk

DMA1

Char Time Out 1

Programmable

Char Time Out

TxClk

BRGOut

SyncOut

Sync

WR11[1:0]

WR11[4:3]

BRGClk

BRGOut

TRClk

RClk Tx Shift

Reg

RxClk SC_BitClk1

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

To TxD1

RxClk

WR11[6:5]

BRGClk

BRGOut

TRClk

RClk Rx Shift

Reg

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

From RxD1

P3[0] DataIn

P3[3] DataIn

P3[7] DataIn

122 Chapter 5: Serial Communications Controller (SCC)

SCC Clocks

Figure 5-6 SCC2 Clocks

P1[2]

P1[3]

P1CFGA[2]

P1CFGB[2]

P1.2_RTClk2

PIN 70

Pads

ComClk

PClk

BRG2

Sync2

RTClk2

P1CFGA[7]

P1CFGB[7]

P1[7]

P1.7_BRG2_Sync2

PIN 75

P1CFGA[3]

P1CFGB[3]

P1.3_TRClk2

PIN 71

IDL Rx

ClkGen 1

SC2isIDL

IDL Tx

ClkGen

IDL

TRClk2

SC2isIDL

1Clock

SCC2

BRG

Divdr

x7/8 BRGClk BRGOut

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

WR13[1:0]

WR[12]

/10

WR0[0]

WR14[1]

WR0[1]

ByteClk

DMA2

Char Time Out 2

Programmable

Char Time Out

TxClk

BRGOut

SyncOut

Sync

WR11[1:0]

WR11[4:3]

BRGClk

BRGOut

TRClk

RClk Tx Shift

Reg

RxClk SC_BitClk2

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

To TxD2

RxClk

WR11[6:5]

BRGClk

BRGOut

TRClk

RClk Rx Shift

Reg

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

From RxD2

P1[7] DataIn

P1[3] DataIn

P1[2] DataIn

Chapter 5: Serial Communications Controller (SCC) 123

SCC Interrupts

Figure 5-7 SCC3 Clocks

5.7 SCC Interrupts

In SDLC/HDLC mode, most or all of the SCC interrupts are not needed with normal

DMA driven operation. The DMA interrupts have been specifically designed to be

complete and sufficient for DMA driven SDLC/HDLC applications.

In Asynchronous mode, some of the SCC’s Receive Interrupts may be needed

(specifically, Special Receive Condition interrupts).

P2[2] DataOut

P2[3] DataOut

P2CFGA[2]

P2CFGB[2]

P2.2_RTClk3

PIN 82

Pads

ComClk

PClk

RTClk3 0

1Clock

SCC3

BRG

Divdr

x7/8 BRGClk BRGOut

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

WR13[1:0]

WR[12]

/10

WR0[0]

WR14[1]

WR0[1]

ByteClk

DMA3

Char Time Out 3

Programmable

Char Time Out

P2[7] DataIn

P2[7] DataOut

P2.7_Sync3_BRG3

PIN 87

BRG3

TxClk

BRGOut

SyncOut

Sync

WR11[1:0]

Sync3

P2CFGA[3]

P2CFGB[3]

P2[3] DataIn

P2[2] DataIn

P2.3_Comclk_TRClk3

PIN 83

TRClk3

WR11[4:3]

BRGClk

BRGOut

TRClk

RClk Tx Shift

Reg

RxClk SC_BitClk3

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

To TxD3

RxClk

WR11[6:5]

BRGClk

BRGOut

TRClk

RClk Rx Shift

Reg

00 = /1

01 = /4

10 = /8

11 = /16

WR4[7:6]

From RxD3

P2CFGA[7]

P2CFGB[7]

124 Chapter 5: Serial Communications Controller (SCC)

SCC Interrupts

5.7.1 SCC Channel Int errupt Groups

SCC interrupts are grouped by pairs of SCC channels. SCC0/SCC1 are a grouped pair,

and SCC2/SCC3 are a grouped pair. Internal to each grouped pair, there is a Master

Interrupt Enable bit (WR9[3]) which globally enables or inhibits all interrupts from that

pair of SCC channels.

All interrupts from SCC0 /SCC1 appear to the XA as the maskable Event interrupt which

is enabled by setting the ESC01 bit in the IEH SFR (hex 427[0]). All interrupt s from

SCC2/SCC3 appear as the maskable Event interrupt which is enabled by setting the

ESC23 bit in the IEH SFR (hex 427[1]).

As with all other XA Event interrupts, the priority levels for ESC01 and ESC23 must be

initialized upon reset. The Interrupt Priority Register fields for ESC01 and ESC23 are

PSC01 (hex 4A4[2:0]) and PSC23 (hex 4A4[6:4]), respectively. Also, the EA (Enable

All) bit in the IEL SFR (hex 4 26[ 7]) must be set before any Event interrupts will be

serviced. The SFR add resses for initializing SCC interrupts are summarized below.

Table 5-3 SFR Addresses for SCC Interrupts

Bit/Field Name

SFR Bit(s)

Byte Address (hex)

Bit Address (hex) Description

ESC01 IEH.0

427[0]

338

Enable bit for SCC0 and 1

ESC23 IEH.1

427[1]

339

Enable bit for SCC2 and 3

EA IEL.7

426[7]

337

Master Enable bit

PSC01 IPA4[2:0]

4A4[2:0]

Priority Re

ister Field for SCC0 and 1

PSC23 IPA4[6:4]

4A4[6:4]

Priority Re

ister Field for SCC2 and 3

Chapter 5: Serial Communications Controller (SCC) 125

SCC Interrupts

5.7.2 IE Bits and IP Bits

IE (Interrupt Enable) bits for the SCC channel reside in WR1 and WR15. If an IE bit is

set, the associated SCC interrupt source may interrupt the processor, assuming all the

required conditions are met. If an IE bit is clear, that interrupt source is disabled.

IP (Interrupt Pending) bits reside in RR3, and are read-only bits. An IP bit is set by the

presence of an SCC in terrup t condition, and is cleared when that condition is removed,

usually through the action of an interrupt service routine.

5.7.3 SCC Interrupt Priorities

Each SCC channel has three varieties of interrupts: Receive, Transmit, and External/

Status. These interrupts are prioritized internally for each grouped pair of SCC channels

in th e fo ll owing mann e r.

5.7.4 SCC Receive Interrupts

SCC Receive interrupts are caused by either the presence of a character in the Rx Data

Buffer (Rx Character Available), or a Special Recei ve Cond ition, or both, in the

following com binations.

• Interrupt on First Rx Character or Speci al Conditi on.

• Interrupt on All Rx Characters or Special Condition.

• Rx Interrupt on Special Condition Only.

The SCC considers the following to be Special Conditions durin g data reception :

• SDLC/HDLC End Of Packet (see Section 5.4.2 SDLC/HDLC Mode).

• CRC Error (SDLC/HDLC, and other Synchronous modes).

• Asynchronous Framing Error (see Section 5.4.1 Asynchronous Mode)

• Rx Overrun, where the character in the Rx Data Buffer is overwritten.

• Rx Parity Error (if enabled by WR1[2] = 1).

Rx Interrupts are controlled with the two-bi t fiel d in WR1[4:3]. The condition which wi ll

cause an Rx Interrupt is selected here, while writing 00 to this field disables Rx Interrupts

(See Se ction 5.8.2 for detai l s).

SCC0 Receive Interrupts Hi

SCC0 Transmit Interrupt

SCC0 External/Status Interrupts

SCC1 Receive Interrupt

SCC1 Transmit Interrupt

SCC1 External/Status Interrupts Low

SCC2 Receive Interrupts Hi

SCC2 Transmit Interrupt

SCC2 External/Status Interrupts

SCC3 Receive Interrupt

SCC3 Transmit Interrupt

SCC3 External/Status Interrupts Low

126 Chapter 5: Serial Communications Controller (SCC)

SCC Interrupts

5.7.5 SCC Transmit Interrupts

Each SCC channel has one source for the Transmit Interrupt, Tx Buffer Empty. If Tx

Interrupt is enabled, the SCC ch ann e l will g e nerate a Tx In terrup t when th e Tx Data

Buf fer becomes empty.

5.7.6 SCC External/Status Interrupts

Each SCC channel has six External/Status Interrupts, which are globally enabled by

setting the Master External/Status Interrupt Enable bit (WR1[0] = 1). Each External/

Status Interrupt is individually enabled or disabled us ing its associated External/St a tus IE

bit in WR15 . The “statuses” of the six External/Status Interrupts can be read in RR0.

Writing a “1” to an External/Status IE bit in WR15 inserts a latch between the source of

the interrupt and the status bit in RR0. The processor can read the current status of the

interrupt source at any tim e, but an interrupt will only be generated, and th e “1” latched

in the RR0 bit, if the External/Statu s IE bit in WR15 has been set.

The latches between the interrupt sources and the RR0 status bits are all updated

simultaneously, whenev er any of the associated interrupt sources (i.e., those with latches

inserted) changes state. Therefore, it is possible for more than one RR0 status bit to

change states between Extern al/Status Interrupt servicings. In order for the processor to

determine which RR0 status bits have changed states since the last External/Status

Interrupt was serviced, the interrupt service routine must keep an image of the current

state of RR0. The next time an External/Status Interrupt is serviced, the image can be

compared to the current state. The latches are cleared by issuing a Reset External/Status

Interrupts command (WR0[5:3] = 010).

When any of the latches are set, the External/Status IP bit in RR3 for that SCC channel is

also set. However , if the Master External/Status Interrupt Enable bit (WR1[0]) is zero, the

External/Status IP bit will never be set, even though there may be latches inserted and

operating, as outlined above. The six External/Statu s Interrupts are summarized in the

Table 5-4.

Chapter 5: Serial Communications Controller (SCC) 127

SCC Interrupts

Table 5-4 External/Status Interrupts

For operational details about the individual External/Status interrupts, and the External/

Status Interrupt Status bits, see Section 5.9.1, “Read Register 0: Interrupt Status Bits”.

The interrupt structure for the grouped pair SCC0/SCC1 appears in Figure 5-8 as an

example. The structure for SCC2/SCC3 is identical. Figure 5-9 shows how interrupts

from both SCC interrupt groups are presented to the XA Interrupt Controller.

Name External Status IE bit External/Status Interrupt Status bit

Break/Abort WR15[7] RR0[7]

Tx Underrun/EOM WR15[6] RR0[6]

CTS WR15[5] RR0[5]

Sync/Hunt WR15[4] RR0[4]

DCD WR15[3] RR0[3]

Zero Count WR15[1] RR0[1]

128 Chapter 5: Serial Communications Controller (SCC)

SCC Interrupts

Figure 5-8 SCC0/SCC1 Interrupt Structure

Break/Abort RR0[7]

Break/Abort IE WR15[7]

Tx Underrun/EOM RR0[6]

Tx Underrun/EOM IE WR15[6]

CTS RR0[5]

CTS IE WR15[5]

Sync/Hunt RR0[4]

Sync/Hunt IE WR15[4]

DCD RR0[3]

DCD IE WR15[3]

Zero Count RR0[1]

Zero Count IE WR15[1]

Break/Abort RR0[7]

Break/Abort IE WR15[7]

Tx Underrun/EOM RR0[6]

Tx Underrun/EOM IE WR15[6]

CTS RR0[5]

CTS IE WR15[5]

Sync/Hunt RR0[4]

Sync/Hunt IE WR15[4]

DCD RR0[3]

DCD IE WR15[3]

Zero Count RR0[1]

Zero Count IE WR15[1]

RR1[7]

RR1[6]

RR1[5]

RR1[4]

Rx Char. Avail. RR0 [0]

(SCC0)

Tx Buffer Empty RR0[2]

(SCC0)

Tx Buffer Empty RR0[2]

(SCC1)

SCC0

WRI

Logic

RR3[5]

Even CH.

Rx IP

RR3[4]

Even CH.

Tx IP

RR3[1]

Odd CH.

Tx IP

SCC0

WR1[1]

Tx INT enable

WR1[1]

Tx INT enable

SCC0

WR1[0]

Master Ext/Stat

RR3[3]

Even CH.

Ext/Stat

Rx Special Conds

(SCC1)

WR1[0]

Master Ext/Stat

RR3[0]

Odd CH.

Ext/Stat

RR1[7]

RR1[6]

RR1[5]

RR1[4]

Rx Char. Avail. RR0[0]

(SCC1) SCC1

WRI

Logic

RR3[2]

Odd CH.

Rx IP

Rx Special Conds

(SCC0)

SCC1

SCC0

SCC1

SCC0/SCC1

Chapter 5: Serial Communications Controller (SCC) 129

SCC Writ e Registers

Figure 5-9 Continuation of SCC Interrupt Structure, Showing Both SCC

Interrupt Groups

5.8 SCC Write Registers

Each SCC channel contains 18 Write Registers. One Write Register (WR9) is shared by

the grouped pair SCC0/SCC1 and one is shared by SCC2/SCC3. The following sections

describe each Write Register in detail, on a bit-by-bit basis where applicable.

Interrupt Signal

To Processor

SCC0/SCC1

WR9[3]

Master Int. Enable

SCC0/SCC1

Prioritizer

SCC0/SCC1

SCC2/SCC3

XA Interrupt Controller

SCC0 Rx (Highest)

SCC0 Tx

SCC0 Ext/Stat

SCC1 Rx

SCC1 Tx

SCC1 Ext/Stat (Lowest)

ESC01

From Other Event

Interrupt Sources

ESC23

SCC2/SCC3

WR9[3]

Master Int. Enable

SCC2/SCC3

Prioritizer

SCC2 Rx (Highest)

SCC2 Tx

SCC2 Ext/Stat

SCC3 Rx

SCC3 Tx

SCC3 Ext/Stat (Lowest)

...

130 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

5.8.1 Write Register 0: Command Register

WR0 is the C omm and Reg ister, and con t ains the C RC reset co mman d co de field. Bits 7-3

are “command field bits,” which w ill always be read as zeroes. Writing a on e has an

immediate hardware effect, but the value is not latched. Bits 2-0 are “normal register

bits” which are latched and can be read by the processor.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000

001

010

011

100

101

110

111

7/8 Prescale Enable

RClk Select

Force Sync

Null code

Reserved

Reset Externa l/S ta tus Inte rr upts

Send Abort

Enable Interrupt on Next Rx Character

Reset Tx Interrupt Pendi ng

Error Reset

Reserved

Null Code

Reset Rx CRC Checker

Reset Tx CRC Generator

Reset Tx Underrun/EOM Latch

Chapter 5: Serial Communications Controller (SCC) 131

SCC Writ e Registers

WR0[7:6] - CRC Reset Code Bits

WR0[5:3] - Command Code Bits

00 Null Code. Use this code when writin

to other bits in WR0, as the bit pattern

has no effect on the SCC channel.

01 Reset Rx CRC Checker. Not relevant with normal SDLC/HDLC DMA

operation.This command reset s the receive CRC checker . Any act ion which

disables the receiver will reset the CRC circuit. In SDLC mode, the CRC

checker is aut omatical ly reset upon reception of a Fla

or upon enterin

Hunt

mode. This command is necessary in non-SDLC synchronous modes when

the Enter Hunt Mode command (in WR3) is not issued between received

messa

es.

10 Reset Tx CRC Generator. Not relevant with normal SDLC/HDLC DMA

operation.This command initializes the CRC

eneratin

circuitry. A channel

reset will not initialize the CRC

enerator, so this command should be issued

after the channel has been reset and enabled.

11 Res et Tx Underrun/EOM Latch. Not relevant with normal DMA operation.This

command reset s the Tx Underrun/EOM Latch, which controls the transmission

of CRC at the end of a messa

e (EOM). If usin

DMA, this command should

not be issued. Do not issue this command durin

asynchronous operation. For

Synchronous, non-DMA operation, the reset command should be issued

immediately after the 1st byte of a new messa

e is written to the Tx Data

Buffer.

000 Null Code

001 Reserved

010 Reset External/Status Interrupts. Not relevant with normal DMA operation.

When an External/Status Interrupt is asserted, the enabled status bits in RR0

are latched. This command resets those latches and would normally be issued

by the interrupt service routine, after havin

stored an ima

e of the state of

RR0. The ima

e will be needed to determine which pins/bits have chan

since the last External/Status Interrupt was serviced.

011 Send Abort. Not relevant with normal DMA operation. This command would be

used in SDLC mode to send an abort code. The command empties the Tx

Data Buffer and sets the Tx Underrun/EOM bit in RR0.

100 Enable Interrupt on Next Rx Character. Not relevant with normal DMA

operation. In Interrupt on First Received Character Mode, this command is

used to re-enable that interrupt after each messa

e has been received.

101 Reset Tx Interrupt Pendin

. Not relevant with normal DMA operation. This

command clears the Tx Interrupt Pendin

fla

132 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

WR0[2] - For ce Sync

A zero in this bit allows the external Sync input to drive the SCC channel’s Sync inp ut

signal in the normal manner. A one in this bit forces the Sync input signal active high.

This bit is used to enable Transparent mode (see Section 5.4.6).

WR0[1] - RClk Sel ect

This bit selects the RClk signal for the SCC channel. It also controls the first layer of the

three layer selection structure for generating the BRGClk signal (the clock input to the

Baud Rate Generator, see Section 5.5.

WR0[0] - 7/8 P resc ale Enab le

This bit controls the third and final layer of the three-layer selection structure for

generating the BRGClk signal (the clock input to the Baud Rate Generator,

see Section 5.5, “Baud Rate Generator”).

110 Error Reset. Not relevant with normal DMA operation. This command clears

the error bits in RR1. If Interrupt on First Rx Character Mode, or I nterrupt on

Special Condition Mode are sel ected, and a special condition exists, the data

with the special condition is held in the Receive Data Buffer until this

command is issued. When this command is issued, the special condition data

are lost.

111 Res et Hi

hest IUS. Reserved, do not issue this command.

0 Selects RTClk inverted as the RClk si

nal.

1 Selects ComClk as the RClk si

nal (see SCC Cl ocks, Section 5.6).

0 Selects the normal (1/1) version of the incomin

clock.

1 Selects the 7/8 prescal ed version of the incomin

clock.

Chapter 5: Serial Communications Controller (SCC) 133

SCC Writ e Registers

5.8.2 Write Register 1: Transmit/Receive Interrupt Control

WR1 contains the master interrupt control bits for the SCC channel.

WR1[7:6] - Reserved, write 0

WR1[5] - MCIP En able (A sync hro nous mod e use onl y)

0 Disable DMA MCIP interrupt.

1 Enable DMA MCIP interrupt. If (and only if ) the SCC channel is in

Asynchronous mode, then when a match character has been written to

memory by the Rx DMA channel, it

enerates an MCIP Interrupt (Global DMA

Interrupt Re

ister bits [15:12]).

WARNING! Never set this bit to one except in Asynchronous mode!

Setting this bit to one in any other mode will cause system failure!

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Rx Interrupt Disable

Rx Interrupt on First Character or Special Condition

Rx Interrupt on All Characters or Special Condition

Rx Interrupt on Special Co nditions Only

Master External/Stat us Interrupt Enable

Tx Interrupt Enab le

Rx Parity is Special Condition

MCIP Enable (Asynchronous Match Character)

Reserved, write 0

134 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

WR1[4:3] - Rx Inter rupt Co ntr ol Bi ts

WR1[2] - Par it y is Sp ecial Condi tio n

When this bit is set to one, received characters with parity not matching the sense

selected in WR4 cause a Special Receive Condition. If parity is disabled in WR4[0], this

bit is ignored.

WR1[1] - Tx I nte rr upt Enabl e

If this bit is set, the transmitter requests an interrupt when the Tx Data Buffer becomes

empty. If this bit is clear, the interrupt is disabled.

WR1[0] - Master Exte rna l/S tat us Inte rr upt E nabl e

This is the master enable bit for the External/Status Interrupts. The individual enable bits

for the External/Status Interrupts are in WR15. This bit is cleared by a hardware or

channel rese t.

00 Rx Interrupt Disable. Normally, disable the SCC Rx Interrupt for SDLC/HDLC

DMA operation, because DMA stores the status byte in memory with the

Packet. Rx Interrupts normall y come from the DMA. This mode prevents the

SCC Receiver from requestin

an interrupt.

01 Rx Interrupt on First Character or Special Condition. Not relevant with normal

SDLC/HDLC DMA operation. In this mode, the receiver requests an interrupt

on the first available character, or on a special condition. Sync characters do

not cause an interrupt. Special Receive Conditions are Parity Error (if

selected), End of Frame, Framin

Error, and Rx Overrun. This mode can be

re-enabled usin

the Enable Rx Interrupt on Next Char command in WR0

(WR0[5:3] = 100b).

10 Rx Interrupt on All Charact ers or Special Condition. Not relevant with normal

SDLC/HDLC DMA operation. In this mode, the receiver requests an interrupt

on every character, or on a special condition. Two special conditions which are

latched, the Rx Overrun bit and the Parity Error bit in RR1, must be reset by

the Error Reset command in WR0 (WR0[5:3] = 110b). Charact ers with special

conditions are not held in the Rx Data Buffer as they are in other Rx Interrupt

modes.

11 Rx Interrupt on Special Conditions Only. Not relevant with normal SDLC/

HDLC DMA operation, because the Packet Status Byte reports any errors. In

this mode, the receiver interrupts only on characters with Special Receive

Conditions.

Chapter 5: Serial Communications Controller (SCC) 135

SCC Writ e Registers

5.8.3 Write Register 2: SDLC Enhancement

Write Register 2 (WR2) provides various features for use with DMA. Bits [5], [1], and

[0] should always be set to one when using SDLC/HDLC and DMA.

WR2[7] - Bac k to Back A llowed

If this bit is set to one, SDLC/HDLC Packets separated by a single flag (“Back to Back”

Packets) are allowed. If this bit is clear, a minimum of two flags are inserted between

Packets.

WR2[6] - Re s erved, writ e 0

WR2[5] - Re s erved, writ e 1

WR2[4] - Re s erved, writ e 0

WR2[3] - TxD Hi for SDLC/HDLC-NRZI

In SDLC/HDLC with NRZI and the transmitter disabled, a one in this bit pulls TxD high.

WR2[2] - Au to RTS D eact ivate

Use this bit to sy nchronize the deactivation of RTS with the SDLC frame closing flag. If

RTS is deactivated while the CRC is bein g transmitted , a one in this bit assures that the

entire closing flag is transmitted before RTS goes high. A zero in this bit allows RTS to

be negated imm ediately.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Auto Tx Flag

Auto EOM

Auto RTS Deactivate

TxD High for SDLC-NRZI

Reserved, write 0

Reserved, write 1

Back to Back Allowed

136 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

WR2[1] - Au to EOM Reset

Set this bit to one for SDLC/HDLC DMA operation. After the first byte is transmitted,

the Tx Underrun/EOM latch will be automatically reset if this bit is set to one. If this bit

is clear, resetting the Tx Underrun/EOM latch must be done manually during

transmission.

WR2[0] - Auto Tx Flag

Set this bit to one for SDLC/HDLC DMA operation. If the transmitter is in m a rk idle

state and this bit is clear, then the first byte of a new frame can not be written to th e Tx

Data Buffer (WR8) until the opening flag has been sent. If this bit is set to one, then the

opening flag will be sent automatically when the first byte arrives in WR8, from DMA.

5.8.4 Write Register 3: Receiver Control

Write Register 3 contains the control and parameter select bits for the Rx section of the

SCC channel.

WR3[7:6] - Rx Bits/Char

In asynchronous modes, unused bits are set to one in the Rx Data Buffer (RR8).

00 5 bits/character (not supported with Autobaud)

01 7 bits/character

10 6 bits/character (not supported with Autobaud)

11 8 bits/character

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receiv er Enable

Sync Char Load Inhibit

SDLC Address Search mode

Rx CRC Ena bl e

Enter Hun t m ode (co mm a nd)

Auto Enables

5 Rx Bits/Character

7 Rx Bits/Character

6 Rx Bits/Character

8 Rx Bits/Character

Chapter 5: Serial Communications Controller (SCC) 137

SCC Writ e Registers

WR3[5] - Au to Enable s

The Auto Enables bit acts as the master on/off switch for DCD and CTS handshaking. If

this bit is clear, the DCD and CTS lines simply function as inputs to the corresponding

RR0 status bits. If this bit is set to one, CTS becomes the transmitter enable and DCD

becomes the receiver enable. However, the Transmit Enable and Receive Enable bits

(WR5[3] ) and WR 3[0 ]) must be set in or der f or DC D and CTS to function in this manner.

In Local Loopback mode, the state of DCD is ignored. In both Auto Echo and Local

Loopback modes the state of CTS is ignored. If transmission is disabled by CTS during a

byte, the entire byte will still be transmitted.

WR3[4] - Ent er Hunt Mode (command)

Not needed for DMA operation. Writing a one to this bit sets the Sync/Hunt bit (RR0[4])

and forces the receiver into Hunt mode (comparison of Sync characters (Monosync/

Bisync) or Flags (SDLC/HDLC)). After a reset (except for Asynchronous mode), the

SCC automatically enters Hunt mode. When a Flag or Sync character is matched, the

Sync/Hunt bit in RR0 is cleared and an External/Status Interru pt is generated, if enabled.

Upon reception of an SDLC/HDLC Abort character, or when the receiver is disabled, the

SCC channel automatically enters Hunt mode.

This bit is a command bit onl y, and is not latched. Therefore, writing a zero to this bit has

no effect.

WR3[3] - Rx CR C Ena ble

If this bit is set to one, each byte transferred from the Receive Shift Register to the Rx

Data Buffer is included in the calculation of the CRC. If a byte is to be excluded from

CRC, this bit mus t be cleared before that byte appears in the Rx Data Bu ffer. This bit is

automatically set to one in SDLC mode, and ignored in asynchronous modes.

WR3[2] - SD LC Ad dress S ear ch m ode

This bit is valid only in SDLC mode , and ignored in all other modes. With this bit set to

one, Address Search mode is enabled. In this mode, the first 8-bit character that is not a

Flag character is assumed to be the intended station address for the Frame. The receiver

will compare the character to the contents of WR6, and if they match, character assembly

begins. All messages with addresses not m a tching the contents of WR6 will be ignored.

The address compare can be across all 8 bits (if WR3[1] = 0) or only across the 4 Most

Significant bits (if WR3[1] = 0). No Receiver interrupts will occur unless there is an

address match.

138 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

WR3[1] - Syn c C har Loa d I nhib it

All synchronous modes except SDLC: If this bit is set to on e, the receive Syn c char acter

in WR7 is compared to the byte in the Rx Shift Register, and if they match, the load to

the Rx Data Buffer is inhibited. Bytes wh ich are stripped in this manner are not included

in the CRC calculation. If the Monosync Mode 6 bit Sync option is selected, care must be

taken in writing th e proper Sync character to WR7, as the compare is still across 8 bits

(see Table 5-6).

If this bit is set to one, and the 6-bit sync option is selected, all sync characters are

stripped except for the one immediately preceding the first data byte. If the 6-bit sync

option is selected in Bisync mode, this bit is ignored.

SDLC mode: If this bit is set to one, with Address Search mode selected (WR3[2] = 1),

then only the 4 most significant bits of the station address are compared to the

corresponding bits in WR6. Thus, frames from 16 separate sources, whose addresses

have their four most significant bits in common, can be received without changing the

value in WR6. In SDLC mode, this bit is ignored if Address Search mode (WR3[2] = 0)

has not been enabled.

WR3[0] - Rec eiver Enabl e

When this bit is set to one, operation of the receiver begins. This bit should be set only

after the initialization of the receiver is complete and all receive parameters have been

programmed. When this bit is cleared, operation of the receiver is disabled. This bit is

cleared by a hardware or channel reset.

Chapter 5: Serial Communications Controller (SCC) 139

SCC Writ e Registers

5.8.5 Write Register 4: Tx and Rx Parameters and Modes

Write Register 4 contains various mode select bits for both the transmitter and receiver.

This register should be initialized before any enable command s are issued in WR1 and

WR3.

WR4[7:6] - Clock mode

00 1x Clock mode. The clock rate and the bit clock rate are the same. If External

Sync mode is selected, the (00) code specif ies that only the Sync input is

used to achieve character synchronization.

01 4x Clock mode. The clock rate is 4 times the bit clock rate. If External Sync

mode is selected, the (01) code specifies that only the Sync input is used to

achieve character synchronization.

10 8x Clock mode. The clock rate is 8 times the bit clock rate. If External Sync

mode is selected, the (10) code specifies that either the Sync input or a match

with WR7 are used to achieve character synchronization. The Sync character

can be either 6 or 8 bits in len

th as specified in WR10[0].

11 16x Clock mode. The clock rat e is 16 times the bit clock rate. If External Sync

mode is selected, the (11) code places both the receiver and transmitter into

SDLC/HDLC mode. In this case, however, the SYNC input is used to si

nal

the be

innin

and end of a frame to the receiver in lieu of the Fla

character.

The transmitter’s SDLC/HDLC operation is normal.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Parity Enable

Parity Even/ O dd

1x Clock mode

4x Clock mode

8x Clock mode

16x Clock mode

Synchronous modes enable (forces 1x Clock mode)

Async mode 1 Stop Bit per Character

Async mode 1 1/2 Stop Bits per Character

Async mode 2 Stop Bits per Character

Monosync mode

Bisync mode

SDLC mode

Extern al Sy nc mode

140 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

The code written to this bit field selects the divid er applied to the clock rate, in derivin g

the bit clock rate. In Synchronous modes (Monosync, Bisync, and SDLC/HDLC) the 1x

Clock mode is forced internally, and, unless External Sync mode has been selected

(WR4[5:4] = 11), these bits are ignored.

WR4[5:4] - Sync mode

The code written to this bit field selects a specific Synchronous operating mode for the

SCC channel. These bits are ignored unless Synchronous Modes are enabled in bits [3:2].

WR4[3:2] - Sync Enable/S top Bits

00 Monosync mode. In this mode, the receiver searches the incomin

data

stream for a character identical to that stored in WR7. The Sync character can

be either 6 bit s or 8 bits in l en

th (see Table 5-5 and Table 5-6), as determined

by the state of WR10[0]. If Sync Char Load Inhibit is selected (WR3[1]), the

Sync charact er is stripped from the data stream.

01 Bisync mode. In this mode, the receiver searches the incomin

data stream

for a character identical to the concatenation [WR7][WR6]. The Sync

character can be either 12 or 16 bits in len

th (see Table 5-5 and Table 5-6),

as determined by t he state of WR10[0]. The transmitter always uses a 16-bit

Sync character.

10 SDLC/HDLC mode. SDLC/HDLC mode requires a Fla

(01111110b) to be

stored in WR7. The SDLC Station Address is stored in WR6, and the SDLC

CRC polynomial must be selected by writin

a zero to WR5[2] .

11 E xternal Sync mode. In this mode, external lo

ic is used to si

nal character

synchronization to the SCC channel via the Sync input. If External Sync mode

is selected, the transmitter operates in Monosync mode, and either the Sync

input, or a match with WR7, or both (see bits [7:6]) can si

nal the start of a

messa

e to the receiver.

00 Synchronous Modes Enable. This code selects the Synchronous mode

specified in bits [7:4], and internally forces the 1x Clock mode.

01 1 Stop Bit per Character. This code selects Asynchrono us mode with 1 stop

bit per character .

10 1 1/2 Stop Bits per Character. This code selects Asynchronous mode with 1 1/

2 stop bits per character. This mode can not be used in conjunction with the

1x Clock mode.

11 2 Stop Bits per Character. This code selects Asynchronous mode with 2 stop

bits per character.

Chapter 5: Serial Communications Controller (SCC) 141

SCC Writ e Registers

These bits are used either to specify that a Synchronous mode is to be selected (with bits

[7:4]), or to choose the number of stop bits for Asynchronous Tx operation.

Asynchronous Rx operation always assumes 1 stop bit.

WR4[1] - Par ity E ven/Odd

A one in this bit selects even parity. A zero selects odd parity. We define even parity such

that when there are an even numb er of zeros in a char acter, the parity bit should be a zer o.

This bit is igno red if parity is disabled in bit [0].

WR4[0] - Par ity E nabl e

A one in this bit enables parity. A zero disables parity. When parity is enabled, one extra

bit is added by the transmitter and expect ed by the receiver. Except when 8 Rx bits/

character are selected, the received parity bit is passed along by the SCC as part of the

data byte. The received data are right justified in the Rx Data Buffer, with the parity bit

being the next more significant bit than the Most Significant b it of the data.

5.8.6 Write Register 5: Transmitter Control

Write Register 5 controls the operation of the Tx section of the SCC channel.

WR5[7] - Re s erved, writ e 0.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Tx CR C Enable

RTS Control

CRC Poly

Tra ns mitter En able

5 bits per Tx Character

7 bits per Tx Character

6 bits per Tx Character

8 bits per Tx Character

Send Break

Reserved, write 0

142 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

WR5[6:5] - Tx Bits/Cha r

This field determines the number of data bits/byte transferred to the Tx Data Buffer. The

bits are assume d to be right justified with the least significant bit on the right.

WR5[4] - Sen d B reak

When this bit is set to one, the TxD outpu t is forced to s end continuous zeros, starting on

the next Tx Clock, regardless of the contents of the Tx Shift Register. This function

applies even if the transmitter is disabled. When this bit is cleared to zero, transmission of

the contents of the Tx Shift Register resumes.

While in the X21 mode (Monosync and Loop mode selected), if this bit has been set and

character synchronization is achieved in the receiver, the bit is automatically cleared and

transmission begins. A hardware or channel reset clears thi s bit.

WR5[3] - Tx E nab le

Setting thi s bit to one enables the Transmitter to send data. If th is bit is clear, the TxD

output sends continuous ones unless Auto Echo or SDLC Loop mode is selected. If this

bit is cleared to zero after transmission has started, the transmission of the character is

completed. If the bit is cleared during the transmission of a CRC character, a Sync

(Monosync or Bisync) or Flag (SDLC/HDLC) character is sent instead of the CRC. This

bit is cleared by a hardware or channel reset.

WR5[2] - CR C Polynom ial

This bit is used to select the CRC polynomial to be used by the Tr ansm itter and Receiv e r.

When this bit is set to one, the CRC-16 polynomial is used. When this bit is clear, the

SDLC polynomial is used. The SDLC polynomial must be selected when operating in

SDLC mode.

00 5 bits per Tx character (not supported with Autobaud)

01 7 bits per Tx character

10 6 bits per Tx character (not supported with Autobaud)

11 8 bits per Tx character

Chapter 5: Serial Communications Controller (SCC) 143

SCC Writ e Registers

WR5[1] - RTS Contro l

This is the control bit for the RTS output signal. When the RTS Control bit is set to one,

the RTS output goes Low. When the RTS Control bit is cleared, the RTS output goes

High. In Asynchronous mode with the Auto Enables bit set to one, RTS goes High only

after the entire byte has been sent and the Tx Data Buffer is empty. In Synchronous

modes, or in Asynchronous mode with the Auto Enables bit clear, the RTS output is

controlled by the state of the RTS Control bit directly. This bit is cleared by a hardwar e or

channel rese t.

WR5[0] - Tx C RC E nab le

If Tx CRC is desired during DMA operation, set this bit and leave it set. If this bit is set

at the time when a character is loaded from the Tr ansmit Data Buffer to the Transmit

Shift Register, CRC is calculated on that character. If this bit is clear at the time, CR C is

not calculated on the character. This bit must b e set in order for CRC to be auto matically

sent upon the occurrence of Tx Underrun.

5.8.7 Write Register 6: Station Address/Sync Char Low/Async Match Char

For SDLC mode operation, Write Register 6 is programmed to hold the SDLC Station

Address field. For Monosyn c mode it h olds the tran smit Sync character. For Bisync mode

it holds the low order bits of the 2 byte Sync character. For Async Char Match mode (see

4.5.7 Asynchronous Character Match), it is one of four Match Character Registers. Bit

positions for WR 6 are shown below in Table 5- 5.

Table 5-5 Write Register 6 Bit Positions

Bit 76543210

Monosync 8 bits S ync 7Sync6Sync5Sync4Sync3Sync2Sync1Sync0

Monosync 6 bits S ync 1Sync0Sync5Sync4Sync3Sync2Sync1Sync0

Bisync 16 bits Sync7Sync6Sync5Sync4Sync3Sync2Sync1Sync0

Bisync 12 bits Sync3Sync2Sync1Sync01111

SDLC Address 8 bit A7A6A5A4A3A2A1A0

SDLC Address Ran

e 4 bit A7A6A5A4XXXX

144 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

5.8.8 Write Register 7: HDLC Flag/Sync Char High/Async Match Char

In SDLC/HDLC mode, Write Register 7 is programmed to hold the SDLC/HDLC Flag

character (01111110b). Note that the SDLC/HDLC protocol requires this Flag character,

but the SCC does not generate it automatically. Hence, the SDLC/HDLC Flag must be

written to WR7 for SDLC/HDLC mode operation. In Monosync mode, this register holds

the receive Sync character. In Bisync mode it holds the high order bits of the two byte

Sync character. Bit positions for WR7 are shown below in Table 5-6.

5.8.9 Write Register 8: Tx Data Buffer

Write Register 8 is the Transmit Data Buffer Register. A byte placed in this register will

be loaded into the Tx Shift Register, when it becomes empty, and transmitted on the TxD

line. Please note: It is recommended that all data transmission be DMA driven.

5.8.10 Write Register 9: Channel Reset /Master Interrupt Enable

Write Register 9 is a shared register between two SCC channels. There is one WR9

shared by SC C0 /S C C1, and an ot her shared by SCC2/SCC3. Write Register 9 co ntai ns t he

Master Interrupt Enable bit, and the Channel Reset Code bit field.

Table 5-6 Write Register 7 Bit Positions

Bit 76543210

Monosync 8 bits Sync7Sync6Sync5Sync4Sync3Sync2Sync1Sync0

Monosync 6 bits Sync5Sync4Sync3Sync2Sync1Sync0XX

Bisync 16 bits Syn c15 Sync14 Sync13 Sync12 Sync11 Sync10 Sync9Sync8

Bisync 12 bits Syn c11 Sync10 Sync9Sync8Sync7Sync6Sync5Sync4

SDLC Fla

01111110

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved, write 0

Master Interrup t Enable

No Reset

Reset Odd Channel (1 or 3)

Reset Even Channel (0 or 2)

Force Hardware Reset

Chapter 5: Serial Communications Controller (SCC) 145

SCC Writ e Registers

WR9[7:6] - Channel Reset C odes

The two bit code written to this bit field selects one of the SCC reset commands. An SCC

channel reset command disables that channel’s receiver and transmitter, forces TxD to

mark, sets the modem control signals high (inactive), clears all Interrupt Pending signals,

and disables all interrupts for that channel. Five extra PClk cycles are required before the

next command can be written to that SCC channel, after a channel reset command has

been issued.

WR9[5:4] - Reserved, write 0

WR9[3] - Master I nte rrupt Enabl e

The Master Interrupt Enable bit is used to globally enable or inhibit interrupts for the

relevant grouped pair of SCC channels, SCC0/SCC1 or SCC2/SCC3. When this bit is set

to one, interrupts are enabled. When the bit is clear, interrupts are disabled. No Interrupt

can be asserted by that SCC grouped pair after the Master Interrupt Enable bit is cleared.

This bit is cleared by a hardware reset.

WR9[2:0] - Reserved, write 0

00 No Reset. This command is a NOP for reset. Use this command if writin

bit [3] for other reasons than reset.

01 Reset Odd Channel (SCC1 or SCC3)

10 Reset Even Channel (SCC0 or SCC2)

11 Forc e Hardware Reset. This command has the identical effect as a hardware

reset.

146 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

5.8.11 Write Register 10: Miscellaneous Tx and Rx Control

Write Register 10 is the Miscellaneous Transmitter and Receiver Control bits register.

Use this register to choose data encoding method, Sync character length, SDLC

parameters, and CRC preset states.

WR10[7] - CRC Pr eset

This bit is used to preset the receive CRC checker and the transmit CRC generator. If this

bit is set to one, the CRC checker and generator are preset to all ones. If this bit is clear,

the CRC checker and generator are preset to all zeros. These options can both be selected

with either CRC polynomial. In SDLC mode, the generated CRC is inverted before being

transmitted, and the received CRC is compared to the bit pattern 0001 11 01 0000 1111. If

you understand this, please call (408) 991 - 3101 and explain it to Bill Kolb.

WR10[6:5] - Data Encodin g

These bits control the data encoding method used by both the transmitter and receiver. A

hardware reset forces these bits in to NRZ mode.

00 NRZ (Lo

ic hi

h = 1, lo

ic low = 0)

01 NRZI (No chan

e = 1, chan

e = 0)

10 FM1 (Bit center transition: Transition = 1, no transition = 0)

11 FM 0 (Bit center transition: No transition = 1, transition = 0)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Sync Char L eng th

Reserved, write 0

SDLC Underrun mode

SDLC Idle mode

NRZ

NRZI

FM1

FM0

Reserved, write 0

CRC Preset

Chapter 5: Serial Communications Controller (SCC) 147

SCC Writ e Registers

WR10[4] - Reserved, w r ite 0

WR10[3] - SD LC Idl e Mod e

This bit is used to control th e line co ndition in the idle state for SDLC m ode only. If this

bit is clear, the transmitter sends continuous SDLC Flags (7Eh) as the idle character. If

this bit is set to one, the transmitter sends continuous “Marks” (FFh) as the idle character.

WR10[2] - SD LC Under ru n Mod e

For normal DMA operation, this bit is a “Don’t Care,” as it is overridden by the DMA

controller. This bit is cleared by a hardware or channel reset.

This bit is used to select the action ta ken by the SCC channel’s transmitter when a Tx

Underrun occurs in SDLC/HDLC mode.

WR10[1] - Reserved, w r ite 0

WR10[0] - Syn c C haracter L ength

This bit is used to select the length of the Sync character in the various Synchronous

modes (see Table 5-5 and Table 5-6 for bit positions).

This bit is applicab le to the External Sync Modes (see Write Regi ster 4), but is ignored in

SDLC and Asynchronous modes. This bit is cleared by a hardware or channel reset.

0 On Tx Underrun, first send CRC then send Fla

(“normal endin

”).

1 On Tx Underrun, first send Abort then send Fla

0 Monosync mode: 8-bit Rx and Tx Sync characters. Bisync mode: 16-bit Rx

and Tx Sync characters.

1 Monosync mode: 6-bit Rx and Tx Sync characters. Bisync mode: 12-bit Rx

and 16-bit Tx Sync characters.

148 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

5.8.12 Write Register 11: Clock Mode Control

Write Reg ister 11 is used to co ntrol the clock multiplexer, which determines the clock

sources for the receiver and transmitter.

WR11[ 7] - Reserved, write 0

WR11[ 6:5] - Receive C lo ck

These bits determine the source of RxClk (see Figure 5-4 through Figure 5-7). A

hardware reset forces the state 01.

00 RClk si

nal is RxClk.

01 TRClk si

nal is RxClk.

10 BRGOut si

nal is RxClk.

11 BRGClk si

nal is RxClk.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RxClk is RClk Signal

RxClk is TRClk Signal

RxClk is BRGOut Signal

RxClk is BRGClk Signal

BRG Forced High

TxClk

BRGOut

SYNCout

TxClk is RClk Signal

TxClk is TRClk Signal

TxClk is BRGOut Signal

TxClk is BRGClk Signal

Reserved, write 0

Reserved

write 0

Chapter 5: Serial Communications Controller (SCC) 149

SCC Writ e Registers

WR11[ 4:3] - Transmit C lock

These bits determine the source of TxClk (see Figure 5-4 through Figure 5-7). A

hardware reset forces the state 01.

WR11[ 2] - Reserved, write 0.

WR11[ 1:0] - BRG select

These bits select the signal to appear on the BRG output line (see Figure 5-4 through

Figure 5-7).

5.8.13 Write Register 12: Baud Rate Generator TC Lower Byte

00 RClk si

nal is TxClk.

01 TRClk si

nal is TxClk.

10 BRGOut si

nal is TxClk.

11 BRGClk si

nal is TxClk.

00 BRG forced Hi

h. Use 00 if none of the other t hree si

nals are to be used.

01 TxClk to BRG output.

10 BRGOut to BRG output.

11 SyncOut to BRG output.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC0

TC1

TC2

TC3

TC4

TC5

TC6

TC7

150 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

5.8.14 Write Register 13: Baud Rate Generator TC Upper Byte

Write Register 12 holds the lower byte of the Baud Rate Generator Time Constant

(BRGTC). The upper byte is stored in Write Register 13. When the Baud Rate

Generator ’s internal downcounter reaches zero, it reloads itself from [WR13][WR12].

The Baud Rate Generator should be disabled while the contents of WR13 and WR12 are

modified.

The formulas relating the BRGClk and BRGOut frequencies to the BRGTC time constant

are:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC8

TC9

Reserved, write 0

BRGOut BRGClk

2 BRGTC 2+

()

-------------------------------------=

BRGTC BRGClk

2 BRGOut

()

----------------------------- 2–=

Chapter 5: Serial Communications Controller (SCC) 151

SCC Writ e Registers

5.8.15 Write Register 14: Miscellaneous Control Bits

Write Register 14 contains miscellaneous control bits. It controls the bit transmission

order, bit justification, Local Loopback and Auto Echo modes, and the Baud Rate

Generator Source and enable.

WR14[7] - Most Sig nif ican t Bit Fi rst

This bit controls the transmitted bit order and the expected receive b it order. Usually,

Asynchronous protocols use Least Significant Bit first, and Synchronous protocols use

Most Significant Bit first. Using this bit, the programmer can force whichever order she

pleases. See Figure 5-10 and Figure 5-11.

WR14[6] - Left Ju sti fied

For character lengths smaller than 8 bits , the data bits can be left justified or right

justified in memory. Typically, short d ata length bytes are right justified, but this b it can

be used to select either. See Figure 5-10 and Figure 5-11.

WR14[5] - Reserved, w r ite 0

0 LSbit First (typical for Asynchronous communications )

1 MSbit First (typical for Synchronous communication protocols)

0Ri

ht Justified

1 Left Justified

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BRG Enable

BRG Source Select

Reserved, write 0

Auto Echo mode

Local Loopback m ode

Reserved, write 0

Left Justified

Most Significant Bit Fi rst

152 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

WR14[4] - Local Lo opba ck mo de

This bit is used to select the Local Loopback operating mode. In Local Loopback mode,

TxD is “looped back” to RxD as well as appearing on the TxD pin. Even if Auto Enables

is selected, the DCD and CTS inputs are ignored in Local Loopback mode, but they can

still cause interrupts if enabled. This bit is cleared by a hardware or channel reset.

WR14[3] - Auto Echo mode

This bit is used to select the Auto Echo mode of operation. In Auto Echo mode, TxD is

connected to RxD and data comes in from the RxD pin. The CTS input is igno red in this

mode, and the bit is cleared by a hardware or channel reset.

WR14[2] - Reserved, w r ite 1

WR14[1] - BRG So ur ce Select

This bit controls the second layer of the three layer selection structure for generating the

BRGClk sign al, which is the clock input to the Baud Rate Generator (see Figure 5-2).

WR14[0] - BR G En able

This bit is used to enable and d isable the Baud Rate Generator. If Autobaud for this

channel is going to be used, this bit must be cleared to zero. The Autob a ud hardware will

set this bit automatically at the appropriate time.

0 Local Loopback disabled.

1 Local Loopback enabled.

0 Auto Echo disabled.

1 Auto Echo enabled.

0 Selects RClk.

1 Selects PClk.

0 Disable Baud Rate Generat or

1 Enable Baud Rat e Generator

Chapter 5: Serial Communications Controller (SCC) 153

SCC Writ e Registers

Figure 5-10 Least Significant Bit First, 6 Bits per Character

Figure 5-11 Most Significant Bit First, 6 Bits per Character

Bit 5 Bit 4 Bit 3

Tx Data

Buffer Bit 2 Bit 1 Bit 0

Right JustifiedLeft Justified

0b 0b Bit 5 Bit 4 Bit 3

Rx Data

Buffer Bit 2 Bit 1 Bit 0

Data Wire

Transmission

Sequence 0543210 etc.

Time

Bit5 Bit 4 Bit 3

Tx Data

Buffer

Rx Data

Buffer

Bit 2 Bit 1 Bit 0 xx

0b 0b

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Tx Data

Buffer

Rx Data

Buffer

Data Wire

Transmission

Sequence 5012345 etc.

Time

Tx Data

Buffer

Rx Data

Buffer

Right JustifiedLeft Justified

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0b 0b Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 x x

0b 0b

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

154 Chapter 5: Serial Communications Controller (SCC)

SCC Write Registers

5.8.16 Write Register 15: External/Status Interrupt Control

Write Reg ister 15 is the External/Status Interrupt Control register. Bits in this register

control which External/Status conditions can generate an interrupt, assuming the Master

External/Status Interrupt Enable bit (WR1[0]) is set. Only External/Status conditions

which occur after the corresponding bit has been set can generate an interrupt, even if the

condition was pending before the bit was set .

Note that most of these interrupts are coming from multi-function pins. So, if not using a

given pin for the SCC function, be sure to disable the associated interrupt.

WR15[7] - Break/ Abo rt IE ( Interrup t E nabl e)

A change in the Break/Abort status of the receiver generates an External/Status Interrupt.

This bit is set by a hardware or channel reset.

WR15[6] - Tx Under r un/EO M IE (Inte rr upt E nabl e)

A state change of the Tx Underrun/EOM latch in the transmitter generates an External/

Status Interrupt. This bit is set by a hardware or channel reset.

0 Disable

1 Enable

0 Disable

1 Enable

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved, write 1

Zero Cou nt IE

Reserved, write 1

DCD IE

Sync/Hunt IE

CTS IE

Tx Underr un/ EOM IE

Break/Abort IE

Chapter 5: Serial Communications Controller (SCC) 155

SCC Writ e Registers

WR15[5] - CTS I E ( Int er ru pt Enab le)

A change of state on the CTS input generates an External/ Statu s Interrupt. This bit is set

by a hardware or channel reset.

WR15[4] - Syn c/H unt IE (I nte rr upt Enabl e)

In Asynchronous mode, a change of state on the Sync line generates an External/Status

Interrupt. In Synchronous modes, a change of state of the Hunt bit in the receiver

generates an External/Status Interrupt. This bit is set by a hardware or channe l reset.

WR15[3] - DC D IE (I nterr upt En able )

A change of state on the DCD input generates an External/Status Interrupt. This bit is set

by a hardware or channel reset.

WR15[2] - Reserved, w r ite 1

WR15[1] - Zer o C ount I E ( In ter rupt Ena b le)

When the internal downcounter in the Baud Rate Generator reaches zero, it generates an

External/Status Interrupt. This bit is cleared to zero by a hardware or channel reset.

WR15[0] - Reserved, w r ite 1

0 Disable

1 Enable

0 Disable

1 Enable

0 Disable

1 Enable

0Disable

1 Enable

156 Chapter 5: Serial Communications Controller (SCC)

SCC R ead Re gist er s

5.8.17 Write Registers 16 and 17: As ync Match Charact ers

Write Registers 16 and 17 are used only in Asynchronous mode. They have no function

in Synchronous or SDLC modes. The associated Rx DMA channel must be operating in

8-bit mode (not to be confused with 8-bit bus width). In that case, these registers work in

parallel with WR6 and WR7 to hold the third an d fourth Asynchronous Match

Characters, if desired (see 4.5.7, “Asynchronous Character Match”). All four Match

Character Registers are active concurrently. If fewer than four Match Characters are

being searched for, the unused Match Character Register(s) must hold a copy of an active

match character.

5.9 SCC Read Re gisters

The contents of the XA-SCC Read Registers reflect the current operating status of the

SCC channels, and are continuously changing during serial communication.

Most Read Register status bits are not relevant with normal DMA data transfer. These

bits have been preserved, as part of this industry standard block, for completeness.

Detailed descriptions of the SCC Read Register Set is given below.

There are only two instances of Read Register Three (RR3) in the XA-SCC; One RR3 is shared

between SCC0/SCC1 and one RR3 is shared between SCC2/SCC3. Furthermore, Read Registers

2, 4, 5, a nd 9 do not exist.

Chapter 5: Serial Communications Controller (SCC) 157

SCC Re ad Re gisters

5.9.1 Read Register 0: Interrupt Status Bits

Read Register 0 is the status register for the Tx and Rx Data Buffers. It also contains the

status bits for the External/Status Interrupts.

RR0[7] - Break/Abort

Not usually applicable for normal DMA operation. In Asynchronous mode, this bit gets

set when a Null Character plus Framing Error (Break Sequence) is detected in the

incoming data stream. This bit is cleared when the sequence is terminated, and a null

character is left in the Rx Data Buffer. In SDLC mode, this bit is set upon detection of an

SDLC Abort and cleared at the termination of the Abort. Each time this bit changes state,

an External/Status Interrupt is generated (if the Break/Abo rt IE b it is set), even if another

External/Status Interrupt is pending.

RR0[6] - Tx Underru n/EOM

Not usuall y applicable for normal DMA operation. DMA will automa tically manage the

setting and clearing of this bit. Only the zero to one transition of this bit gen e rates an

interrupt, and the bit can only be cleared by issuing the “Reset Tx Underrun/EOM Latch”

command in WR0. The bit is set when Tx Underrun occurs, and an External/Status

Interrupt is generated if the Tx Underrun/EOM IE bit is set. This bit is set by a hardware

or channel reset, when the transmitter is disabled, or upon the issuance of a “Send Abort”

command.

This bit sh ould always remain set while in Asynchronous mode.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Rx Character Available

Zero Cou nt

Tx Buffer Empty

DCD

Sync/Hunt

CTS

Tx Underrun/EOM

Break/Abort

158 Chapter 5: Serial Communications Controller (SCC)

SCC R ead Re gist er s

RR0[5] - CTS

Not usually read during normal DMA operation. However, if Auto Enables is on

(WR3[5] = 1), then CTS will affect the flow of Tx data. If the CTS IE bit is clear, this bit

simply reflects the current (un latched) state of the CT S pin. If the CTS pin is Low, this bit

will be High, and vice versa.

If the CTS IE bit is set, this bit reflects the (latched) stat e of the CTS pin the last time any

of the enabled External/Status bits changed. Any transition of the CTS pin while no other

External/Status Interrupt is pend ing is latched by this bit and generates an External/Status

Interrupt. If another External/Status Interrupt is pending, an od d number of transitions of

the CTS pin will generate an Ex ternal/Status Interrupt, if enabled

RR0[4] - Sync/Hunt

Not applicable with normal DMA operation. Use of the Sync/Hunt bit varies slightly

depending on the mode in which the SCC channel is operating .

Both state transitions of the Sync/Hunt bit will generate an External/Status Interrupt, if

enabled. Therefore, issuing the Enter Hunt Mode command with the Sync/Hunt Interrupt

enabled will cause an immediate External/Status Interrupt.

Mode Description

Asynchronous In Asynchronous mode, this bit reflects the state of the Sync pin. When

the Sync pin is Low this bit is Hi

h, and vice versa.

External Sync In External Sync mode, a Hi

h on the Sync pin drives the Sync/Hunt bit

Low, and vice versa. Both state transitions will cause External/Status

Interrupts if the Sync/Hunt IE bit is set.

Monosync and Bisync This bit is initially set to one by issuin

the “Enter Hunt Mode” command.

The bit is cleared when character synchronization is achieved upon

detection of the Sync character(s). Both transitions cause External/Status

Interrupts if the Sync/Hunt IE bit is set. When the end of messa

e is

detected, or synchronization is lost, the processor should set the bit

ain by issuin

the “Enter Hunt Mode” command, WR3[4] = 1.

SDLC mode The Hunt mode status of the Receiver is reported via RR0[4], the Sync /

Hunt bit. A one in this bit means that the Receiver is in Hunt Mode. The

Receiver will enter Hunt mode, and the Sync/Hunt bit will be set to one,

when either: (a) an Enter Hunt Mode command is issued, (b) the

Receiver is enabled, (c) an Abort character is received, or (d) the

channel is reset. The Sync/Hunt bit

ets cleared (and an External/Status

Interrupt is

enerated if the Sync/Hunt IE bit is set) when the Receiver

leaves Hunt mode.

Chapter 5: Serial Communications Controller (SCC) 159

SCC Re ad Re gisters

RR0[3] - DCD

Not usually read by software during normal DMA operation. However, if WR3[5] (Auto

Enables) is set to one, then the DCD pin becomes the receiver enable (see Section 5.8.4).

If the DCD IE bit is set, this bit reflects th e (l at ched) state of the DCD pin the last tim e

any of the enabled External/Status bits changed. Any trans ition of the DCD pin while no

other External/Status Interrupt is pending is latched by this bit and ge nerates an External/

Status Interrupt. If another External/Status Interrupt is pending, an odd number of

transitions of the CTS pin will generate an External/Statu s Interrupt. If the DCD IE bit is

clear, this bit reflects the current (unlatched) state of the DCD pin. If t he DCD pin is Low,

this bit is High and vice versa.

RR0[2] - Tx Buffer Empty

Not relevant with normal DMA operation , as DMA automatically fills the Tx Data

Buffer. This bit is set to one when the Tx Data Buffer is empty. The bit is cleared when a

byte is loaded into the Tx Data Buffer. The bit remains clear while CRC is being

transmitted in Sync hronous or SDLC modes. This bit is set b y a hardware or channel

reset.

RR0[1] - Zero Count

If the Zero Count IE bit (RR15[1]) is set, this bit will be set to one while the downcounter

in the Baud Rate Generator remains at count zero. An External/Status Interrupt will be

generated if no other External/ Statu s Interrupt is pending. If another Extern al/Status

Interrupt is pending, no interrupt is generated until the other IP is removed. The Zero

Count condition is not latched, and if the condition does not persist beyond the removal

of the other IP, no interrupt will be generated. If the BRG is disabled (WR14[0] = 0), the

Zero Count bit will remain set if the downcounter is in the zero state. In this case, the

Zero Count bit will only be cleared if the Zero Count IE bit is cleared.

RR0[0] - Rx Character Availa ble

Not relevant with normal DMA operation . This bit is set to one when a byte is availab le

in the Rx Data Buffer. The bit is cleared after the Rx Data Buffer has been read. A

hardware or channel reset clears this bit.

160 Chapter 5: Serial Communications Controller (SCC)

SCC R ead Re gist er s

5.9.2 Read Register 1: Special Receive Condition

Read Register 1 contains the Special Receive Condition status bits and the SDLC residue

code bits.

RR1[7] - SDLC EOF

Not relevant with normal DMA operation. The SDLC EOF (End of Frame) bit is used

only in SDLC mode. A one in this bit indicates that a valid Closing Flag has been

received. The bit can be cleared by issuing the “Error Reset” command, and it is cleared

upon reception of the first character of the next frame. This bit is clear in all modes other

than SDLC.

RR1[6] - CRC/Framing Er ror

Synchronous and SDLC modes Not relevant with normal DMA operat ion, as thi s status bit is

stored in memory as part of the SDLC/HDLC Packet Status Byte

(see “Packet Status By te” on pa

e 4-76). A one in this bit

indicates a CRC Error was detected when comparin

the CRC

check value to the received CRC. This bit is not latched, thus it

is always updated upon reception of the next character. This bit

is cleared by issuin

an “Error Reset” command.

Asynchronous mode In Asynchronous mode, this bit is set to one if a framin

error

occurs. The bit is set, and not latched, for the character in which

the framin

error occurred.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All Sent

Residue Code 2

Residue Code 1

Residue Code 0

Parity Error

Rx Overrun

CRC/Framing Error

SDLC EOF

Chapter 5: Serial Communications Controller (SCC) 161

SCC Re ad Re gisters

RR1[5] - Rx Overrun

A one in this bit indicates that the Rx Data Buffer has been overwritten. The error

condition is latched and must be cleared by issuing an “Error Reset” com mand.

RR1[4] - Parity Er ror

If parity is enabled, this bit is set when a byte’s parity d oes not m atc h the parity sense

(odd/even) prog rammed. This bit is latched, so it remains set un til cleared by an “Error

Reset” command.

RR1[3:1] - Residue Co de bits 0, 1, 2

These bits are stored in memory as part of the SDLC/HDLC Packet Status Byte. The

function of thes e bits is explained in the context of DMA. See “Rx SDLC/HDLC Partial

Byte” on page 4-77.

RR1[0] - All Sent

In Asynchronous mode, this bit is set to one when the last byte has completely cleared the

Tx Shift Register. This bit is always set to one in Synchronous and SDLC modes.

5.9.3 Read Register 3: Interrupt Pending

There are only two (not four) instances of Read Register 3 in the XA-SCC. Hence, RR3

(the Interrupt Pending Register) is a shared register which contains the interrupt flags for

the relevant SCC pair. One RR3 is shared by the pair SCC0/SCC1 and the other RR3 is

shared by the pair SCC2/SCC3. Data reads from MMRs 826h and 866h access the same

physical register, while reads from MMRs 8A6h and 8E6h access the same register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Odd Channe l Ext ern al /Status IP (SCC1 or 3)

Odd Channel Tx IP (SCC1 or 3)

Odd Channel Rx IP (SCC1 or 3)

Even Ch an nel External/S tatus IP (SCC0 or 2)

Even Channel Tx IP (SCC0 or 2)

Even Chan n e l Rx IP (SCC0 or 2)

Reserved

162 Chapter 5: Serial Communications Controller (SCC)

SCC R ead Re gist er s

RR3[7] - Reserved, read as 0 or 1

RR3[6] - Reserved, read as 0 or 1

RR3[5] - Even Channel Rx IP

Not relevant with normal DMA operation .

RR3[4] - Even Channel Tx IP

Not relevant with normal DMA operation .

RR3[3] - Even Channel External/ Status IP

RR3[2] - Odd Channel Rx IP

Not relevant with normal DMA operation .

0 No Interrupt Pendin

1 Rx Interrupt Pendin

for even channel (SCC0 or SCC2). This bit is cleared by

readin

the character in the Rx Data Buff er (RR8).

0 No Interrupt Pendin

1 Tx Interrupt Pendin

for even channel (SCC0 or SCC2). This bit is cleared by

issuin

the “Reset Tx Interrupt Pendin

” command, WR0[5:3] = 101.

0 No Interrupt Pendin

1 External/Status Interrupt Pendin

for even channel (SCC0 or SCC2). This bit

is cleared by issuin

the “Reset External/Status Interrupts” command,

WR0[5:3] = 010.

0 No Interrupt Pendin

1 Rx Interrupt Pendin

for odd channel (SCC1 or SCC3). This bit is cleared by

readin

the character in the Rx Data Buff er (RR8).

Chapter 5: Serial Communications Controller (SCC) 163

SCC Re ad Re gisters

RR3[1] - Odd Channel Tx IP

Not relevant with normal DMA operation .

RR3[0] - Odd Channel Ex ternal /St atu s IP

5.9.4 Read Register 6: SDLC Byte Count Lower Byte

When the SCC channel is operating in SDLC mode, Read Register 6 contains the Least

Significant Byt e of the Byte Count. This Byte Count is stored in memory along with the

Packet during normal DMA SDLC/HDLC operation.

0 No Interrupt Pendin

1 Tx Interrupt Pendin

for odd channel (SCC1 or SCC3). This bit is cleared by

issuin

the “Reset Tx Interrupt Pendin

” command, WR0[5:3] = 101.

0 No Interrupt Pendin

1 External/Status Interrupt Pendin

for odd channel (SCC1 or SCC3). This bit is

cleared by issui n

the “Reset Ext ernal/Status Interrupts” command,

WR0[5:3] = 010.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BC0

BC1

BC2

BC3

BC4

BC5

BC6

BC7

164 Chapter 5: Serial Communications Controller (SCC)

SCC R ead Re gist er s

5.9.5 Read Register 7: SDLC Byte Count Upper Byte

When the SCC channel is operating in SDLC mode, Read Register 7 contains the Most

Significant Byt e of the Byte Count. This Byte Count is stored in memory along with the

Packet during normal DMA SDLC/HDLC operation.

5.9.6 Read Register 8: Rx Data Buffer

Not relevant with normal DMA operation. Read Register 8 is the Receive Data Buffer.

When a complete byte has been shifted from RxD into the Rx Shift Register, it is placed

in RR8. Please note: It is recommended that all serial data movement be DMA driven.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BC8

BC9

BC10

BC11

BC12

BC13

Reserved

Chapter 5: Serial Communications Controller (SCC) 165

SCC Re ad Re gisters

5.9.7 Read Register 10: Miscellaneous Status Bits

Read Register 10 contains two miscellaneous status bits and the Last Matched Code bit

field. Unused bits are always read as zero.

RR10[7:6] - Reserved, read as ze ro

RR10[5] - Read as zero

RR10[4] - Loop Sending

In SDLC Loop mode, this bit is set to one while the transmitter is actively sending on the

loop. This bit is clear at all othe r ti mes .

RR10[3:2] - Last Matched Code

This 2-bit field indicates which of the four match registers was matched last during

Asynchronous Character Match operation. The Last Matched Code is used by the

processor to determine which match register holds the character to be searched for in

memory. If more than one match register is matched simultaneously (because they

contain the same pattern), th e lower binary value will result.

00 WR6 matched last.

01 WR7 matched last.

10 WR16 matched last.

11 WR17 matched last.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Zero

On Loop

WR6

WR7

WR16

WR17

Loop Sending

Zero

Reserved, read as zero

166 Chapter 5: Serial Communications Controller (SCC)

SCC R ead Re gist er s

RR10[1] - On Loop

In SDLC Loop mode, this bit is set to one while the SCC channel is actually on-loop. If

Loop mode is selected wh ile in Monosync mode (X21 mode), this bit is set to one when

the transmitter is active. This bit is clear at all other times.

RR10[0] - Read as zero

Chapter 6: Autobaud 167

Chapter 6

Autobaud 6

Contents

6.1 Introductio n................................................................................................................................................168

6.2 Autobaud Detection...... .............................................................................................................................168

6.3 Clocks and Valid Baud Rates....................................................................................................................171

6.4 Autobaud Echo..... ............................... ..................... ................................ ...................................... ...........174

6.5 Autobaud Interrupts...................................................................................................................................174

6.6 Usin

Autobaud...... ................................ ..................... ............................... ..................... ..........................175

6.7 Autobaud Re

ister Descriptions................................................................................................................177

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

168 Chapter 6: Autobaud

Introduction

6.1 Introduction

Each of the four SCC channels has a dedicated hardware Autobaud circuit. When an

Autobaud detection sequence is successfully completed , the Auto baud circuit will

program the SCC channel’s Baud Rate Generator and configure the SCC for 7 or 8 Data

Bits, as well as Even, Odd, or No Parity. The SCC channel will then be automatically

enabled to Receive.

An SCC used with Autobaud MUST be operating in Asynchronous Mode. The Autobaud

circuits suppo rt only as ynchron ous comm unicat ions. Alt hough the S CCs can operat e with

fewer than 7 data bits, Autobaud only supports 7 or 8 data bits per character, with a

minimum of 1 s top bit.

If Autobaud is enabled for an SCC, the SCC’s Baud Rate Generator and Asynchronous

mode control registers must not be modified. If it is necessary to modify these registers

during Autobaud operation, Autobaud must firs t be disabled.

In order for an Autobaud circuit to transmit on TxD of the associated multifunction pin,

the pin must have been properly pr ogrammed to output the TxD signal. See Chapter 11,

“XA-SCC Pins,” for details.

The detai le d o perati on of Autobaud detectio n i s cov ered in Sections 6.2 t hro ug h 6.5. SCC

configuration for use with Autobaud is covered in Section 6.6.

6.2 Autobaud Detection

When enabled using ABDiE = 1 (for i = 0 - 3), the Autobaud detection circuit monitors

the incoming asynchronous data stream on RxD for a start bit. If the duration of the start

bit corresponds to the bit-time for a legal ba ud rate (see Section 6.3), then the Autoba ud

circuit begins to search for any of the following character sequences:

• “at” = 61h 74h → Enables SCC reception at new baud rate.

• “AT” = 41h 54h → Enables SCC reception at new baud rate.

• “a/” = 61h 2Fh → Enables SCC reception using previous settings.

• “A/” = 41h 2Fh → Enables SCC reception using previous settings.

If the sequence “at” or “AT” is identified, Autobaud detection is complete, and the SCC’s

baud rate, parity, and data bits/character are reprogrammed. Then, the SCC is enabled for

Receive, the ABDiF interrupt flag is set to one, and the ABDiE enable bit is cleared to

zero.

If the sequence “a/” or “A/” is identified, then the SCC’s baud rate, parity, and data bits/

character do not get updated . Th e SCC is enab led f or Receive using the previous settings,

the ABDiF interrupt flag is set to one, and the ABDiE enable bit is cleared to zero.

Chapter 6: Autobaud 169

Autobaud Detection

Received characters are echoed, or not, depending on the state of the AEEi bit, as

described in Section 6.4. The step-by-step process of Autobaud detection is explained

below, and depicted graphically in the Autobaud Detection State Diagram, Figure 6-1.

• The mark state between characters on the RxD input pin is logic ‘1’.

• The autobaud de tection circuit monitors the RxD input for a start bit, logic ‘0’.

• When a start bit is detected, its duration is measured.

• If the duration of the start b it corresponds to one bit-time (with some to lerance for

error) for one of the eighteen supported baud rates, then the subsequent bits are

sampled using the new baud rate and compared to the bit patterns for “a” and “A”.

• If an “a” or “A” is successfully detected (with either 7 or 8 data bits, and even, odd, or

no parity) and Autobaud Echo is enabled, then the “a” or “A” character is echoed onto

the TxD output pin using the new baud rate, number of data bits, and parity. In any

case, the autobaud detection circuit begins to monitor RxD for the next start bit.

• If the next character is “/”, it is echoed onto the TxD pin (if Autobaud Echo is enabled)

but the SCC’s baud rate, number of data bits, and parity are not reconfigured. The

SCC is enabled for Receive, the Autobaud detection flag (ABDiF) is set, and

Autobaud is terminated (ABDiE cleared to zero). If the two-character sequence was

“at” or “AT”, the “t” or “T” is echoed (if Autobaud Echo is enabled), and the SCC’s

baud rate, number of data bits, and parity are reconfigured. The SCC is enabled for

Receive, the Autobaud detection flag (ABDiF) is set, and Autobaud is terminated

(ABDiE cleared to zero).

• Successions of “a” and/or “A” are echoed on the TxD pin (if Autobaud Echo is

enabled) until either “at”, “AT”, “a/”, or “A/” is encountered.

170 Chapter 6: Autobaud

Autobaud Detection

Figure 6-1 Autobaud Detection State Diagram

Detect Start Bit?

Yes

Go to OFF

Yes

Echo Character if Enabled

Echo "/" if Enabled

Wait 8 Bit Times

ADBE = 1

Receive Next Character

Echo "T" or "t" if Enabled

Set ABDF Bit

Clear ABDE to 0

Reconfigure SCC baud rate,

data bits, parity, and turn ON

Rx Enable

Start Bit within a

legal window?

Next Character =

"A" or "a"?

Is it "/"?

Last 2 Characters =

"AT" or "at"?

1st Character =

"a" or "A"?

Do not reconfigure

SCC, but turn ON

Rx Enable

OFF

Chapter 6: Autobaud 171

Clock s and Valid Baud Ra tes

6.3 Clocks and Valid Baud Rates

6.3.1 Autobaud Source Clock

As shown in Chapter 5, there are sever al clock sou rce options available fo r the SCC Baud

Rate Generators. However , the clock source for all f our Autobaud circuits is always PClk,

which is CClk / 2. Therefore, any SCC which will be used with Autobaud must be

configured so that its Baud Rate Generator is clocked by PClk, without the 7 /8 prescaler.

See Sectio n 5 .5 "B aud Rat e Gener ator" for details. In ord er fo r both the Autobaud and t he

Baud Rate Generator circuit s to function as intended, it is recommended that CC lk =

29.4912 MHz., yielding PClk = 14.7456 MHz.

6.3.2 Valid Baud Rates

All baud rate measurement is relative to CClk, the system clock. The hi ghest baud rate

supported by Autobaud is 1/32 of the frequency of CClk. In other words,

There are 18 valid baud rates for Aut oba ud detection, which satisfy the relation

, where for

Clearly, scaling the frequenc y of the system clock will scale the values of the valid baud

rates by the same factor. In this manner, uncommon baud rates can be detected through

careful selection of the system clock frequency. The 18 valid baud rates, assuming CClk

= 29.4912 MHz., are listed in Table 6-1.

Max Baud Rate CClk

------------=

Baud RateMCClk

32M

------------= M2i or 3 2

()

i08–=

172 Chapter 6: Autobaud

Clocks and Valid Baud Rates

Table 6-1 Baud Rate

with CClk = 29.4912 MHz

Baud Rate

(CClk =29.4912 MHz)

1 921,600 bps

2 460,800 bps

3 307,200 bps

4 230,400 bps

6 153,600 bps

8 115,200 bps

12 76,800 bps

16 57,600 bps

24 38,400 bps

32 28,800 bps

48 19,200 bps

64 14,400 bps

96 9,600 bps

128 7,200 bps

192 4,800 bps

256 3,600 bps

384 2,400 bps

768 1,200 bps

Chapter 6: Autobaud 173

Clock s and Valid Baud Ra tes

6.3.3 Acceptable Baud Rate Error Margins

When the edge transitions in the received bit stream occur within a predefined window,

the baud rate is deemed valid. The width of the window, in number of CClk cycles, for a

given value of M can be found in Table 6-2. Any baud rate within this window will be

detected, and will be identified as the baud rate, Baud RateM.

Table 6-2 Baud Rate

Error Windows in Number of CClk Cycles

Window Width

(in CClks)

114

224

332

440

664

886

12 130

16 174

24 260

32 350

48 524

64 702

96 1098

128 1356

192 2098

256 2814

384 4914

768 9832

174 Chapter 6: Autobaud

Autobaud Echo

6.4 Autobau d Ec ho

The XA-SCC Autobaud circuits each have an optional Autobaud Echo feature, which is

enable d or disab l ed using the AEE (Autob aud Echo Enable) bit in the BDAEE Register.

When Autobaud Echo is enabled, all “legal” character sequences detected by the

Autobaud circuit will b e echoed (i.e., retransmitted) on the TxD output pin of the

associated SCC.

“Legal” character sequences begin with either “a” or “A”. After detecting and echoing

“a” or “A”, the autobaud circuits will echo subsequent strings of “a” and/or “A”. “T” will

be echoed only if it directly follows “A”. Likewise, “t” will be echoed only if it directly

follows “a”. The character “/” will be echoed if it directly follows either “A” or “a”.

In order for an Autobaud circuit to transmit on TxD of the associated SCC, the relevant

multifunction p in (and Pin Mux Control Register bit, if applicable) must have b een

properly programmed to output the SCC’s TxD signal. See Chapter 11, “XA-SCC Pins,”

for details. The behavior of Autobaud Echo can be seen in Figure 6-1.

6.5 Autobaud Interrupts

Each Autobaud circuit has one interrupt. ABD3F - ABD0F are the interrupt flags for

Autobaud 3 thro ugh Autobaud 0, and they reside in bits[7:4] of the BDCS Register

(MMR 272h). Autobaud detection interrupt flags are set only if Autobaud for that SCC is

enabled, and the two most recent characters were either “at”, “AT”, “a/”, or “A/”.

Furthermore, if Autob aud Echo is enabled, the interrupt flag will n ot be set until the echo

transmission of the last control character is complete. Autobaud detection interrupt flags

are cleared by writing ‘1’ to the flag’s bit pos ition. Writing ‘0’ to an ABDF flag’s bit

position is a NOP.

The four Autobaud interrupts are combined in a multiple OR configuratio n with the four

V.54/2047 interrupts and appear to the XA as the Event Interrupt “Autobaud and V.54/

2047.” This interrupt is en abled by setting the EAuto bit in SFR 427[2]. The Enable All

(EA = SFR 426[7]) bit must also be set to globally enable all Event Interrupt s. The

relevant bits for Autobaud interrupts are summarized in the table below.

Autobaud Interrupt Flag

Bits Event Interrup t

Source

Interrupt

Vector

Address

(hex) Enab le

Bit (SFR)

Priority

Fiel d (S FR )

Global

Event

Interrupt

Enable

(SFR)

ABD3F (MMR 272[7])

ABD2F (MMR 272[6])

ABD1F (MMR 272[5])

ABD0F (MMR 272[4])

“AutoBaud and

V.54/2047” 00A8-00AB EAuto

427[2]

33A

PAutoB

4A5[2:0] EA

426[7]

337

Chapter 6: Autobaud 175

Using A utobaud

6.6 Using A utobaud

The following should be configured before enabling Autobaud for an SCC:

• The Write Register set of the SCC should be configured as shown in Table 6-3.

• DMA should already be configured and enabled. If Autobaud Echo is enabled, the

Autobaud circu it’s ABDF interrupt flag does not get set until the echo transmission of

the final control character is complete. However, the Rx Enable bit in the SCC is set

immediately upon recognition of the valid sequence. If a character arrives during the

time when the final echo character is being sent, it should be stored in memory by

DMA.

• Since Autobaud only works with 7 or 8 data bits/character, WR3[6] must be set to ‘1’.

Only WR3[7], not WR3[6], will be updated by Autobaud.

In general, the use of Autobaud for a given SCC proceeds as follows:

Set up SCC for Asynchronous mode, do

not enable.

Enable Autobaud (and Autobaud Echo,

if desired).

Autobaud detects valid sequence.

Autobaud programs SCC Baud Rate.

Autobaud programs SCC Parity.

Autobaud programs SCC Rx Bits/Char.

Autobaud turns on SCC Rx Enable.

Echo (if enabled) of final control charac-

ter is completed.

Autobaud sets its interrupt flag bit, and

disables itself.

176 Chapter 6: Autobaud

Using A utobaud

6.6.1 SCC Write Register Configuration f o r Autobaud

Table 6-3 illustrates the recommended configuration of an SCC’s Write Registers before

enabling Autoba ud for that SCC. The letter “P” in a bit position means the value of the

bit is option al, being at the discretion of the Programmer. The letter “L” in a bit position

means this value sh ould be Left as-is, Autobaud might or might n ot update this bit when

detection is complete, depending on which control sequence was received. The letter “x”

in a bit position mean s the value is a “don ’t care.” Write Reg ister bits which can be

updated by the Autobaud circuitry are shown in bold type.

WR3[6] must be set to ‘1’ prior to enabling Autobaud. Also, WR3[0] and WR14[0]

must be cleared to ‘0’ before enabling Autobaud. The Autobaud hardware will turn on

the SCC’s Rx Enable (WR3[0]) and BRGEnable (WR14[0]) at the appropriate time,

when detection is complete.

Table 6-3 Recommended SCC Write Register Va lues for Use with Autobaud

Write Register 7 65 43210

WR0 00000000

WR1 00PPPPPP

WR2 0010xPxx

WR3 L1P00000

WR4 LL0001LL

WR5 0 P P 0 P 0 P 0

WR6 ← P→

WR7 ← P→

WR8 ← P→

WR9 0000P000

WR10 x 0 0 0 x x 0 x

WR11 010100PP

WR12 ← L→

WR13 0 0 0 0 0 0 LL

WR14 P P 0 0 0 0 1 0

WR15 P0P0P101

WR16 PPPPPPPP

WR17 PPPPPPPP

Chapter 6: Autobaud 177

Autob aud Re gister D escript ions

6.7 Autobaud Register Descriptions

There are two control registers in Memory Mapped Register space which are shared by

the four Autobaud circuits. These registers are described below.

6.7.1 BDAEE: Autoba ud Echo Enable

BDAEE[7:4] - Reserved, writ e ‘ 0’.

BDAEE[3:0] - AEE3 throu gh AEE0 (Autob aud Echo Enabl e for SCC3 - SC C0)

If the Autobaud Echo Enable bit is set, Autobaud will echo the “legal” characters o n the

TxD output pin of the associated SCC. If the bit is clear, Autobaud Echo is disabled. See

Section 6.4 and Figure 6-1. Als o see the logic diagrams for Pin 96: Tx D0 _L1TxD, Pin 66 :

P3.6_TxD1, Pin 69: P1.1_TxD2, and Pin 81: P2.1_TxD3 in Chapter 11, “XA-SCC Pins.”

6.7.2 BDCS: Autobaud Control and Status

BDCS[7:4] - ABD3F th ro ugh AB D0 F ( Au toba ud D et ecti on Flag fo r S CC3 - S CC 0)

The Autobaud De tection Flag is the interrupt flag for the Autob a ud circuit. The bit is set

to one when Autobaud detection is completed successfully. Writing a ‘1’ to the flag’s bit

position clears the flag bit to zero. The setting of an ABDiF flag bit will cause a processor

interrupt, if enabled.

BDCS[3:0] - ABD3E t hr ough ABD 0E (Auto baud En able for S CC3 - S CC0)

This is the enable bit for the Autobaud circ uit. When this bit is written with ‘1’, Autobaud

detection begins for the associated serial channel. When Autobaud detection is complete,

the Autobaud hard ware turns itself off by clearing this bit to ‘0’. The processor can also

clear the bit by writing ‘0’ to the bit’s position.

76543210

0 0 0 0 AEE3 AEE2 AEE1 AEE0

76543210

ABD3F ABD2F ABD1F ABD0F ABD3E ABD2E ABD1E ABD0E

178 Chapter 6: Autobaud

Autobaud Register Descriptions

Chapter 7: V.54/2047 Units 179

Chapter 7

V.54/2047 Units 7

Contents

7.1 Introductio n................................................................................................................................................180

7.2 Assi

nin

V.54/2047 Units. ....................................................................................................................... 180

7.3 V.54 and 2047 Receive.............................................................................................................................185

7.4 V.54 and 2047 Generate...........................................................................................................................187

7.5 V.54/2047 Interrupts..................................................................................................................................187

7.6 V.54/2047 Re

ister Descriptions..... ..................... ................................ ..................... ................................189

7.7 V.54 and 2047 Circuits..............................................................................................................................193

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

180 Chapter 7: V.54/2047 Units

Introduction

7.1 Introduction

The XA-SCC supports both the V.54 and 2047 line testing protocols. The two on-chip

V.54/2047 units, A and B, operate independently. Unit A can be assigned to SCC0 or

SCC2, and unit B can be assigned to SCC1 or SCC3. Each unit contains both a V.54 and

2047 generator and receiver.

Each unit’s generator and receiver can be independently enabled and disabled, but both

generator and receiver are assigned to either V.54 or 2047 mode together. The V.54/2047

units should be assigned only to an SCC, operates in one of the sy nchronous modes,

using N RZ data en coding.

7.2 Assigning V.54/2047 Units

V.54 and 2047 operation begins by assigning the relevant unit to an SCC. Unit A can be

assigned to SCC0 or SCC2, and unit B can be assigned to SCC1 or SCC3. The

assignment is made using the VxSCC bit (where x = A o r B) in the unit’s VxCS Register

(VxSCC = VxCS[6]).

When a V.54/2047 unit is assigned to an SCC, it automatically receives, for its input, the

same signal which appears on that SCC’s RxD in put (with or without IDL). This is

illustrated graphically by the pin diagrams for Pins 97, 65, 68, and 80. See Chapter 11,

“XA-SCC Pins.”

In order for a V.54/2047 unit to transmit, several control bits in various MMRs must be

configured before the unit’s gen e rator output will appear on the desired TxD outpu t pin.

The configuration procedures for these control bits are presented in the next two sections.

7.2.1 Assigning V.54/2047 Unit A

Assigning Unit A to SCC0

If unit A is assigned to SCC0, then Autobaud 0 and Pin 96 must be configured

appropriately. The logic diagram for Pin 96 is reprinted below as Figure 7-1, to

accompany this discussion.

• Assign unit A to SCC0 by clearing the VASCC bit to zero.

• Disable Autobaud 0 by writing ‘0’ to the Autobaud 0 enable bit, ABD0E.

• Enable the unit A generator by writing ’1’ to the unit A generator enable b it, VAGE.

• Since Pin 96 is an output-only pin, no Pin 96 programming is required.

•If IDL is off, V.54/2047 unit A’s generator outpu t (V54 T xD0) will appear as TxD0 on

Pin 96. If IDL is on, unit A’s g e nerator output will be time multiplexed by the IDL

Interface using the bit time slots assigned to SCC0.

Chapter 7: V.54/2047 Units 181

Assig ning V.5 4/2047 Units

Unit A Assigned to SCC2

If unit A is assigned to SCC2, then AutoBaud 2 and Pin 69 must be configured

appropriately. The logic diagram for Pin 69 is reprinted below as Figure 7-2, to

accompany this discussion.

• Assign unit A to SCC2 by setting the VASCC bit to 1.

• Disable Autobaud 2 by writing ‘0’ to the Autobaud 2 enable bit, ABD2E.

• Enable the unit A generator by writing ’1’ to the unit A generator enable b it, VAGE.

• If SCC2 is not connected to IDL, then Pin 69 must be programmed so that TD2

appears as TxD2 on the pin, as follows:

– Allow TD2 to pass through the Pin Mux bl ock by writing Pin Mux Co ntrol[5] = 1

(this in conjunction with SC2isIDL = 0 all ow s TD2 to pass).

– Configure Pin 69 as an output by writing P1CFGB[1] = 1, and P1CFGA[1] = 1.

– Allow TD2 to reach the pin by writing P1[1] = 1.

• If SCC2 is connected to IDL, then unit A’s generator output will be time multiplexed

by the IDL Interface using the bit time slots assigned to SCC2.

The configuration bits for assigning V.54/2047 unit A are summarized in Table 7-1.

Table 7-1 V.54/2047 Unit A Assignment Bits

For Unit A to

Transmit on VBSCC VBGE Autobaud 0 Enable

(ABD0E) Autobaud 2 Enable

(ABD2E)

TxD0 0 1 0 Autobaud 2 and

SCC2 are free to use

TxD2.

TxD2 1 1 Autobaud 0 and SCC0 are

free to use TxD0. 0

Generator Disabled Don’t care 0 Autobaud 0 and SCC0 are

free to use TxD0. Autobaud 2 and

SCC2 are free to use

TxD2.

182 Chapter 7: V.54/2047 Units

Assigning V.54/2047 Units

Figure 7-1 Logic for Pin 96

Figure 7-2 Logic for Pin 69

TD0

TD1

L1TxD

TriStEn

D0Out

TD2

TxD0_L1TxD

PIN 96

Border of

XA-SCC Chip

PAD LOGIC

IDL

Logic

IDLOn*

*MSI Control[2:0] ≠111 is IDLOn

SCC0

V.54/2047 Unit A

(for SCC0 & 2)

Autobaud 0

V54TxD0

Generator Enabled

to SCC0

TxD0

ABD0E

AbdTxD0

IDL

To P1[1] DataIn

P1[1] Output Latch

D2Out TD2

P1.1_TxD2

PIN 69

P1CFGB[1]

P1CFGA[1]

Border of

XA-SCC Chip

PAD LOGIC

To IDL

SC2isIDL*

PMCR[5]

1SCC2

V.54/2047 Unit A

(for SCC0 & 2)

Autobaud 2

V54TxD2

Generator Enabled

to SCC2

TxD2

ABD2E

AbdTxD2

*If SC2isIDL = 1, then

D2Out = 1, allowing

GPI/O P1[1] to use

Pin 69 as an output.

Chapter 7: V.54/2047 Units 183

Assig ning V.5 4/2047 Units

7.2.2 Assigning V.54/2047 Unit B

Unit B Assigned to SCC1

If unit B is assigned to SCC1, then AutoBaud 1 and Pin 66 must be configured

appropriately. The logic diagram for Pin 66 is reprinted below as Figure 7-3, to

accompany this discussion.

• Assign unit B to SCC1 by clearing the VB SCC bit to 0.

• Disable Autobaud 1 by writing ‘0’ to the Autobaud 1 enable bit, ABD1E.

• Enable the unit B generator by writing ’1’ to the unit B generator enable bi t, VBGE.

• If SCC1 is not connected to IDL, then Pin 66 must be programmed so that TD1

appears as TxD1 on the pin, as follows:

– Allow TD1 to pass through the Pin Mux bl ock by writing Pin Mux Co ntrol[4] = 1

(this in conjunction with SC1isIDL = 0 all ow s TD1 to pass).

– Configure Pin 66 as an output by writing P3CFGB[6] = 1, and P3CFGA[6] = 1.

– Allow TD1 to reach the pin by writing P3[6] = 1.

• If SCC1 is connected to IDL, then unit B’s generat or output will be time multiplexed

by the IDL Interface using the bit time slots assigned to SCC1.

Unit B Assigned to SCC3

If unit B is assigned to SCC3, then AutoBaud 3 and Pin 81 must be configured

appropriately. The logic diagram for Pin 81 is reprinted below as Figure 7-4, to

accompany this discussion.

• Assign unit B to SCC3 by setting the VBSCC bit to 1.

• Disable Autobaud 3 by writing ‘0’ to the Autobaud 3 enable bit, ABD3E.

• Enable the unit B generator by writing ’1’ to the unit B generator enable bi t, VBGE.

• Pin 81 must be programmed so that TD3 appears as TxD3 on the pin, as follows:

– Configure Pin 81 as an output by writing P2CFGB[1] = 1, and P2CFGA[1] = 1.

– Allow TD3 to reach the pin by writing P2[1] = 1.

184 Chapter 7: V.54/2047 Units

Assigning V.54/2047 Units

The configuration bits for assigning V.54/2047 unit B are summarized in Table 7-2.

Figure 7-3 Logic for Pin 66

Table 7-2 V.54/2047 Unit B Assignment Bits

For Unit B to

Transmit on VBSCC VBGE AutoBaud 1 Enable

(ABD1E) AutoBaud 3 Enable (ABD3E)

TxD1 0 1 0 AutoBaud 3 and SCC3 are free

to use TxD3.

TxD3 1 1 AutoBaud 1 and SCC1

are free to use TxD1. 0

Generator

Disabled Don’t care 0 AutoBaud 1 and SCC1

are free to use TxD1. AutoBaud 3 and SCC3 are free

to use TxD3.

To P3[6] DataIn

P3[6] Output Latch

D1Out TD1

P3.6_TxD1

PIN 66

P3CFGB[6]

P3CFGA[6]

Border of

XA-SCC Chip

PAD LOGIC

To IDL

SC1isIDL*

*If SC1isIDL = 1, then

D1Out = 1, allowing

GPI/O P3[6] to use

Pin 66 as an output.

PMCR[4]

SCC1

V.54/2047 Unit B

(for SCC1 & 3)

Autobaud 1

V54TxD1

Generator Enabled

to SCC1

TxD1

ABD1E

AbdTxD1

Chapter 7: V.54/2047 Units 185

V.54 and 2047 Receive

Figure 7-4 Logic for Pin 81

7.3 V.54 and 204 7 Rece ive

A V.54 generator can produce two unique patterns, Scramb le Zeros and Scramble Ones.

Only if the correct receiver pattern (Unscramble Zeros or Unscramble Ones) is selected,

will the V.54 receiver properly d ecode the incoming bit stream. When the receiver detects

a bit which deviates from the pattern (“er ror bit”), it subtracts a preset value (the Receiver

Error Weight) from a counter (the Receiver Threshold Counter). When a bit that matches

the pattern (“good bit”) is detected, the counter is incremented (by one). When the

counter coun ts up to a p reset threshold value (the R eceiver Thresho l d), an inter rup t flag is

set.

Before reception can take place, the V.54/2047 unit must be assigned to an SCC channel

using VxCS[6] (VxSCC), as described in Section 7.2. Upon reset, or when the receiver

was disabled using VxCS[2] = VxRE = 0, the Receiver Threshold C o unter and the

Receiver Erro r C oun ter ( which is on ly u sed in 2047 mode) were cleared to zero . Th e V.54

receive process and the 2047 receive process are outlined below.

To P2[1] DataIn

P2[1] Output Latch TD3

P2.1_TxD3

PIN 81

P2CFGB[1]

P2CFGA[1]

Border of

XA-SCC Chip

PAD LOGIC

1SCC3

V.54/2047 Unit B

(for SCC1 & 3)

Autobaud 3

V54TxD3

Generator Enabled

to SCC3

TxD3

ABD3E

AbdTxD3

186 Chapter 7: V.54/2047 Units

V.54 and 2047 Receive

7.3.1 V.54 Receive

• V.54 mode is selected using VxCS[7] = VxSEL = 0.

• The Receiver Error Weight is written to the three-bit field VxCFG[2:0]

(VxWT2-VxWT0). The actual weighting factor is the binary value plus one.

• The Receiver Threshold is written to the five-bit field VxCFG[7:3] (VxT11-VxT7).

• The Unscramble Ones Receiver Pattern is selected using VxCS[1] = VxRP = 1.

• The receiver is enabled using VxCS[2] = VxRE = 1.

• Each data bit received by the assigned SCC channel is shifted into the V.54/2047 unit’s

receive shift register, and the “good bit/error bit” determination is made (see

Figure 7-6).

• If it is a good bit, the Receiver Threshold Counter is incremented by one.

• If it is an error bit, the Receiver Threshold Counter is decremented by the Receiver

Error Weight (VxCFG[2:0] - 1), but the counter will not decrement below zero.

• When the Receiver Threshold is reached (VxTC11-VxTC7 = VxT11-VxT7), the

VxDFG flag bit gets set, generating a processor interrupt if enabled. For details on the

interrupt, see Sectio n 7.5.

• The V.54/2047 software normally replies by having this unit generate Scramble Ones.

7.3.2 2047 Receive

• 2047 mode is selected using VxCS[7] = VxSEL = 1.

• The Receiver Pattern select bit must be VxCS[1] = VxRP = 0 for 2047 mode

operation.

• The receiver is enabled using VxCS[2] = VxRE = 1.

• Each data bit received by the assigned SCC channel is shifted into the V.54/2047 unit’s

receive shift register and the “good bit/error bit” determination is made (see

Figure 7-8).

• Each bit (good or erroneous) increments the 12-bit Receiver Threshold Counter by

one. Every 4096th bit, when the counter rolls over from 4095 to 0, the VxDFG flag

gets set, generating a processor interrupt if enabled. For details on the in terru pt , see

Section 7.5.

• Each erroneous bit increments the 8-bit Receiver Error Counter by one. Every 256th

error bit, when the counter rolls over from 255 to 0, the VxVFG flag get s set,

generating a process or interrupt if enabled. For details on the interrupt, see Section 7.5.

Chapter 7: V.54/2047 Units 187

V.54 and 2047 Generate

7.4 V.54 and 2047 Generate

Before generation can take place, the V.54/2047 unit must be assigned to an SCC channel

using VxCS[6] (VxSCC), as described in Section 7.2. Upon reset, or when the generator

was disabled using VxCS[5] = VxGE = 0, the pattern generator was initi alized with its

starti ng v al ue (1 010 101 for the V.54 generator, and 101 01010101 for the 204 7 gen erat or ) .

The V.54 generate process and the 2047 generate process are outlined below.

7.4.1 V.54 Generate

• V.54 mode is selected using VxCS[7] = VxSEL = 0.

• The generator pattern must first be selected using VxCS[4] (VxGP). VxGP = 1 selects

Scramble Ones, and VxGP = 0 selects Scramble Zeros.

• The generator is enabled using VxCS[5] = VxG E = 1.

• One bit is outp ut from the generator for every data bit required by the assigned SCC

transmit channel (see Figure 7-5).

7.4.2 2047 Generate

• The Generator Pattern select bit must be VxCS[4] = VxGP = 0 for 2047 mode

operation.

• The generator is enabled using VxCS[5] = VxG E = 1.

• One bit is outp ut from the generator for every data bit required by the assigned SCC

transmit channel (see Figure 7-7).

7.5 V.54/2047 Interrupts

Each V.54/2047 unit has two interrupts: VxVFG (VxCS[3]) and VxDFG (VxCS[0]).

VxVFG is active only in 2047 mode, and gets set when the unit’s 8- bit Error Counter

overflows. VxDFG is active in both V.54 and 2047 modes but behaves differently in

each. In V.54 mode, VxDFG gets set when the Receiver Threshold is detected

(VxTC11-VxTC7 = VxT11-VxT7). In 2047 mode, VxDFG gets set when the 12-bit

Receiver Threshold Counter (which is a pure bit counter in 2047 mode) overflows every

4096 bits. Both interrupt flags are cleared by writing ‘1’ to the flag’s bit position.

188 Chapter 7: V.54/2047 Units

V.54/2047 Interrupts

Tabl e 7-3 s umm a rizes the conditions which can gene rate an interrupt in V. 54 and 2047

modes.

The four V.54/2047 in terrupts are combined in a mu ltip le OR co nfiguration with the four

Autobaud interrup ts, an d appear to the XA Interrupt Controller as the Event Interrupt

“AutoBaud and V.54/2047.” This interrupt is enabled by setting the EAuto bit in SFR

427[2]. The Enable All (EA = SFR 426[7]) bit must also be set to globally enable all

Event Interrupts. The relevant bits for V.54/2047 interrup ts are summarized in the table

below.

Table 7-3 V.54 and 2047 Interrupt Conditions

Mode Threshold Coun ter (12-b it) Error Count er ( 8 -b it )

Operation Interrupt Operation Interrupt

V.54 Add one every correct

bit. Subtract wei

every error bit.

Threshold

detected. Held at zero. none

2047 Add one every bit. At rollover. Add one

every bit. At rollover.

V.54/2047 Interrupt

Flag Bits

Event

Interrupt

Source

Interrupt

Vector

Address

(hex) Enable Bit

(SFR)

Priority

Fiel d (S FR )

Global

Event

Interrupt

Enable

(SFR)

VBVFG (MMR 248[3])

VBDFG (MMR 248[0])

VAVFG (MMR 240[3] )

VA DFG (MMR 240[0])

“AutoBaud

and V.54/

2047”

00A8-00AB EAuto

427[2]

33A

PAutoB

4A5[2:0] EA

426[7]

337

Chapter 7: V.54/2047 Units 189

V.54/2047 Register Descriptions

7.6 V.54/2047 R egister Descriptions

Each V.54/2047 unit, A and B, has five associated Memory Mapped Registers. The

deta iled function of these registers for V.54/2047 unit x (where x = A or B) is de scribed

in this section.

7.6.1 VxCS: Unit x Control and Status Register

This register contains the mode select, control, and interrupt flag bits for V.54/2047

unit x.

VxCS[7] - VxSEL (V.54 or 2047 Se lect )

VxCS[6] - VxSCC (SCC Select)

The value of this bit determines which SCC channel the V.54/2047 unit is connected to .

0 Selects V.54 operation.

1Selects 2047 operation.

0 For unit A: Connected to SCC0. For unit B: Connected to SCC1.

1For unit A: Connected to SCC2. For unit B: Connected to SCC3.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

VxDFG

VxRP

VxRE

VxVFG

VxGP

VxGE

VxSCC

VxSEL

190 Chapter 7: V.54/2047 Units

V.54/2047 Register Descriptions

VxCS[5] - VxGE (Gen erator Enabl e)

VxCS[4] - VxGP (Gen erator Patt ern)

This bit selects the Scramble Zeros or Scramble Ones generator pattern in V.54 mode (see

Section 7.3). This bit must be cleared to zero for 2047 mode operation.

VxCS[3] - VxVFG ( Receiver Error Coun ter Overfl ow Fla g)

The 2047 mode Receiver Error Counter Overflow Interrupt Flag is set by hard ware and

cleared by software. It is only active in 2047 mode. When the 8 bit Receiver Error

Counter overflows (increments from 255 to 0), this bit gets set to one, generating an

interrupt if enabled. The interrupt is removed, and the bit is cleared, by writing ‘1’ to this

bit position.

VxCS[2] - VxRE (R eceiver Enable)

VxCS[1] - VxRP (R eceiver Pattern)

This bit selects the Scramble Zeros or Scramble Ones receiver pattern in V.54 mode. This

bit must be cleared to zero for 2047 mode operation.

0Generator disabled, and startin

bit pattern loaded (by hardware) into

enerator shift re

ister.

1Generator enabled. Generator wi ll shift out one bit for each bit transmitted by

the SCC channel.

0Selects Scramble Zeros

enerator pattern (when in V.54 mode).

1Selects Scramble Ones

enerator pattern (when in V.54 mode).

0Receiver disabled. Receiver Threshold Counter and Receiver Error Counter

are cleared to zero.

1Receiver enabled. Receiver will shift in one bit for each data bit received by

the SCC channel.

0Selects Scramble Zero receiver pattern (when in V.54 mode).

1Selects Scramble One receiver pattern (when in V.54 mode).

Chapter 7: V.54/2047 Units 191

V.54/2047 Register Descriptions

VxCS[0] - VxDFG ( Re ceiver T hreshol d D ete cted Fla g)

This bit is set by hardware and cleared by software. It is either the Receiver Threshold

Detected Interrupt Flag (V.54 mode) or the Receiver Threshold Counter Overflow

Interrupt Flag (2047 mode). When this bit gets set, an interrupt is g enerated, if enabled.

The bit is cleared, and the interrupt is removed, by writing ‘1’ to this bit po sition.

7.6.2 VxCFG: Unit x Configuration Register

VxCFG[7:3] - VxT11 through V xT7 ( Receiver T hreshol d)

The Receiver Threshold is written to this five-bit field. In V.54 mode, when the five most

significant bits of the Receiver Threshold Counter (VxTC11-VxTC7) equal the Receiver

Threshold (VxT11-VxT7), the VxDFG interrupt flag bit will be set by hardware. The

Receiver Threshold is not active during 2047 mode operation.

VxCFG[2:0] - VxWT2 through VxWT0 (Recei ver Error Weight)

The Receiver Error Wei ght is the value that will be subtracted from the Receiver

Threshold Counter for each erroneous bit detected. As shown in the figure above, the

value subtracted will be the binary value in these three bits, plus one.

Mode Description

V.54 mode If operatin

in V.54 mode, this bit

ets set when the Receiver Threshold is

detected.

2047 mode If operatin

in 2047 mode, this bi t

ets set when the 12-bit Receiver Threshold

Counter (which is a raw bit counter in 2047 mode) overflows from 4095 to 0.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000

001

010

011

100

101

110

111

Error weight = 1

Error weight = 2

Error weight = 3

Error weight = 4

VxT7

VxT8

VxT9

VxT10

VxT11

Error weight = 5

Error weight = 6

Error weight = 7

Error weight = 8

192 Chapter 7: V.54/2047 Units

V.54/2047 Register Descriptions

7.6.3 VxTCL: Unit x Receiver Threshold Counter Low Byte

This register contains the Least Significant Byte of the 12-bit Receiver Threshold

Counter. See VxTCH below for description.

7.6.4 VxTCH: Unit x Receiver Threshold Counter High Byte

Bits [3:0] of this register contain the Most Significant four bits of the 12-bit Receiver

Threshold Counter. Bits [7:4] are reserved and must be written with zero.

The Receiver Threshold Counter is a 12-bit up-counter, which is cleared to zero upon

reset, or when the receiver is disabled by writing VxRE = 0. The counter functions

differently in V.54 and 2047 modes.

V.54 mode: If ope rating in V.54 mode , the coun ter will increment (by one) for every

good bit received, and decrement by (VxCFG[2:0] + 1) for every erroneous bit received.

The counter will never decrement belo w zero. When the counter increments such that the

Receiver Threshold is reached (VxTC11:VxTC7 = VxT11:VxT7), the VxDFG flag bit

will be set, generating an interrupt if enabled.

2047 mode: If operating in 2047 mode, the counter operates as a simple bit-counter, and

increments by one for every bit received. When the counter overflows (rolls over from

4095 to 0) every 4096 bits, the VxDFG flag bit will be set, generating an interrupt if

enabled.

7.6.5 VxEC: Unit x Receiver Error Counter

The Receiver Error Counter is an 8 bit up-counter, which is cleared to zero upon reset,

when the receiver is disabled using VxRE = 0, or when V.54 mode is selected using

VxSEL = 0. This counter is only operational in 2047 mode. For every erroneous bit

received in 2047 mod e, the cou nter increments by one. When the counter overflows (rolls

over from 255 to 0) every 256 errors, the VxVFG flag will be set, generating an interrupt

if enabled.

76543210

VxTC7 VxTC6 VxTC5 VxTC4 VxTC3 VxTC2 VxTC1 VxTC0

76543210

Reserved Reserved Reserved Reserved VxTC11 VxTC10 VxTC9 VxTC8

76543210

VxEC7 VxEC6 VxEC5 VxEC4 VxEC3 VxEC2 VxEC1 VxEC0

Chapter 7: V.54/2047 Units 193

V.54 and 2047 Circuits

7.7 V.54 and 204 7 Circuits

Figure 7-5 V.54 Generator

Figure 7-6 V.54 Receiver

1 0

VxGP

Pattern Out

Starting Pattern 10101

XOR

Flip-flop

LEGEND

Counter = Threshold

Threshold

Counter

VxRP

Pattern In

XOR

Flip-flop

LEGEND VxCFG[7:3]

Threshold

Set VxDFG

VxCFG[2:0]

(Weight)

Correct: +

Error: -

/ 3

±+-

194 Chapter 7: V.54/2047 Units

V.54 and 2047 Circuits

Figure 7-7 2047 Generator

Figure 7-8 2047 Receiver

Note: See Appendix D for XA-SCC V.54/2047 Generator Output Listings.

1 0

VxGP= 0 Pattern

Out

Starting

Pattern 101010101

XOR

Flip-flop

LEGEND

VxVFG

VxRP = 0

Error

Counter

Add one for

every error 255-0

Rollover

Detect

VxDFG

Threshold

Counter

4095-0

Rollover

Detect

Pattern In

XOR

Flip-flop

LEGEND

Count every bit

Chap ter 8: IDL In terface 195

Chapter 8

IDL Interface 8

Contents

8.1 Introductio n................................................................................................................................................196

8.2 IDL Interface Architecture..........................................................................................................................196

8.3 IDL Bus Si

nals.........................................................................................................................................199

8.4 IDL Interface Clocks..................................................................................................................................200

8.5 Assi

nin

B1, B2, and D Channel s to SCCs...... .......................................................................................203

8.6 B Channel Bi t Maskin

and Enable...........................................................................................................203

8.7 Confi

uration Example...................... ................................ ..................... ............................... ....................206

8.8 IDL Interface Re

ister Descript ions...........................................................................................................208

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

196 Chapter 8: IDL Interface

Introduction

8.1 Introduction

The XA-SCC IDL Interface is a full-duplex ISDN interface used to connect the XA-SCC

to a physical layer device, on an Interchip Digital Link (IDL) bus. When configured with

IDL, three of the XA-SCC’s serial ports (SCC0, SCC1, and SCC2) can b ecome I DL slave

devices, which are driven by time multiplexed clock signals derived from L1Clk, the IDL

master clock.

For ISDN terminal adaptor applications, the XA-SCC IDL Interface connects the

XA-SCC to an ISDN transceiver, such as a U Interface chip, or other device. In this case,

SCC1, SCC2, and SCC0 are easily configured to service the ISDN B1, B2, and D

channels respectively. Other configurations are available as well.

The XA-SCC IDL Interface currently supports both the 8-Bit Frame (also known as

“Short Frame”) and the 10-Bit Frame IDL formats (see Figure 8-9 and Figure 8-10).

8.2 IDL Interface Architecture

SCC0, SCC1, and SCC2 can all be connected to IDL or used without IDL. SCC3 has no

hardware connections to the IDL bus signals and can never be used with IDL. If the IDL

block is “on,” then SCC0 is automatically connected to IDL. SCC1 and SCC2 can be

connected or not, as needed.

8.2.1 IDL Interface Block Diagram

Figure 8-1 is a simplified block diagram of the XA-SCC IDL Interface. The following

description can best be followed while referring to that figure.

If the IDL block, as a whole, is “on” (represented in the block diagram by the state

“IDLOn = 1”), then SCC0 automatically gets its two clock inputs (RTClk and TRClk),

and its data input (RxD), fr om the IDL Interface. Also, SCC0’s data output (TxD), is

prevented from directly reaching the TxD0 pin (Pin 96) output driver, but is used by the

IDL Interface. When IDL is “on”, SCC0 is always using IDL. There is no actual,

individual “IDLOn” bit. “IDLOn” is formally defined by a three-bit field in the MSI

Control Register. Specifically IDLOn = MSI Control[2:0] ≠ 111.

Conversely, “IDLOff” is formally defined by IDLOff = MSI Control[2:0] = 111. If the

IDL block is “off” (represented in the block diagram by the state “IDLOn = 0”), then

SCC0 gets its RTClk signal from the RTClk0 pin (Pin 95, with appropriate Pin Mux

programming), its TRClk signal from the TRClk0 pin (Pin 94, with appropriate Pin Mux

programming), and its RxD signal directly from the RxD0 pin (Pin 97). Also, SCC0’s

TxD output is routed to the TxD0 pin (Pin 96) output driver, bypassing the IDL Interface.

Chap ter 8: IDL In terface 197

IDL Int erface Arch itectur e

Both SCC1 and SCC2 can connect to, or bypass, the IDL interface, independent of the

state of IDLOn. However, connecting an SCC channel to IDL, with IDL “off,” would

render that SCC channel useless.

If SCC1 is connected to IDL, using MSI Control[7] = 1 (shown in the block diagram by

the state “SC1isIDL = 1”), then SCC1 gets its two clock inputs (RTClk and TRClk), and

its data input (RxD), from the IDL Interface. SCC1’s data output (TxD) is used by the

IDL Interface, but is prevented by a logic gate in the Pin Mux block from affecting the

state of the TxD1 pin (Pin 66). See Section 11.5.7, “Pin 66: P3.6_TxD1” for details.

If SCC1 is not connected to IDL (SC1isIDL = MSI Control[7] = 0), then SCC1 gets its

RTClk signal from the RTClk1 pin ( P in 56), its TRClk signal from the TRClk1 pin (Pin

67), and its RxD signal from the RxD1 pin (Pin 65). SCC1’s TxD output is ignored by the

IDL Interface, but passed to the TxD1 pin (Pin 66) by a logic gate in the Pin Mux block.

All four of these signal paths require Pin Mux programming (see Chapter 11, “XA-SCC

Pins,” for details).

If SCC2 is connected to IDL, using MSI Control[8] = 1 (shown in the block diagram by

the state “SC2isIDL = 1”), then SCC2 gets its RTClk, TRClk, and RxD from the IDL

Interface. SCC2’s TxD is used by the IDL Interface, but is prevented by a logic gate in

the Pin Mux block from affecting the state of the TxD2 pin (Pin 69). See Section 11 .5.10,

“Pin 69: P1.1_ TxD2” for details.

If SCC2 is not connected to IDL (SC2isIDL = MSI Control[8] = 0), then SCC2 gets its

RTClk signal from the RTClk2 pin ( P in 70), its TRClk signal from the TRClk2 pin (Pin

71), and its RxD signal from the RxD2 pin (Pin 68). SCC2’s TxD output is ignored by the

IDL Interface, but passed to the TxD2 pin (Pin 69) by a logic gate in the Pin Mux block.

Again, these signal paths require Pin Mux programming.

The V.54/2047 circuitry may or may not be active while an SCC channel is transmitting

and receiving. In any case, the connection to IDL is still controlled by IDLOn, SC1isIDL,

and SC2isIDL.

198 Chapter 8: IDL Interface

IDL Int erface Archit ect ure

Figure 8-1 IDL Interface Block Diagram

L1RxD0

TClk0

RClk0

L1RxD1

TClk1

RClk1

3/0

IDL On

MUX

TRClk0

L1RxD2

TClk2

RClk2

3/0

MUX

3/0

MUX

IDL On

SC2IsIDL

SC1IsIDL

IDL

PIN 94

RTClk0

RxD0

PIN 95

RxD1 PIN 65

PIN 97

TRClk1 PIN67

RTClk1 PIN56

RxD2 PIN68

TRClk2 PIN 71

RTClk2 PIN 70

TxD1 PIN 66

TxD2 PIN69

L1RxD PIN 91

L1RQ PIN 92

L1GR

PIN 90

SDS2 PIN 94

SDS1 PIN 93

L1Sy1 PIN 95

L1Clk

PIN 96

L1TxD

TriStEn

PIN MUX

v.54

2047

TxD

RxD

TRClk

RTClk

SCC0

v.54

2047

TxD

RxD

TRClk

RTClk

SCC1

v.54

2047

TxD

RxD

TRClk

RTClk

SCC2

NOTE:

SCC3 never

connects to

IDL.

Chap ter 8: IDL In terface 199

IDL Bus Si gnals

8.3 IDL Bus Signals

There are eight IDL bus signals, four inputs and four outputs, in the XA-SCC. These

appear on the eight uppermost pins shown on the right side of Figure 8-1. All of the IDL

bus signals, except L1RxD on Pin 97 and L1TxD on Pin 96, requiring Pin Mux

programming. The eight IDL bus signals are:

8.3.1 How the XA-SCC Uses D Channel Request and Grant

The XA-SCC IDL Interface requests use of the D channel by asserting L1RQ. The L1GR

grant for D channel is only sampled during Sync, approximately in the middle of the

L1SY1 sync pu lse. If L1GR is active, then D channel grant is be ing given to the

XA-SCC, and SCC0 begins transmitting the Opening Flag during the D channel’s bit

time slots. During this part of the transmission, the IDL Interface continues to monitor

L1GR, once during each L1SY1 sync pulse.

If D channel grant is removed, it is guaranteed to occur before the 32nd D channel bit

time. In this case, the external device has negated L1GR, and the XA-SCC transmission

is stopped. The Pin 96 output driver is tri-stated during subsequent D channel bit times.

In the event of loss of grant, the IDL Interface again requests use of the D channel by

asserting L1RQ. When L1GR is received, the XA-SCC begins retransmitting the frame.

Up to 3 2 b i ts may have been sent by SCC0 before the grant was re moved . Howev er, these

bits are internally stored by the XA-SCC IDL Interface and automatically retransmitted

when D channel grant is restored. There is no need for software to manage these bits.

Signal Description

L1Clk (Pin 95) (input to the XA-SCC) This is the master IDL clock si

nal.

L1SY1 (Pin 93) (input to the XA-SCC) This is the IDL Sync si

nal, which desi

nates the

innin

of an IDL f rame.

L1GR (Pin 92) (input to the XA-SCC) The physical layer interface device

rants permission to

transmit on the D channel by assertin

L1GR (active hi

h) to the XA-SCC.

L1RxD (Pin 97) (input to the XA-SCC) This is the IDL receive data si

nal.

L1TxD (Pin 96) (output from the XA-SCC) This is the IDL transmit data si

nal.

L1RQ (Pin 91) (output from the XA-SCC). The XA-SCC requests permission to transmit on the

D channel by assertin

L1RQ (active hi

h).

SDS1 (Pin 94) (output from the XA-SCC) This is the IDL Serial Data Strobe 1 si

nal. It is used

as an enable st robe by devices (such as CODECs) that do not, by themselves,

identify the IDL time slots.

SDS2 (Pin 90) (output from the XA-SCC) This is the IDL Serial Data Strobe 2 si

nal. Its function

is similar to tha t of SDS 1 .

200 Chapter 8: IDL Interface

IDL Int erfac e C locks

8.3.2 Assigning SDS1 and SDS2

SDS1 and SDS2 are assigned to be active (High) during either B1 or B2, but they cannot

be active at the same time. The assignments are made using the SDC1 (MSI Control[9])

and SDC2 (MSI Control[10]) bits.

8.4 IDL Interface Clocks

The IDL Interface always receives its clock from L1Clk, the master IDL clock input

signal, which is one function of Pin 95. In order for Pin 95 to function as an input, and

pass L1Clk to the IDL Interface, the Pin 95 output driver must be put into it s

High-Impedance state. This is accomplished by writing P0CFGB[5] P0CFGA[5] = 10 =

Hi-Z (see Chapter 11, “XA-SCC Pins,” for details).

Then, when IDL is “On,” the IDL Interface will supply SCC0 with the RTClk0 and

TRClk0 clocks, as shown in Figure 8-2. Similarly, when “SCC1 is IDL” and “SCC2 is

IDL,” the IDL Interface will supply the RTClk and TRClk clocks to SCC1 and SCC2, as

shown in Figure 8-3 and Figure 8-4 respectively.

Finally, all SCC s that are connected to IDL must be configured to receive RxClk from

RTClk, TxClk from TRClk, and to operate in 1x Clock Mode. This procedure is covered

in detail in Section 5.6, “SCC Clocks”, but the results are included below.

Assignment Description

SDC1 = 0 Assert SDS1 durin

SDC1 = 1 Assert SDS2 durin

SDC2 = 0 Assert SDS2 durin

SDC2 = 1 Assert SDS1 durin

Assignment Description

WR0[1] = 0 Selects RT Clk for RClk

WR11[6 :5] = 00 Selects RClk for RxClk

WR11[4: 3] = 01 Selects TRClk for TxClk

WR4[7:6] = 00 Selects 1x Clock mode

Chap ter 8: IDL In terface 201

IDL Interface Clocks

8.4.1 Maximum Frequency for L1Clk

The master IDL clock signal, L1Clk, must not exceed PClk / 4 (recall, PClk = CClk / 2).

Therefore, if CClk = 29.4912 MHz, then PClk = 14.7456 MHz, and so maximum

L1Clk = 3.6864 MHz. Common industry practice is that L1CLK not exceed 2.56 MHz.

Figure 8-2 IDL Clocks to SCC0

ComClk

PClk

BRG0

Sync0

RTClk0

IDL Rx

ClkGen

IDL Tx

ClkGen

IDL On

P0[0] data in

P0[5] data in

TRClk0

P0[4] data in

P0CFGA[0]

P0CFGB[0]

P0CFGA[5]

P0CFGB[5]

P0CFGA[4]

P0CFGB[4]

P0[5]

2 /

P0[4]

2 /

P0[0] IDLOn

2 /

SCC0IDLPads

P0.5_RTClk0_L1Clk

PIN 95

P0.0__Sync0_BRG0_SDS2

PIN 90

P0.4_TRClk0_SDS1

PIN 94

IDLOff

SDS2

IDLOff

SDS1

202 Chapter 8: IDL Interface

IDL Int erfac e C locks

Figure 8-3 IDL Clocks to SCC1

Figure 8-4 IDL Clocks to SCC2

BRG1

Sync1

IDL Rx

ClkGen

IDL Tx

ClkGen

P3[3] data in

P3[0] data in

TRClk1

SC1isIDL

P3[7] data in

CS4

(from MIF)

P3[0]

P3[7]

P3[3]

From

Timer 1

SCC1IDLPads

P3.0_CS4_RAS4_RTClk1

PIN 56

P3.3_Timer1_BRG1_Sync1

PIN 63

P3.7_Int1_TRClk1

PIN 67

ComClk

PClk

RTClk0

P3CFGA[3]

P3CFGB[3]

P3CFGA[0]

P3CFGB[0]

2 /

P3CFGA[7]

P3CFGB[7]

2 /

BRG2

Sync2

IDL Rx

ClkGen

IDL Tx

ClkGen

SC2isIDL

P1[7] data in

P2[2] data in

TRxC2

SC2isIDL

P1[3] data in

P2[2]

P1[3]

P1[7]

SCC2IDLPads

P1.2_RTClk2

PIN 70

P1.7_BRG2_Sync2

PIN 75

P1.3_TRClk2

PIN 71

P2CFGA[2]

P2CFGB[2]

2 /

P1CFGA[7]

P1CFGB[7]

2 /

P1CFGA[3]

P1CFGB[3]

2 /

ComClk

PClk

RTClk2

Chap ter 8: IDL In terface 203

Assig ning B1, B 2, and D C han nels to SCC s

8.5 Assigning B1, B2, and D Channels to SCCs

The IDL Interface time multiplexes the attached SCCs, so that they transmit and receive

data during their assigned B1, B2, and D channel time slots.

• SCC0 can be assig ned to the D Channel, the B1 Chann el, the B2 Channel, or both the

B1 and B2 Channels. The assignment is made using the three-bit field in MSI

Control[2:0] (see Section 8.8.1, “MSI Control Register”).

• SCC1 can be assigned to the B 1 Channel, the B2 Channel, or both the B1 and B2

Channels. The assignment is made using the two-bit field in MSI Control[4:3] (see

Section 8.8.1, “MSI Control Register”).

• SCC2 can be assigned to the B 1 Channel, the B2 Channel, or both the B1 and B2

Channels. The assignment is made using the two-bit field in MSI Control [6:5] (see

Section 8.8.1, “MSI Control Register”).

An SCC channel which is connected to IDL can be temporarily paused without

disconnecting the SCC from IDL. This is accomplished with the same bit field that is

used to assign ISDN channels to that SCC.

8.6 B Channel Bit Masking and Enable

8.6.1 B Channel Bit Masking

Individual bit time slots in the B1 and B2 channels can be enabled or disabled for use by

the XA-SCC. The 16-bit DataMask Register is used for this purpose. A DataMask bit set

to one activates the corresponding B Channel bit time slot for both transmission and

reception. A DataMask bit cleared to zero disables the corresponding B channel bit time

slot.

Masking a B channel bit time slot (writing a zero to a DataMask bit) has the following

three effects:

1. RTClk and T RCl k clock pulses are withheld from the SCC assigned to that B

channel during the masked bit time, so no bit is shifte d into, or out of, the SCC.

2. The L1TxD (Pin 96) pin driver is tri-stated during the masked bit time, so that the

external device (e.g. a U-interface chip) can be driven by some other, external, data

source.

Assignment Description

MSI Control[2:0] = 000 SCC0 is connected to IDL (IDL is On), but SCC0 paused.

MSI Control[4:3] = 00 SCC1 is connected to IDL, but SCC1 paused.

MSI Control[6:5] = 00 SCC2 is connected to IDL, but SCC2 paused.

204 Chapter 8: IDL Interface

B Chann el Bit M askin g and Enabl e

3. The corresponding SDS1 or SDS2 strobe output goes low (inactive) during the

masked bit time.

DataMask[15] masks the first B1 channel bit time slot after the L1SY1sync pulse, and

DataMask[0] masks the last B2 Channel bit time slot, as indicated in Figure 8-5. Note

that 8-Bit IDL Format is shown, but the DataMask bits mask the same relative B Channel

bits in 10-Bit IDL Format.

Figure 8-5 DataMask Bits and B Channel Bit Time Slots

8.6.2 B Channel Enable

Transmission and reception for each of the B Channels can be independently enabled or

disabled, using the B 1En able an d B2Enable bits in the MSI Contro l R egister (B 1En able =

MSI Control[11], B2Enable = MSI Control[12]). When B1Enable or B2Enable are set to

one, transmission and reception on the respective B Channel begins after the next Sync

pulse. When the bit is cleared, transmission and reception on that B channel stops after

the next Sync pulse.

Disabling a B channel (writing a zero to either B1Enable or B2Enable) has the following

three effects:

1. RTClk and T RCl k clock pulses are withheld from the SCC assigned to that B

channel during the channel’s 8 bit ti mes, so no bits are shifted into, or o ut of, the

SCC.

2. The L1TxD (Pin 96) pin driver is tri-stated during the channel’s 8 bit times , so that

the external device (e.g. a U-interface chip) can be driven by some other, external,

data source.

L1CLK

(FSC) L1SY1

Time

125µsec

CLOCK NOT TO SCALE

DataMask 715 14 13 12 11 10 9 8 6 35 4 2 1 0

L1TxD/L1RxD 1st last

B2 ChannelB1 Channel

Chap ter 8: IDL In terface 205

B Cha nnel Bit M asking a nd Enable

3. The SDS1 or SDS2 strobe assigned to that B channel is unaffected. That is, it

continues to operate during the B chan nel’s 8 bit times, and would still be af fected b y

masked bits in the DataMask Register. This allows the SDS strobes to activate an

external device (such as a CODEC) during the time belonging to the B channel

which is not being used.

If desired, the SDS1 and SDS2 strobes can be effectively disabled, while the B Channel

they are assigned to remains active, by clearing a GPI/O Port bit. Writing a zero to P0[4]

prevents the SDS1 strobe from asserting Pin 94 high (see Figure 8-2 and “Pin 94:

P0.4_TRClk0_SDS1” for details). Writing a zero to P0[0] prevents the SDS2 strobe from

asserting Pin 90 high (see Figure 8-2 and “Pin 90: P0.0_Sync0_BRG0_S DS2” for

details). Caution: Disabling the data strob es in this manne r wi ll take effect immediately,

asynchronously with respect to L1SY1. Care must be taken so that a data strobe is not

disabled du ring the B Channel time to which that data s trob e is assigned.

An illustrative example of B Channel Bit Masking, with SDS1 disa bled using

P0[4],appears in Figure 8-6. The 8-Bit Frame IDL format is shown, but the principles are

the same for the 10-Bit Frame IDL format.

Figure 8-6 DataMask and P0[4] Affecting SDS1 and SDS2

L1CLK . . . . . . . . . .

L1SY1

SDS1

L1TxD/L1RxD B1

7 6 5 4 B1

2 1 0 B2

7 6 5 4 3 2 1 0 D

125µsec

CLOCK NOT TO SCALE

Drive_L1TxD

SDS2

NOTES: 1. SDS1 masked out by P0[4] = 0, and assigned to B2.

2. SDS2 affected by DataMask, and assigned to B1.

3. Drive_L1TxD is an internal signal, shown here to indicate when the XA-SCC drives TxD.

4. DataMask = F7FF.

5. MSI Control = 3FCC.

206 Chapter 8: IDL Interface

Config uration Example

8.7 Conf iguratio n Exam ple

This example and the timing diagrams which follow, demonstrate configuring the IDL

Interface for a typical ISDN terminal adaptor application. The programming sequence

shown in the flow chart is recommended, although other sequences may work.

The following list details the individual steps in configuring the MSI Control and

DataMask Registers (the second and third blocks in the flow diagram) for this example.

• Write to the MSI Control Register as follows:

– Make sure the diagnostic bits are clear: MSI Control[15:14] = 00.

– Activate 10-Bit Frame IDL format: MSI Contro l[13] = 0.

– Do not enable B1 and B2 Channels yet: MSI Control[12:11] = 00.

– Assign the B1 Channel to SCC1: MSI Control[4:3] = 01.

– Assign the B2 Channel to SCC2: MSI Control[6:5] = 10.

– Connect SCC1 to IDL: MSI Cont rol[7 ] = 1. Mak e sure Pin Mux Contro l[4] = 0, and

Pin 66 has been programmed as needed by GPI/O P3[6].

– Connect SCC2 to IDL: MSI Cont rol[8 ] = 1. Mak e sure Pin Mux Contro l[5] = 0, and

Pin 69 has been programmed as needed by GPI/O P1[1].

– Assert SDS1 during B1: MSI Control[9] = SDC1 = 0.

– Assert SDS2 during B2: MSI Control[10] = SDC2 = 0.

– Turn “IDL On,” assign the D Channel to SCC0, and start D Channel: MSI

Control[2:0] = 100.

Program Pin Mux

Program MSI Control, but

wit h B1Enable and

B2Enable cleared to zero.

Write DataMask.

Set up SCC0 - SCC2 and

DMA.

Set B1Enable and/or

B2Enable.

Chap ter 8: IDL In terface 207

Config uration E xample

• Write DataMask Register as follows:

– Activate all 8 bit times for the B1 Channel: DataMask[15:8] = FFh.

– Activate only th e first three bit tim e s (and mask the last 5 bit times) for the B2

Channel: DataMask[7:0] = E0h.

• Enable B1 & B2 Channels (when ready): Write MSI Control[12:11 ] = 11.

• Final values: DataMask = FFE0 and MSI Control = 19CC.

Later, B1 and B2 can be reassigned by first clearing the enables, changing the assigns in

MSI Control[6:3], and then reenabling.

The timing which would result from this configuration is shown in Figure 8-7. Note that

the XA-SCC is usin g the D Channel in this exam ple. It is assumed in Figure 8-7 that D

Channel grant has been received. Figure 8-7 does not show L1RQ or L1GR.

Figure 8-8 shows D Channel grant being given to the XA-SCC, and the first 2 bits being

clocked i n and ou t of SCC0 using t h e D chan nel ’s bit t i me sl ot s. Not i ce that L1 GR i s on ly

sampled during Sync.

Figure 8-7 Bit Masking, Showing Clocks to SCC1 and SCC2

L1CLK . . . . . . . . . .

L1SY1

TRClk and RTClk to SCC1

TRClk and RTClk to SCC2

SDS1

L1RxD B1 Channel D DX B2 Channel

125µsec

CLOCK NOT TO SCALE

L1TxD B1 Channel

1 1 1 1 1 1 1 1

DataMask has masked out 5 of the 8 B2 bits

SDS1 assigned to B1

XB2

Tri-State Enable for L1TxD

DataMask 1 1 1 0 0 0 0 0

SDS2 SDS2 assigned to B2

208 Chapter 8: IDL Interface

IDL Interface Register Descriptions

Figure 8-8 D Channel Grant, Showing Clocks to SCC0

8.8 IDL Interface Register Descriptions

8.8.1 MSI Control Register

The 16-bit MSI Control Register contains the configuration bits for the IDL Interface. It

is a Read/Write Memory Mapped Register, with MMR Address Offset 2C0h. All MSI

Control Register bits take effect during the L1SY1 sync pulse, so all IDL changes occur

on a frame boundary.

MSI Control[15:14] - Reserved Diagnostic Bits, Write 0 Only

Only write zeros to these bits. Setting either of these b its will cause the IDL to

malfunction.

MSI Control[13]

0 Activates 10-Bit Frame I DL format (see Fi

ure 8-10).

1 Activates 8-Bit Frame I DL format (see Fi

ure 8-9).

L1CLK . . . . . . . . . .

L1SY1

125µsec

CLOCK NOT TO SCALE

Tri-State Enable for L1TxD

TRClk and RTClk to SCC0

L1GR1 //

L1RxD B1 Channel D DX B2 Channel

L1TxD B1 Channel D DXB2

Chap ter 8: IDL In terface 209

IDL Int erface R egiste r Des criptions

MSI Control[12] - B2Enable

MSI Control[11] - B1Enable

MSI Control[10] - SDC2

MSI Control[9] - SDC1

MSI Control[8] - SC2isIDL

MSI Control[7] - SC1isIDL

0 B2 channel disabled (Stop). L1TxD is tri -stated, and clocks are disabled to the

assi

ned SCC durin

B2. SDS1 and SDS2 are not affected.

1 B2 transmission be

ins after next Sync pulse. L1TxD is not tri-stated, and

clocks are enabled to the assi

ned SCC durin

B2. SDS1 and SDS2 are not

affected.

0 B1 channel disabled (Stop). L1TxD is tri -stated, and clocks are disabled to the

assi

ned SCC durin

B1. SDS1 and SDS2 are not affected.

1 B1 transmission be

ins after next Sync pulse. L1TxD is not tri-stated, and

clocks are enabled to the assi

ned SCC durin

B1. SDS1 and SDS2 are not

affected.

0 Asserts SD S2 durin

B2 time slot.

1 Asserts SD S1 durin

B2 time slot.

0 Asserts SD S1 durin

B1 time slot.

1 Asserts SD S2 durin

B1 time slot.

0 SCC2 connected to Pin Mux.

1 SCC2 connected to IDL.

0 SCC1 connected to Pin Mux.

1 SCC1 connected to IDL.

210 Chapter 8: IDL Interface

IDL Interface Register Descriptions

MSI Control[6:5] - SCC2

MSI Control[4:3] - SCC1

MSI Control[2:0] - SCC0

8.8.2 DataMask Register

The 16-bit DataMask Register is used to mask out individual bit time slots from the B1

and B2 channels. It is a Read/Writ e Memory Mapped Register, with MMR Address

Offset 2C2h. A DataMask bit set to ‘1’ activates the corresponding bit in the B1 or B2

channel for both transmission and reception. A DataMask bit cleared to ‘0’ disables the

corresponding B channel bit.

DataMask[15] masks the first B1 channel bit time slot after the L1SY1sync pulse, and

DataMask[0] masks the last B2 Channel bit time slot (see Section 8.6, “B Channel Bit

Masking and Enable” for details).

00 Disables clocks to SCC2 (Pause).

01 Assi

ns B1 channel to SCC2.

10 Assi

ns B2 channel to SCC2.

11 Assi

ns both B1 and B2 channels to SCC2.

00 Disables clocks to SCC1 (Pause).

01 Assi

ns B1 channel to SCC1.

10 Assi

ns B2 channel to SCC1.

11 Assi

ns both B1 and B2 channels to SCC1.

000 Disabl es clocks to SCC0 (Pause) (IDL On).

001 Assi

ns B1 channel to SCC0 (I DL On).

010 Assi

ns B2 channel to SCC0 (I DL On).

011 Assi

ns both B1 and B2 channels to SCC0 (IDL On).

100 Assi

ns D channel to StbCC0 (IDL On).

101 Reserved, don’t write 101 (IDL On).

110 Reserved, don’t write 110 (IDL On).

111 IDL Off and SCC0 connected to Pin Mux.

Chap ter 8: IDL In terface 211

IDL Int erface R egiste r Des criptions

Figure 8-9 8-Bit Frame (“Short Frame”) IDL Format

Figure 8-10 10-Bit Frame IDL Format

L1CLK . . . . . . . . . .

L1SY1

125µsec

CLOCK NOT TO SCALE

SDS2

SDS1

L1TxD/L1RxD B1 Channel DB2 Channel D

L1CLK . . . . . . . . . .

L1SY1

125µsec

CLOCK NOT TO SCALE

SDS2

SDS1

L1TxD/L1RxD B1 Channel D B2 Channel DX

212 Chapter 8: IDL Interface

IDL Interface Register Descriptions

Chapter 9: SCP Interface 213

Chapter 9

SCP Interface 9

Contents

9.1 Introductio n................................................................................................................................................214

9.2 The SCP State Machine............................................................................................................................ 215

9.3 SCP Timin

............................................................................................................................................... 216

9.4 SCP Interrupts...........................................................................................................................................218

9.5 SCP Re

ister Descriptions........................................................................................................................219

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

214 Chapter 9: SCP Interface

Introduction

9.1 Introduction

The XA-SCC SCP Interface is a full duplex, synchronous serial communication bus,

similar to SPI and Microwire. General Purpose I/O Port (GPI/O) pins can be used to

provide SCP enables (CS) to slave devices, and so the number of supportable slave

devices is limited on ly by the number of available Port pins. For an application which

uses only one SCP slave device, it is not usually necessary to provide a CS, if the slave

device’s enable can be hard-wired active.

The SCP Interface provides selectable inverted or non-inverted clock polarities, and a

selectable bit rate. Data frames can be from one to eight bits in length, and the SCP

Interface will generate an interrupt, if enabled, upon completion of an SCP bus cycle (one

to eight bi t times, full duplex.)

The SCP Interface consists of a state machine, an 8-bit (left-shifting) shift register, and

three Memory Mapped Registers. As shown in Figure 9-1, the SCP Interface’s clock

signal to the slave devices, called “SCPClk,” is output on Pin 98. Tr ansmit data are

shifted from the shift register to the SCPTx function of Pin 99 (P0.6_SCPTx) and receive

data are shifted from the SCPRx function of Pin 100 (P0.7_SCPRx) to the shift register.

Both GPI/O Pins 99 and 100 must first be programmed to activate these SCP functions.

See Section 11.5.34 "Pin 99: P0.6_SCPTx" and Section 11.5.35 "Pin 100: P0.7_SCPRx"

in Chapter 11 for details.

There are three MMRs related to the SCP Interface:

SCPCFG Contains the confi

uration bits for SCPClk. See Section 9.5.1.

SCPD Provides acces s to the shift re

ister. Data to be transmitted are written to this

ister, and recei ved data are read from this re

ister. See Section 9.5.2.

SCPCS Contains control and st atus bits for the state machine. See Section 9.5.3.

Chapter 9: SCP Interface 215

The S CP State M achine

Figure 9-1 SCP Block Diagram

9.2 The SCP State Machine

The actions of the state machine (and thus SCP bus cycles) are controlled by bits in the

SCPCS Register. The state machine is started by writing ‘1’ to the SPSTT bit

(SCPCS[7]). While the st ate machine is running SPSTT will remain set, and will be

cleared to zero by hardware when the state machine stops.

The number of bits to be shifted in an SCP bus cycle is selected using the three-bit field

SCPCS[6:4] (S PB2 SPB1 SPB0). The number of bits is given by the binary value stored

in this field, plus one. The SCP Shift Reg ister shifts left, most significant bit first.

Therefore, if fewer than eight bits are selected, Tx data written to the SC PD R e gister

must be left justified, and Rx data read from the SCPD Register will be right justified.

The state of the SCPTx pin, before and after the SCP bus cycle, is selected using

SCPCS[0] ( SPIDL for SCP Idle.) Notice that the SCPTx idle state is not n ecessarily the

same as the SCPClk idle state, which results from the SCPClk polarity selected using

SCPCFG[ 7] (SPCP).

Warning: No writes to any SCP Registers should be made while the state machine is

runnin g. Th e SPSTT bit can be polle d, if desi red. At the com pleti on of the SCP bu s

cycle, on the falling edge of SPSTT, the SPFG bit will be set, generating a maskable

processor interrupt.

70214563

P0.7_SCPRx

PIN 100 PAD LOGIC

P0.6_SCPTx

PIN 99 PAD LOGIC

SCPClk

PIN 98 SCP

Clock

Generator

SCP

State

Machine SPFG

"ESCP"

SFR 427[3]

"SCP"

SCP Shift

To Event

Interrupts

216 Chapter 9: SCP Interface

SCP Timing

9.3 SCP Timing

9.3.1 Data Rate - Frequency of SCPClk

The frequency of SCPC lk determines the rate at which data bits are shifted into and out

of the SCP Interface, and is selected using Bits[3:0] of the SCPCFG Register. The

frequencies of SCPClk and CClk (the system clock) have the following relationship:

Writin g a value of zero (0000b) is not permitted in this field, thus the fastest b it rate

allowed is CClk/8. Therefore, if CClk = 29.4912 MHz, the maximum SCPClk frequency

is 3.6864 MHz (with SCPCFG[3:0] = 0001) and the minimum frequency is 460.8 KHz

(with SCPCFG[3:0] = 1111 ).

9.3.2 Description of SCP Bus Cycle

The polarity of SCPClk is selected using the SPCP bit (SCPCFG[7]). SPCP = 1 selects

“normal” SCPClk, and SPCP = 0 selects “inverted” SCPClk. When SPCP = 1, the idle

state of SCPClk is logic ‘0 ’, data are driven onto SCPTx on rising edges of SCPClk, and

SCPRx is sa mpled on falling edges. When SPCP = 0, the idle state of SCPClk is logic

‘1’, data are driven onto SCPTx on falling edges, and SCPRx is sampled on rising edges .

A typica l 8-bit SCP bus cycle, as shown in Figure 9-2, is described below. The list

numbers refer to the numbered pointers in the figure.

Before the sequence begin s, SCPClk is in the idle state determined by the value of the

SPCP bit, and SC PTx is in the idle state determined by the value of the SPIDL bit. The

state of SCPRx is a don’t care. An eight bit bus cycle has been previously selected by

writing 111 to the three-bit field SCP CS[6:4].

1. SCP Enable (SCPEn) is asserted to the slave device by writing ‘0’ to the appropriate

GPI/O Port pin. Man y SCP slave devices will respond by driving data bit 7 onto the

wire we are calling SCPRx, although to the XA-SCC the state of SCPRx is still a

don’t care.

2. The bus cycle is started by writing ‘1 ’ to the SPSTT bit, and SCPD[7] is immediately

driven ont o SC PTx.

3. After 8 CClk cycles, the first transmit edge of SCPClk occurs (the rising edge if

SPCP = 1 = Normal Clock Polarity.) If the slave is n ot already driving bit 7 onto the

pin that we call SCPRx, it must do so in response to this first transmit edge.

SCPClk (Hz.) CClk

4SPCFG 3:0[]1+()

-------------------------------------------------- (Hz.) Note: SPCFG[3:0] = 0000b is illegal.=

Chapter 9: SCP Interface 217

SCP Timing

4. On the next edge (receive edge) of SCPClk, data bit 7 is sampled from the SCPRx

pin. The receiving edge is the falling edge if SPCP = 1 = Normal Clock Polarity.

5. This sequence continues, with SCPTx being updated on every Transmit edge, and a

new bit being shifted in on every receive edge, until all 8 bits have been transferred

in each direction. Both master and slave devices should transmit on the transmit

edge, and receive on the receive edge.

6. Soon after the least significant data bit has been sampled from SCPRx into the SPD

shift register, the SCP interface hardware clears the SPSTT bit to ‘0’ , and sets the

SPFG flag bit to ‘1’. SCPTx reverts to the state of the SPIDL bit, and the state of

SCPRx is again a don’t care.

7. SCP Enable (SCPEn) is remo ved f rom t h e slave d evi ce by sof twar e wri ting ‘1’ to the

appropriate GPI/O Port pin.

WARNING about A/C Timing: The slave device must not try to sample on the

transmit edge, because hold time is only guaranteed in relation to the receive edge (e.g.

SCPTx may switch several nanoseconds BEFORE the SCPClk transmit edge.)

218 Chapter 9: SCP Interface

SCP Interrupts

Figure 9-2 SCP Bus Cycle Timing with both Polarities of SCPClk

9.4 SCP Interrupts

The SCP Interface has one interrupt, SPFG (SCPCS[3]), which gets set by hardware

when the SPSTT bit is cleared at the completion of a transmission. WARNING: The

SPFG interrupt flag is cleared by writing ‘1’ to the flag’s bit position. Writing a “0” is a

NOP.

76543210 SPIDLSPIDL

SCPClk

SCPEn

SCPTx

SCPRx

NOTE: For SPCP = 1, SCPTx is updated on the rising edge of SCPClk, SCPRx is sampled on the falling edge.

SPCP = 1 (normal polarity SCPClk)

SPCP = 0 (inverted polarity SCPClk)

NOTE: For SPCP = 0

SCPTx is updated on the fallin

e of SCPClk

SCPRx is sampled on the risin

76543210 XX

2453 67

76543210 SPIDLSPIDL

SCPClk

SCPEn

SCPTx

SCPRx

76543210 XX

53 67

Chapter 9: SCP Interface 219

SCP Reg ister De scriptio ns

The SCP interrupt appears to the XA as the Event Interrupt “SCP.” This in terrup t is

enabled by setting the “ESCP” bit in SFR 427[3]. The Enable All (EA = SFR 426[7]) bit

must also be set to glob ally enable all Event Interrupts. The relevant bits for the SCP

interrupt are summarized in the tab le below.

9.5 SCP Register Descriptions

9.5.1 SCPCFG: SCP Configurati on

SCPCFG[7] - SPCP (S CP Cl k P olar it y )

SCPCFG [6:4 ] - Reserved, must be zero.

SCPCFG [3:0 ] - SPC 3 SP C2 SP C1 SP C0 (S CP Cl k Timi ng)

The binary value stored in SPC3 - SPC0 determines the frequency of SCPClk.

Interrupt Flag Bit

(MMR)

Event

Interrupt

Source

Interr upt

Vector

Address Enable Bit

(SFR)

Prior it y

Fiel d (S FR )

Global Event

Interrupt

Enable (S FR)

SPFG - - See Note

SCPCS[3]

263[3]

“SCP” 00AF-00AC ESCP

427[3]

33B

PSCP

4A5[6:4] EA

426[7]

337

Note: SPFG is cleared by writing a binary “1” to this bit position. Writing a “0” is a

NOP.

76543210

SPCP Rsvd Rsvd Rsvd SPC3 SPC2 SPC1 SPC0

0 Selects inverted polarity SCPClk. See Fi

ure 9-2.

1 Selects normal polarity SCPClk.

WARNING: It is illegal to use the value “binary 0000” in this field. The fastest

allowable SCPClk frequency is CClk/8, thus this field must be written greater than zero

(values “0 001” through “1111” are all valid.) The frequencies of SCPClk and CClk (the

system clock) have the following relationship:

SCPClk (Hz.) CClk

4SPCFG 3:0

[]

()

-------------------------------------------------- (Hz.) Note:SPCFG[3:0] = 0 not allowed.=

220 Chapter 9: SCP Interface

SCP Register Descriptions

9.5.2 SCPD: SCP Data Byte

This is both the transmit and receive Data Regis ter for the SCP Interface. During an SCP

bus cycle, the data in this register will be left shifted, most significant bit first, onto

SCPTx. Simultaneously, data bits from SCPRx are left shifted into th e SCP D Register,

and are available to be read by the processor when the cycle is complete. If a data byte

length of less than eight bits is sel ected, then write data must be stored left justified in

SCPD, and read data will arrive right justified. As an example, if the SPD register is

written by soft ware with data 50h, and then a 4 bit SCP bus cycle is performed (sh ifting

left 4 times), shifting in a 1000b (the 1 arrives first) from an external device, then after

the bus cycle is complete, the resultant value in SPD[7:0] will be 08h.

9.5.3 SCPCS: SCP Control and Status

SCPCS[7] - SPST T ( SC P Star t)

This bit is cleared to zero at reset. When set to one, the SCP State Machine star ts runnin g,

and an SCP bus cycle is performed. While the state machine runs, this bit remains set,

and is cleared by hardware at the completion of the SCP bus cycle.

SCPCS[6:4] - SPB2 SPB1 SPB0 (Number of SCP Bits)

The SCP data length (number of bit times in the bus cycle) is selected using this three-bit

field. The number of data bits is given by the binary value in SCPCS[6:4], plus one. Thus

binary 000 specifies a transmission of one bit each direction. Similarly, binary 111

specifies an 8 bit full duplex transmission.

SCPCS[3] - SPFG ( SCP F lag)

This is the interrupt flag for the SCP Interface. This bit gets set by hard ware on the f alling

edge of SPSTT (the end of the bus cycle.). The setting of this flag bit will generate a

maskable processor interrupt. Software can clear this bit by writing binary ‘1’ to the

flag’s bit po sition. For details on this interrupt, see Section 9.4.

76543210

SCPD7 SCPD6 SCPD5 SCPD4 SCPD3 SCPD2 SCPD1 SCPD0

76543210

SPSTT SPB2 SPB1 SPB0 SPFG Rsvd Rsvd SPIDL

Chapter 9: SCP Interface 221

SCP Reg ister De scriptio ns

SCPCS[2:1] - Reserved, must be zero.

SCPCS[0] - SPID L ( SCP Idle St ate )

The Idle state of the SCPTx function is selected with this bit. The state of SCPTx while

the SCP State Machine is not running (between bus cycles) will be identical to the value

stored in the SPIDL bit. See Figure 9-2.

222 Chapter 9: SCP Interface

SCP Register Descriptions

Chapter 10: Interrupts 223

Chapter 10

Interru

ts 10

Contents

10.1 Introduction...... ........................................................................................................................................ 224

10.2 Overview of Native XA Interrupts............................................................................................................224

10.3 XA-SCC Event Interrupts ........................................................................................................................226

10.4 Hi

h Priority Software Interrupts .............................................................................................................228

10.5 SCP Interrupt...........................................................................................................................................229

10.6 Autobaud and V.54/2047 Interrupts ......... ...............................................................................................229

10.7 SCC Interrupts.........................................................................................................................................230

10.8 DMA Interrupts........................................................................................................................................235

10.9 External Interrupt 2 (INT2). ............ ........................................................................................... ...............237

10.10 External Interrupts 0 and 1, and Timers 0 and 1...................................................................................238

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

224 Ch apte r 10 : Inte rrup ts

Introduction

10.1 Introduction

Interrupts in the XA-SCC are implemented using a standard XA Interrupt Controller. A

detailed discussion of the XA family Interrupt Controller can be found in 16-bit

80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25. The Interrupt

Controller accepts and prioritizes both internal and external interrupt requests and

generates a vector number in the interrupt vector table, during the CPU interrupt

acknowledg e cycle. Interrupt nest in g is provided, so t hat a lower priority i nt err upt m a y b e

suspended by a higher priority interrupt.

Interrupt processing by the XA-SCC involves the following steps:

• Interrupt requests are collected by the Interrupt Controller.

• Priority is determined, and the highest priority reque st is presented to the XA-core.

• If the priority level of the interrupt is high er than that of the currently executing code,

the XA-Core responds with an interrupt acknowledge cycle, after execution of the

current instruction is complete.

• The current PSW and PC are stacked. The new PSW and PC are fetched from the

interrupt vector table in low memory.

• The XA-core starts execution at the new PC address.

10.2 Overview of Native XA Interrupts

The XA family architecture defines four types of interrupts:

Table 10-1 Native XA Interrupts

Interrupt Description

Exception Interrupts reflect events of overridin

importance, and are always serviced

immediately when they occur, re

ardless of the priority level of currently

executin

code. Exceptions defined in the XA-SCC’s XA core are: Reset

(External Reset, Watch Do

Reset, Reset Instruction), User RETI,

Divide-by-zero, Stack Overflow, Tr ace, and Breakpoint. Any exception

occurrin

durin

the execution of the Interrupt Service Routine for another

exception, will still be serviced immediately. For details on Exception

Interrupts, see

16-bit 80C51XA Microcontrollers (eXt ended Architecture)

Data Handbook IC25.

Event Interrupts (discussed in this chapter) reflect hardware event s which are less critical,

and they are associated with both on-chip devices and external interrupt

inputs. The priority level of each Event Interrupt is selectable by software,

from 9 - 15. An Event Interrupt is serviced only when it becomes the

hest priority interrupt pendin

, and its priority is hi

her than that of

currently executin

code. For details on XA Event Interrupts see

16-bit

80C51XA Microcontrol lers (eXtended Architecture) Data Handbook IC25.

Chapter 10: Interrupts 225

Overvie w of Na tive XA In terrupts

10.2.1 SFR Bit Addressing Primer

The tables in this chapter list the relevant addresses for the various interrupt flag and

enable bits in the XA-SCC. Some of the bits are in Memory Mapped Registers (MMRs),

and are addressed by their offset from the MMR base address (see Section 2.7 for

details). Some of the bits are in bit addressable Special Function Registers (SFRs). The

following example demonstrates how an SFR bit address is calculated from a given SFR

byte address.

Example: Calculate the SFR bit address of IE0, the flag bit for INT0.

• The SFR byte address for IE0 is 410[1].

• The low 3 bits of th e 10-bit SFR bit address represent the bit position. In this case

“[1]” = 001.

• The next 6 bits of the 10-bit SFR bit address represent the least significant six bits of

the SFR byte address. In this case “10” = 010000.

• The most significant bit of the 10-bit SFR bit address is always 1.

• The SFR bit address is formed by concatenating these three fields in the following

manner: 1 010000 001 → 10 1000 0001 = 281h.

• Each of the foll owing Assembly langu a ge instructions would clear this bit to zero:

CLR IE0

CLR TCON.1

CLR 281

Software Interrupts (not to be confused with the “Hi

h Priority Software Interrupts,” unique to

the XA-SCC, and discussed below) are caused by software settin

interrupt request bit in an SFR. They act just like Event Interrupts, but their

priorities are fixed from 1 - 7. Like Event Interrupt s, a Software Interrupt

will only be serviced when it becomes the hi

hest priority interrupt

pendin

, and its priority is hi

her than that of currently executin

code. For

details on Software Interrupts, s ee

16-bit 80C51XA Microco ntrollers

(eXtended Architecture) Data Handbook IC25.

Trap Interrupts are

enerated by t he execution of the Trap instruction. There are 16 Traps

available, T r ap 0 - Trap 15. A T r ap interrupt will only occur if the T r ap

instruction is executed, so there is no precedence scheme for

simultaneous Traps. For details on Trap Interrupts, see

16-bit 80C51XA

Microcontrollers (eXtended Architecture) Data Handbook IC25.

Table 10-1 Native XA Interrupts (continued)

Interrupt Description

226 Ch apte r 10 : Inte rrup ts

XA-SCC Event Interrupts

10.3 XA-SCC E ven t Interrup ts

The XA-SCC has the following Event Interrupts:

• High Priority Software Interrupts 0 - 3

•SCP Port

• Autobaud and V.54/2047

• SCC “SCC0/1” and “SCC2/3”

• DMA “DMAL” and “DMAH”

• External Interrupt 2

• External Interrupts 0 and 1

• Timers 0 and 1

Event Interrupts must be globally enabled by setting the EA bit to one. The byte address

of the EA bit is SFR 42 6[7], and the bit address is 337. Clearing the EA bit to zero

globally disables all Event Interrupt s .

Tabl e 10-2 lists the Event Interrupts in the XA-SCC. Only the control bits internal to the

XA Interrupt Controller appear in the table. The control bits, which are external to the

Interrupt Controller and internal to the various on-chip peripherals of the XA-SCC, will

be presented in following sections.

The Interrupt Priority Registers, IPA0 through IPA7, are non-bit addressable SFRs. All

Event Interrupt priorities are selected using the appropriate 3-bit fiel d in the Interrupt

Priority Regis ters as follows:

IPAi[6:4] or IPAi[2:0] = 111 - Priority 15 (highest priority)

IPAi[6:4] or IPAi[2:0] = 110 - Priority 14

IPAi[6:4] or IPAi[2:0] = 101 - Priority 13

IPAi[6:4] or IPAi[2:0] = 100 - Priority 12

IPAi[6:4] or IPAi[2:0] = 011 - Priority 11

IPAi[6:4] or IPAi[2:0] = 010 - Priority 10

IPAi[6:4] or IPAi[2:0] = 001 - Priority 9

IPAi[6:4] or IPAi[2:0] = 000 - Priority 0, effectively disables the interrupt

Some Event Interrupt Flag Bits are in MMRs and some are in SFRs, so the prefixes

“MMR” and “SFR” have been included in the Flag Bit column of Table 10-2. All the

Enable Bits are in bit-addressable SFRs, and both their byte and bit addresses are shown.

The Arbitration Rank ing determines which interrupt is serviced first, if more than o ne

interrupt with the same p ri ority occurs simultaneously.

Chapter 10: Interrupts 227

XA-SCC Event Interrupts

Table 10-2 XA-SCC Ev ent Interrupts

Event Interrupt Source Flag Bit

Interrupt

Vector

Address Enable Bit

(SFR)

Priority

Field (SFR) Arb.

Rank

h Priority Software Interrupt 3 HSWR3

MMR 2D0[15] 00BF-00BC EHSWR3

427[7]

33F

PHSWR3

4A7[6:4] 17

h Priority Software Interrupt 2 HSWR2

MMR 2D0[14] 00BB-00B8 EHSWR2

427[6]

33E

PHSWR2

4A7[2:0] 16

h Priority Software Interrupt 1 HSWR1

MMR 2D0[13] 00B7-00B4 EHSWR1

427[5]

33D

PHSWR1

4A6[6:4] 15

h Priority Software Interrupt 0 HSWR0

MMR 2D0[12] 00B3-00B0 EHSWR0

427[4]

33C

PHSWR0

4A6[2:0] 14

SCP Po rt SPFG

SCPCS[3]

MMR 263[3]

00AF-00AC ESCP

427[3]

33B

PSCP

4A5[6:4] 13

Autobaud and V.54/2047 multiple OR from

Autobauds 3-0 &

V.54/2047 A and B

00AB-00A8 EAuto

427[2]

33A

PAutoB

4A5[2:0] 12

SCC “SCC2/3” Interrupt mult iple OR from

SCC2 & SCC3 00A7-00A4 ESC23

427[1]

339

PSC23

4A4[6:4] 11

SCC “SCC0/1” Interrupt multiple OR from

SCC0 & SCC1 00A3-00A0 ESC01

427[0]

338

PSC01

4A4[2:0] 10

DMA “DMAH” Interrupt multiple OR from

DMA 009B- 0098 EDMAH

426[6]

336

PDMAH

4A3[2:0] 8

DMA “DMAL” Interrupt mult iple OR from

DMA 0097-0094 EDMAL

426[5]

335

PDMAL

4A2[6:4] 7

External Interrupt 2

(INT2)IE2

MMR 2D2[0] 0093-0090 EX2

426[4]

334

PX2

4A2[2:0] 6

Timer 1 TF1

SFR 410[7]

287

008F-008C ET1

426[3]

333

PT1

4A1[6:4] 5

External Interrupt 1

(INT1)IE1

SFR 410[3]

283

008B-0088 EX1

426[2]

332

PX1

4A1[2:0] 4

Timer 0 TF0

SFR 410[5]

285

0087-0084 ET0

426[1]

331

PT0

4A0[6:4] 3

External Interrupt 0

(INT0)IE0

SFR 410[1]

281

0083-0080 EX0

426[0]

330

PX0

4A0[2:0] 2

228 Ch apte r 10 : Inte rrup ts

High Priority Software Interrupts

10.4 High Priority Software Interrupts

The XA-SCC’s High Priority Software Interrupts are actually Event Interrupts, and as

such they differ from normal XA Software Interrupts. The normal XA Software

Interrupts 1 - 7 have the fixed priority levels 1 - 7. The High Priority Software Interrupts,

like the other Event Interrupts, can have any priority level from 9 to 15.

The purpose of the High Priority Software Interrupts is similar to that of the normal

Software Interrupts, but they can be prioritized above the other Event Interrupts when

necessary. For a discussion on the use of Software Interrupts in general, see 16-bit

80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.

High Priority Software Interrupts are generated when software writes a ‘1’ to the

appropriate Flag bit in MMR 2D0[15:12], and they are cleared by writing a ‘0’ to the

Flag bit. The portio n of Tab le 1 0-2 relating to the High Priority Software Interrupts is

reproduced below.

Event Interrupt Source Flag Bit

Interrupt

Vector

Address Enable Bit

(SFR)

Priority

Field (SFR) Arb.

Rank

h Priority Software

Interrupt 3 HSWR3

MMR 2D0[15] 00BF-00BC EHSWR3

427[7]

33F

PHSWR3

4A7[6:4] 17

h Priority Software

Interrupt 2 HSWR2

MMR 2D0[14] 00BB-00B8 EHSWR2

427[6]

33E

PHSWR2

4A7[2:0] 16

h Priority Software

Interrupt 1 HSWR1

MMR 2D0[13] 00B7-00B4 EHSWR1

427[5]

33D

PHSWR1

4A6[6:4] 15

h Priority Software

Interrupt 0 HSWR0

MMR 2D0[12] 00B3-00B0 EHSWR0

427[4]

33C

PHSWR0

4A6[2:0] 14

Chapter 10: Interrupts 229

SCP Interrupt

10.5 SCP Interrupt

The porti o n of Table 10-2 rel at ing t o th e SC P i nterrupt is reprodu ced below. The interrupt

Flag bit, called SPFG, is in the SCPCS Memory Mapped Register, specifically SPFG =

SCPCS[3] = MMR 263[3]. The SCP interrupt is cleared by writing a ‘ 1’ (n ot a ‘0 ’) to this

bit. Writing ‘0’ to this bit is a NOP, and does not change the state of the bit.

10.6 Autobaud and V.54/2047 Interrupts

The portion of Table 10-2 relating to the Autobaud and V.54/2047 interrupts is

reproduced below.

There is one interrupt flag for each Autobaud channel, and two interrupt flags for each

V.54/2047 circuit. These interrupt flags, which are all in MMRs, are cleared by writing a

‘1’ (not a ‘0’) to the MMR bit position. They are summarized in Table 10-3.

Table 10-3 Autobaud and V.54/2047 Interrupt Flags

Event Interrupt

Source Flag Bit

Interrupt

Vector

Address Enable Bit

(SFR)

Priority

(SFR) Arb.

Rank

SCP SPFG

SCPCS[3]

MMR 263[3]

00AF-00AC ESCP

427[3]

33B

PSCP

4A5[6:4] 13

Event Interrupt

Source Flag Bit

Interrupt

Vector

Address Enable Bit

(SFR)

Priority

(SFR) Arb.

Rank

Autobaud and V.54/

2047 multiple OR from

Autobauds 3-0 &

V.54/2047 A and B

00AB-00A8 EAuto

427[2]

33A

PAutoB

4A5[2:0] 12

Potential Interrupt Flag Bit and M MR Offset (Hex)

Autobaud 3 ABD3F = BDCS[7] = MMR 272[7]

Autobaud 2 ABD2F = BDCS[6] = MMR 272[6]

Autobaud 1 ABD1F = BDCS[5] = MMR 272[5]

Autobaud 0 ABD0F = BDCS[4] = MMR 272[4]

V.54/2047 B Error Counter VBVFG = VBCS[3] = MMR 248[3]

V.54/2047 B Threshold Counter VBDFG = VBCS[0] = MMR 248[0]

V.54/2047 A Error Counter VAV FG = VACS[3] = MMR 240[3]

V.54/2047 A Threshold Counter VADFG = VACS[0] = MMR 240[0]

230 Ch apte r 10 : Inte rrup ts

SCC Interrupts

10.7 SCC Interrupts

The portion of Table 10-2 relating to SCC interrupts is reproduced below.

The assorted interrupt enable and flag bits, internal to the SCCs, for each individual SCC

interrupt are detailed in Table 10-4 through Ta ble 10-7. Notice th at the External/Status

Interrupts have bo th Ind ivi dual and Group Enable b its. Also notice that each grouped pair

of SCC channels has its own Master Interrupt Enable bit which must be set, in addition to

the EA bit in SFR 426 [7], before an y interrupts from that pair of SCC channels will b e

serviced.

SCC interrupts are cleared differently, depending on the interrupt type:

• Receiver interrupts (Even or Odd Channel Rx IP bits) are cleared by executing a read

of the Rx Data Buffer (RR8). This action must be taken in order to clear the associated

Rx IP bit.

• Transmitter interrupts (Even or Odd Channel Tx IP bits) are cleared by issuing the

“Reset Tx Interrupt Pending” command, WR0[5:3] = 101.

• External/Status Interrupts (Even or Odd Channel External/Status IP bits) are cleared by

issuing the “Reset Ex ternal/Status Interrupts” command, WR0[5:3] = 010.

Event Interrupt

Source Flag Bit

Interr upt

Vector

Address Enable Bit

(SFR)

Priority

Field (SFR) Arb.

Rank

SCC “SCC2/3”

Interrupt multiple OR from

SCC2 & SCC3 00A7-00A4 ESC23

427[1]

339

PSC23

4A4[6:4] 11

SCC “SCC0/1”

Interrupt multiple OR from

SCC0 & SCC1 00A3-00A0 ESC01

427[0]

338

PSC01

4A4[2:0] 10

Chapter 10: Interrupts 231

SCC Interrupts

Table 10-4 SCC0 Interrupts

Potential SCC0

Interrupt

Individual

Enable Bit

MMR Hex

Offset

Source Bit

MMR Hex Offset

Group Enable

Bit(s)

MMR Hex Offset

Group Flag Bit

MMR Hex Offset

Master Enable

Bit

MMR Hex Offset

Rx Character

Available - RR0[0]

820[0]

WR1[4:3]

802[4:3]

Even Channel Rx

RR3[5]

826[5]

SCC0/1 Master

Interrupt Enable

WR9[3]

812[3]

SDLC EOF - RR1[7]

822[7]

CRC/

Framin

Error - RR1[6]

822[6]

Rx Overrun - RR1[5]

822[5]

Parity Error WR1[2]

802[2] RR1[4]

822[4]

Tx Buffer Empty See WR1[1] RR0[2]

820[2] Tx Interrupt Enable

WR1[1]

802[1]

Even Channel Tx

RR3[4]

826[4]

Break/

Abort Break/

Abort IE

WR15[7]

81E[7]

RR0[7]

820[7]

Master External/

Status Interrupt

Enable

WR1[0]

802[0]

Even Channel

External/Status IP

RR3[3]

826[3]

Tx Underrun/

EOM Tx Underrun/

EOM IE

WR15[6]

81E[6]

RR0[6]

820[6]

CTS CTS IE

WR15[5]

81E[5]

RR0[5]

820[5]

SYNC/

HUNT SYNC/

HUNT IE

WR15[4]

81E[4]

RR0[4]

820[4]

DCD DCD IE

WR15[3]

81E[3]

RR0[3]

820[3]

Zero Count Zero Count

WR15[1]

81E[1]

RR0[1]

820[1]

232 Ch apte r 10 : Inte rrup ts

SCC Interrupts

Table 10-5 SCC1 Interrupts

Potential SCC1

Interrupt

Individual

Enable Bit

MMR Hex

Offset

Source Bit

MMR Hex

Offset

Group Enable

Bit(s)

MMR Hex

Offset

Group Flag Bit

MMR Hex Offset

Master Enable Bit

MMR Hex Offset

Rx Character

Available - RR0[0]

860[0]

WR1[4:3]

842[4:3]

Odd Channel Rx IP

RR3[2]

866[2]

SCC0/1 Mas ter

Interrupt Enable

WR9[3]

852[3]

SDLC EOF - RR1[7]

862[7]

CRC/

Framin

Error - RR1[6]

862[6]

Rx Overrun - RR1[5]

862[5]

Parity Error WR1[2]

842[2] RR1[4]

862[4]

Tx Buffer Empty See WR1[1] RR0[2]

860[2] Tx Interrupt

Enable

WR1[1]

842[1]

Odd Channel Tx IP

RR3[1]

866[1]

Break/

Abort Break/

Abort IE

WR15[7]

85E[7]

RR0[7]

860[7]

Master

External/

Status Interrupt

Enable

WR1[0]

842[0]

Odd Channel

External/Status IP

RR3[0]

866[0]

Tx Underrun/

EOM Tx Underrun/

EOM IE

WR15[6]

85E[6]

RR0[6]

860[6] Odd Channel

External/Status IP

RR3[0]

866[0]

CTS CTS IE

WR15[5]

85E[5]

RR0[5]

860[5] Odd Channel

External/Status IP

RR3[0]

866[0]

SYNC/

HUNT SYNC/

HUNT IE

WR15[4]

85E[4]

RR0[4]

860[4] Odd Channel

External/Status IP

RR3[0]

866[0]

DCD DCD IE

WR15[3]

85E[3]

RR0[3]

860[3] Odd Channel

External/Status IP

RR3[0]

866[0]

Zero Count Zero Count

WR15[1]

85E[1]

RR0[1]

860[1] Odd Channel

External/Status IP

RR3[0]

866[0]

Chapter 10: Interrupts 233

SCC Interrupts

Table 10-6 SCC2 Interrupts

Potential SCC2

Interrupt

Individual

Enable Bit

MMR Hex

Offset

Source Bit

MMR Hex

Offset

Group Enable

Bit(s)

MMR Hex

Offset

Group Flag Bit

MMR Hex Offset

Master Enable Bit

MMR Hex Offset

Rx Character

Available -RR0[0]

8A0[0]

WR1[4:3]

882[4:3]

Even Channel Rx

RR3[5]

8A6[5]

SCC2/3 Mas ter

Interrupt Enable

WR9[3]

892[3]

SDLC EOF -RR1[7]

8A2[7]

CRC/

Framin

Error -RR1[6]

8A2[6]

Rx Overrun -RR1[5]

8A2[5]

Parity Error WR1[2]

882[2] RR1[4]

8A2[4]

Tx Buffer Empty See WR1[1] RR0[2]

8A0[2] Tx Interrupt

Enable

WR1[1]

882[1]

Even Channel Tx

RR3[4]

8A6[4]

Break/

Abort Break/

Abort IE

WR15[7]

89E[7]

RR0[7]

8A0[7]

Master

External/

Status Interrupt

Enable

WR1[0]

882[0]

Even Channel

External/Status IP

RR3[3]

8A6[3]

Tx Underrun/

EOM Tx Underrun/

EOM IE

WR15[6]

89E[6]

RR0[6]

8A0[6]

CTS CTS IE

WR15[5]

89E[5]

RR0[5]

8A0[5]

SYNC/

HUNT SYNC/

HUNT IE

WR15[4]

89E[4]

RR0[4]

8A0[4]

DCD DCD IE

WR15[3]

89E[3]

RR0[3]

8A0[3]

Zero Count Zero Count

WR15[1]

89E[1]

RR0[1]

8A0[1]

234 Ch apte r 10 : Inte rrup ts

SCC Interrupts

Table 10-7 SCC3 Interrupts

Potential SCC2

Interrupt

Individual

Enable Bit

MMR Hex

Offset

Source Bit

MMR Hex

Offset

Group Enable

Bit(s)

MMR Hex

Offset

Group Flag Bit

MMR Hex Offset

Master Enable Bit

MMR Hex Offset

Rx Character

Available -RR0[0]

8E0[0]

WR1[4:3]

8C2[4:3]

Even Channel Rx

RR3[5]

8E6[5]

SCC2/3 Mas ter

Interrupt Enable

WR9[3]

8D2[3]

SDLC EOF -RR1[7]

8E2[7]

CRC/

Framin

Error -RR1[6]

8E2[6]

Rx Overrun -RR1[5]

8E2[5]

Parity Error WR1[2]

8C2[2] RR1[4]

8E2[4]

Tx Buffer Empty See WR1[1] RR0[2]

8E0[2] Tx Interrupt

Enable

WR1[1]

8C2[1]

Even Channel Tx

RR3[4]

8E6[4]

Break/

Abort Break/

Abort IE

WR15[7]

8DE[7]

RR0[7]

8E0[7]

Master

External/

Status Interrupt

Enable

WR1[0]

8C2[0]

Even Channel

External/Status IP

RR3[3]

8E6[3]

Tx Underrun/

EOM Tx Underrun/

EOM IE

WR15[6]

8DE[6]

RR0[6]

8E0[6]

CTS CTS IE

WR15[5]

8DE[5]

RR0[5]

8E0[5]

SYNC/

HUNT SYNC/

HUNT IE

WR15[4]

8DE[4]

RR0[4]

8E0[4]

DCD DCD IE

WR15[3]

8DE[3]

RR0[3]

8E0[3]

Zero Count Zero Count

WR15[1]

8DE[1]

RR0[1]

8E0[1]

Chapter 10: Interrupts 235

DMA Interrupts

10.8 DMA Int errupts

The portion of Table 10-2 relating to DMA interrupts is reproduced below.

The interrupt enable and flag bits for all DMA interrupts, internal to the DMA Controller,

are detailed in Table 10-8 through Table 10-11.

• All MCIP Interrupts go to “DMAH,” and are enabled by setting the MCIPEnable bit in

the associated SCC channel.

• All Rx Character Time Out Interrupts go to “DMAL,” and are enabled by writing any

non-zero value to the Rx Character Time Out Register (RxCTOR) while in

Asynchronous mode.

• Standard Rx and Tx In te rrup ts are eith er enab led and steered to “DMAH,” enabled an d

steered to “DMAL,” or disabled using the two-bit field in DMA Control[6:5] as

follows:

• DMA interrupts are cleared by writing a ‘1’ (not a ‘0’) to the appropriate bit position in

the Global DMA Interrupt Register.

Event Interrupt

Source Flag Bit

Interrupt

Vector

Address Enable Bit (SFR)

Priority

Fiel d (SF R ) Arb.

Rank

DMA “D MAH”

Interrupt multiple OR

from DMA 009B- 0098 EDMAH

426[6]

336

PDMAH

4A3[2:0] 8

DMA “D MAL”

Interrupt multiple OR

from DMA 0097-0094 EDMAL

426[5]

335

PDMAL

4A2[6:4] 7

00 Disabled

01 Reserved

10 Enabled and steered to “DMAL”

11 E nabled and steered to “DMAH”

236 Ch apte r 10 : Inte rrup ts

DMA Interrupts

Table 10-8 DMA 0 Interrupts

Table 10-9 DMA 1 Interrupts

DMA 0 Interrupt Enable Bit(s) Flag bit

MCIP

(Match Char) M CIPEnable in WR1[5]

of SCC0

MMR 802[5]

Global DMA

Interrupt[12]

MMR 210[12]

Rx DMA Control[6:5]

MMR 100[6:5] Global DMA

Interrupt[0]

MMR 210[0]

Tx DMA Control[6:5]

MMR 100[6:5] Global DMA

Interrupt[8]

MMR 210[8]

Rx Char Time Out RxCTOR

MMR 200 Global DMA

Interrupt[4]

MMR 210[4]

DMA 1 Interrupt Enable Bit(s) Flag bit

MCIP

(Match Char) M CIPEnable in WR1[5]

of SCC1

MMR 842[5]

Global DMA

Interrupt[13]

MMR 210[13]

Rx DMA Control[6:5]

MMR 110[6:5] Global DMA

Interrupt[1]

MMR 210[1]

Tx DMA Control[6:5]

MMR 110[6:5] Global DMA

Interrupt[9]

MMR 210[9]

Rx Char Time Out RxCTOR

MMR 202 Global DMA

Interrupt[5]

MMR 210[5]

Chapter 10: Interrupts 237

External Interrupt 2 (INT2)

Table 10-10 DMA 2 Interrupts

Table 10-11 DMA 3 Interrupts

10.9 External Interrup t 2 ( INT2)

The portion of Table 10-2 relating to INT2 is reproduced below.

DMA 2 Interrupt Enable Bit(s) Flag bit

MCIP

(Match Char) M CIPEnable in WR1[5]

of SCC2

MMR 882[5]

Global DMA

Interrupt[14]

MMR 210[14]

Rx DMA Control[6:5]

MMR 120[6:5] Global DMA

Interrupt[2]

MMR 210[2]

Tx DMA Control[6:5]

MMR 120[6:5] Global DMA

Interrupt[10]

MMR 210[10]

Rx Char Time Out RxCTOR

MMR 204 Global DMA

Interrupt[6]

MMR 210[6]

DMA 3 Interrupt Enable Bit(s) Flag bit

MCIP

(Match Char) M CIPEnable in WR1[5]

of SCC3

MMR 8C2[5]

Global DMA

Interrupt[15]

MMR 210[15]

Rx DMA Control[6:5]

MMR 130[6:5] Global DMA

Interrupt[3]

MMR 210[3]

Tx DMA Control[6:5]

MMR 130[6:5] Global DMA

Interrupt[11]

MMR 210[11]

Rx Char Time Out RxCTOR

MMR 206 Global DMA

Interrupt[7]

MMR 210[7]

Event Interrupt Source Flag Bit

Interrupt

Vector

Address Enable Bit

(SFR)

Priority

Field (SFR) Arb.

Rank

External Interrupt 2

(INT2)IE2

MMR 2D2[0]

XInt2[0]

0093-0090 EX2

426[4]

334

PX2

4A2[2:0] 6

238 Ch apte r 10 : Inte rrup ts

External Interrupts 0 and 1, and Timers 0 and 1

External Interrupt 2 (INT2) differs slightly from the standard XA External Interrupts 1

and 0. INT2 has two modes, Level Sensitive mode and Edge Triggered mode, which are

selected using bit[1 ] of the External Interrupt 2 Control Register (XInt2[1]).

• In Level Sensitive mode, IE2 (the INT2 Flag bit) reports the current (inverted) state of

CD1_INT2 (Pin 78). In this mode, the interrupt is cleared when the external device

negate s INT2. Level Sensitive mode is selected by clearing XInt2[1] to zero.

• In Edge Triggered mod e, th e f all i ng edge of CD1_INT2 (Pin 78) latches a ‘1’ into IE2.

In this mode, the interrupt is cleared by writing a ‘1’ (not a ‘0’) to IE2. Edge Triggered

mode is selected by s e tting XInt2[1] to one.

Notice that, unlike INT1 and INT0, the INT2 Flag bit resides in an MMR (XInt2[0]),

while the Enable bit reside s in an SFR (426[4] = 334) as usual.

10.10 External Interrupts 0 and 1, and Timers 0 and 1

The portion of Table 10-2 relating to th e INT0, INT1, Timer 0, and Timer 1 interrupts is

reproduced below.

• In order to use INT1, Pin 67 (P3.7_TRx C1_INT1) must be configured as an input

using P3CFGB[7]P3CF GA[7] = 10 . Se e Chapter 11, “XA- SCC Pins,” for details.

For details on the use of these interrupts, see 16-bit 80C51 XA Mi crocontrollers (eXtende d

Architecture) Data Handbook IC25.

Event Interrupt Source Flag Bit

Interrupt

Vector

Address Enable Bit

(SFR)

Priority

Fiel d (SF R ) Arb.

Rank

Timer 1 TF1

SFR 410[7]

287

008F-008C ET1

426[3]

333

PT1

4A1[6:4] 5

External Interrupt 1

(INT1)IE1

SFR 410[3]

283

008B-0088 EX1

426[2]

332

PX1

4A1[2:0] 4

Timer 0 TF0

SFR 410[5]

285

0087-0084 ET0

426[1]

331

PT0

4A0[6:4] 3

External Interrupt 0

(INT0)IE0

SFR 410[1]

281

0083-0080 EX0

426[0]

330

PX0

4A0[2:0] 2

Chapter 10: Interrupts 239

External Interrupts 0 and 1, and Timers 0 and 1

Figure 10-1 XA-SCC Event Interrupt Structure

"DMAH"

"DMAL"

"SCP"

SCP Interface

CTS0 92*

"SCC0/1"

"SCC2/3"

"Autobaud &

V.54/2047"

"EA"

Interrupt

Processor

"External Interrupt 2"

CD0 93*

CTS1 64*

CD1_INT2 78*

*Pin must be configured

as an input in order to

use interrupt.

CTS2 73*

CD2 72*

CTS3 85*

CD3 84*

INT0 79

INT1 67*

V.54/2047

(Units A & B)

SPFG

"External Interrupt 0"

"External Interrupt 1"

INT2

"Timer0"

Timer0TF0

"EDMAH"

"EDMAL"

"ESC01"

"EX2"

"ESC23"

"EX0"

"EX1"

"EAuto"

"ESCP"

"ET0"

"ET1"

"EHSWR" 3-0

"HSWR" 3-0 = Hi-Priority Software Interrupts

Pin Mux Control Register

"Timer1"

Timer1

Bitwise

AND

TF1

DMA

Interrupts

XA Interrupt Controller

Autobauds

3-0

SCC0/

SCC1

Interrupts

SCC2/

SCC3

Interrupts

240 Ch apte r 10 : Inte rrup ts

External Interrupts 0 and 1, and Timers 0 and 1

Table 10-12 GPI/O Configurations for External Event Interrupts

Chosen

Function Description Direction CFGB/A Reg bits GPI/O P ort Output Latch

Pin 92 CTS0 Clear to Send (SCC0) Input P0CFGB/A[2] = 1/0 P0[2] Output Latch = don’t care

Pin 93 CD0 Carrier Detect (SCC0) Input P0CFGB/A[3] = 1/0 P0[3] Output Latch = don’t care

Pin 64 CTS1 Clear to Send (SCC1) Input P3CF GB/A[ 4] = 1/0 P3[4] Output Latch = don’t care

Pin 78 CD1 Carrier Detect (SCC1) Not a GPI/O pin

Pin 73 CTS2 Clear to Send (SCC2) Input P1CF GB/A[ 5] = 1/0 P1[5] Output Latch = don’t care

Pin 72 CD2 Carrier Detect (SCC2) Input P 1CFGB/A[4] = 1/0 P1[4] Output Latch = don’t care

Pin 85 CTS3 Clear to Send (SCC3) Input P2CF GB/A[ 5] = 1/0 P2[5] Output Latch = don’t care

Pin 84 CD3 Carrier Detect (SCC3) Input P2CFGB/A[4] = 1/0 P2[4] Output Latch = don’t care

Pin 79 INT0 External Interrupt 0 Not a multifunction pin

Pin 67 Int1 External Interrupt 1 Input P 3CFGB/A[7] = 1/0 P3[7] Output Latch = don’t care

Chapter 11: XA-SCC Pins 241

Chapter 11

XA-SCC Pins 11

Contents

11.1 Introduction...... ........................................................................................................................................ 242

11.2 XA-SCC Pin Si

nals and Functions........................................................................................................242

11.3 Pin Groupin

s By Function......................... ..................... ............................... ..................... ....................244

11.4 Multifunction Pins....................................................................................................................................247

11.5 Multifunction Pin Schematics ..................................................................................................................252

11.6 XA-SCC Pinout ........................................................................................................................................287

DRAM

Controller

and MIF 8 x DMA

V.54/2047

4 x SCC

Autobaud

IDL

Interface

SCP

Interface

Ports

Function

Mux

XA-SCC

CPU

Timers

Interrupts External

components

such as:

Physical I/F,

U-Chip,

S/T,

RS-232,

etc.

External

components

such as:

DRAM,

SRAM,

Flash,

ROM,

I/O Ports,

etc.

242 Chapter 11: XA-SCC Pins

Introduction

11.1 Introduction

This chapter describes the signals and functions available on the XA-SCC 100-pin LQFP

package. A brief definition of all XA-SCC pin signals and functions appears in Section

11.2. Pin groupings by function, for two typical XA-SCC applications, are presented in

Section 11.3. Multifunction pins, GPI/O Ports, and pin programming are the subjects of

Sections 11.4 through 11.5. The pinou t for the 100 -pin LQFP XA-SCC app ears in Section

11.6.

11.2 XA-SCC Pin Signals and Functions

Table 11-1 XA-SCC Pin Signals and Functions

Function Name Des cription

A19 - A0 (a22 - a0) Address Bus Durin

the CAS portion of DRAM cycles, various

patterns of a22-a1 are time-multiplexed onto pins

A17-A7. Thus, DRAM banks of 8 MBytes are

supported. a23 affects CS. Pins 24 - 21, 18 - 3.

BHE, BLE Byte Hi

h Enable, Byte Low

Enable Bus Strobes. Pins 53, 54.

BRG3 - BRG0 Baud Rate Generator BRG outputs from SCC3 - SCC0. Pins 87, 75, 63,

90.

CASH, CASL Column Address Strobes

(Hi

h and Low) CAS for DRAM cycles. Pins 53, 54.

CD3 - CD0 Carrier Detect CD inputs to SCC3 - SCC0. Pins 84, 72, 78, 93.

ClkOut Clock Output Same frequency as XTALIN. Pin 45.

ComClk Common Communications Clock Optional clock input to all 4 SCC’s. Pin 83.

CS5 - CS0 Chip Select CS output to SRAM and other bus slaves. Pins 57,

56, 46 - 49.

CTS3 - CTS0 Clear To Send CTS inputs to SCC3 - SCC0. Pins 85, 73, 64, 92.

D15 - D0 Data Bus Pins 42 - 30, 27 - 25.

Int2 - Int0 External Interrupts Ex ternal interrupt inputs 2 - 0. Pins 78, 67, 79.

L1Clk, L1GR, L1RQ,

L1RxD, L1SY1, L1TxD IDL Bus Si

nals Clock, Grant, Request, Receive Data, Sync Input ,

Transmit Data. Pins 95, 92, 91, 97, 93, 96

OE Output Enable Bus strobe,

oes active durin

reads from external

memory. Pin51

P3.7 - P0.0 GPI/O (General Purpose I/O) Port

bits Pins 67 - 63, 58 - 56, 87 - 80, 75 - 68, 97 - 90

Chapter 11: XA-SCC Pins 243

XA-SCC Pi n Signals and Fu nctions

RAS5 - RAS1 Row Address Strobes RAS for Memory Banks 5 - 1 if DRAM. Pins 57, 56,

46 - 48

ResetIn Reset In External reset input. Pin 55

ResetOut Reset Out Goes active durin

an internal reset. Pin 58.

RTS3 - RTS0 Request to Send RTS outputs from SCC3 - SCC0. Pins 86, 74, 57,

91.

RTClk3 - RTClk0 Receive or Transmit Clock Clock inputs to SCC3 - SCC0, can be routed to

receiver or transmitter or both. Pins 82, 70, 56, 95.

RxD3 - RxD0 Receive Data RxD inputs to SCC3 - SCC0. Pins 80, 68, 65, 97.

SCPClk, SCPRx, SCPTx SCP Interf ace si

nals Clock, Receive Data, Transmit Data. Pins 98, 100,

99.

SDS2 - SDS1 Serial Data Strobes Control si

nal outputs from IDL Interface. Pins 90,

94.

Size8 Bus Size Determines the Data Bus width durin

Reset. 1 =

8-bit, 0 = 16-bit. Pin 52.

Sync3 - Sync0 Sync External Sync inputs, or Sync outputs, for SCC3 -

SCC0. Pins 87, 75, 63, 90

Timer1 - Timer 0 Timer 1, 0 Inputs or outputs, dependin

on the mode of the

timers. Pins 63, 58.

TRClk3 - TRClk0 Tr ansmi t or Receive Clock Clock inputs to SCC3 - SCC0, can be routed to

receiver or transmitter or both. Pins 83, 71, 67, 94

TxD3 - TxD0 Transmi t Data TxD outputs from SCC3 - SCC0. Pins 81, 69, 66,

96.

VDD, VSS Power VDD = +Volta

e. Pins 2, 20, 29, 43, 62, 77, 89. VSS

= GND. Pins 1, 19, 28, 44, 59, 76, 88.

WAIT WAIT External (Bus) Wait input. Pin 52.

WE Write Enable Bus strobe,

oes active durin

writes to external

memory. Pin 50.

XTALIN, XTALOUT Crystal In, Out Crystal oscillator connections. Pins 60, 61.

Table 11-1 XA-SCC Pin Signals and Functions (continued)

Function Name Des cription

244 Chapter 11: XA-SCC Pins

Pin Grouping s By Funct ion

11.3 Pin Gr oupings By Func tion

There are four 8-bit wide I/O Ports in the XA-SCC, which are the subject of Section

11.4.1. In general, each port shares a set of eight pins with one of the four SCCs (the

exception being Port 0). Inspection of the XA-SCC Pinout in Section 11.6 reveals the

following correspondence between SCCs and GPI/O Ports:

• SCC0 and Port 0 (plus the eight IDL bus signals) share Pins 90 - 97, except for P0.6

and P0.7 which are shared with the SCP Interface on Pins 99 - 100.

• SCC1 and Port 3 (plus other functions) share pins 56 - 58 and 63 - 67, except for CD1

which is shared with Int2 on Pin 78.

• SCC2 and Port 1 share Pins 68 - 75.

• SCC3 and Port 2 share Pins 80 - 87.

An unused NMSI interf ace sig nal on on e of the SCCs frees up a GPI/O pin, un less the pi n

is bein g used by another functi on . The refore, an unused SCC can free u p as m any as ei g ht

GPI/O pins.

In this section, we look at the functional groupings of XA-SCC pins for two common

configu rations : A typic al ISDN config uration , and a conf igurati on usin g four in dependen t

serial channels.

Chapter 11: XA-SCC Pins 245

Pin Group ings By Functio n

11.3.1 Functional Pin Groups for Typical ISDN Configuration

Figure 11-1 Typical ISDN: SCC0 - SCC2 using IDL, SCC3 using NMSI interface

Figure 11-1 shows the functional groupings of XA-SCC pins in a typical ISDN

configuration. For this example SCC0, SCC1, and SCC2 are using the IDL Interface, and

SCC3 is using a NMSI interface. Also, the SCP Interface is being used to communicate

with the physical layer device (U-Chip, etc.), and possibly other off-chip devices.

It is important to note that in any application where both the full complement of 8 IDL

signals (including SDS1 and SDS2) and SCP are being used, no GPI/O using Port 0 is

possible. The 8 GPI/O port bits P0.0 - P0.7 each share a pin with either an IDL signal or

an SCP signal.

/SCP Interface

SCPTx, SCPRx, SCPClk

/CS_RAS (0 - 5)

XA-SCC

WAIT

/SCC0 / Port 0 / IDL

L1TxD, L1RxD, L1Clk,

L1SY1, L1RQ, L1GR,

SDS1, SDS2

/BLE_CASL, BHE_CASH

/SCC1 / Port 3 / Other

P3.0, P3.1, P3.3 - P3.7

/WE, OE

ResetOut

/SCC2 / Port 1

P1.0 - P1.7

A19 - A0 (A22 - A20 muxed)

/SCC3 / Port 2

TxD3, RxD3, RTS3, CTS3, 4

P2.2, P2.3, P2.4, P2.7

ClkOut

XTALIN

Int0

XTALOUT

D15 - D0

ResetIn

246 Chapter 11: XA-SCC Pins

Pin Grouping s By Funct ion

However, because IDL is being used, all 8 pins from both the “SCC1/Port 3/Other” and

the “SCC2/Port 1” groups are available for GPI/O (or other) functions. In this example, 7

pins from the “SCC1/Port 3/Other” group are used for GPI/O (P3.0, P3.1, and P3.3 -

P3.7) while one pin is used for the “other” function ResetOut. Additionally, all 8 pins

from the “SCC2/Port 1” group are being used for GPI/O.

From the “SCC3/Port 2” group, four pins are being used by SCC3 (two pins for data, and

2 for control) and four pins are being used for GPI/O (P2.2 - P2.4, and P2.7).

Notice that each of the signals shown on the right side of Figure 11-1 appear on a pin

dedicated to that function only.

11.3.2 Functional Pin Groups for 4 Independent Serial Channels

Figure 11-2 Four Independent Serial Channels

Figure 11-2 shows the functional groupings of XA-SCC pins in a typical configuration

with four independent serial channels. Note that SCC1 is using all seven standard NMSI

interface signals. Again the SCP Interface is being used, therefore port bits P0.6 and P0.7

are not available for GPI/O.

/SCP Interface

SCPTx, SCPRx, SCPClk 5

/CS_RAS (0 - 5)

XA-SCC

CD1_Int2

CD1

WAIT

/SCC0 / Port 0 / IDL

TxD0, RxD0, RTS0,

CTS0, CD0

/BLE_CASL, BHE_CASH

P0.0, P0.4, P0.5

/SCC1 / Port 3 / Other

TxD1, RxD1, RTS1, CTS1,

TRClk1, RTClk1, Sync1

/WE, OE

Timer 0

/SCC2 / Port 1

TxD2, RxD2, RTS2,

CTS2, CD2

A19 - A0 (A22 - A20 muxed)

P1.2, P1.3, P1.7

/SCC3 / Port 2

TxD3, RxD3, RTS3, CTS3, 4

P2.2, P2.4, P2.7

ClkOut

XTALIN

Int0

XTALOUT

D15 - D0

ResetIn

Chapter 11: XA-SCC Pins 247

Multifunction Pins

From both the “SCC0/Port 0/IDL” and the “SCC2/Port 1” groups, five pins are being

used by the associated SCC (two for data, and three for control) and three pins are being

used for GP I/O.

Seven pins from the “SCC1/Port3/Other” group are being used by SCC1 while one pin is

being used by the “other” function Timer 0. Additionall y, SCC1 is using the CD1 control

input on th e pin it shares with Int2.

From the “SCC3/Port 2” group, four pins are being used by SCC3 (two for data, and two

for c ontrol), and four pins are being used for GPI/O.

As in the previous example, each of the signals shown on the right side of Figure 11-2

appear on a pin dedicated to that function only.

11.4 Multifunction Pins

The XA-SCC has 36 multifunction pins which are shared by various functional blocks on

the device. The official name of a multifunction pin consists of all the functions available

on the pin, separated by underscore characters (for example, Pin 94 is called

P0.4_TRClk0_SDS1). Multif unction pins must be properly programmed before a desired

pin function will operate correctly. The following sections explain multifunction pin

programming, and contain logic diagrams for each XA-SCC multifunction pin. The

pinout for the 100-pin PQFP XA-SCC appears in Section 11 .6.

11.4.1 Review of XA I/O Ports

On the XA-SCC, thirty two of the thirty six multifunction pins provide access to the

onboard XA-G3 processor’s I/O Ports. These ports, sometimes called GPI/O (General

Purpose I/O) Ports, provide general purpose input and output functions for interfacing

with external devices. A short review of XA I/O Ports appears in the following sections.

For more detail, see 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data

Handbook IC 25.

11.4.2 I/O Port Naming Conventions

There are four eight-bit wide I/O Ports on the XA-SCC, which are accessed through

bit-addressable SFRs. The names of the port SFRs are those which are normally used in

assembler source code: P0 - P3. Individual bits in the port SFRs are also named using the

convention of assembler code. For example Bit[7] of Port 2 is named P2[7]. A quick

glance at Appendix C sh ows that t he SFR Address of Por t 2 is 432h, so the Byte Address

of P2[7] is 432[7], and the Bit Address is 397h.

248 Chapter 11: XA-SCC Pins

Multif un c ti on Pin s

11.4.3 I/O Port Configurati ons

The configuration of each I/O Port bit can be independently selected. There are two

configuration register s for each 8 -bit wide po rt, and the bit values stored in these register s

control the configuration of the individual port bits. For example, Port 0 is controlled by

the two configuration registers P0CFGB and P0CFGA, and Port 3 is controlled by the

registers P3CFGB and P3CFGA.

The configuration of an individual one-bit wide I/O port is determined by the binary

number formed with the corresponding bits in the port’s configuration regis ters. For

example, the configuration of I/O Port 1 Bit[6] (the P1.6 function of Pin 7 4) is controlled

by the binary number formed from the concatenation of P1CFGB[6] with P1CFGA[6].

Similarly, the configuration of Port 3 Bit[2] (the P3.2 function of Pin 58) is controlled by

the concatenation of P3CFGB[2] with P3CFGA[2].

Please note that the following shorthan d notation will be used th roughout this chapter,

where i = 0 - 3 and n = 0 - 7:

PiCFGB[n] PiCFGA[n] = 00 → PiCFGB/A[n] = 0/0

PiCFGB[n] PiCFGA[n] = 01 → PiCFGB/A[n] = 0/1

PiCFGB[n] PiCFGA[n] = 10 → PiCFGB/A[n] = 1/0

PiCFGB[n] PiCFGA[n] = 11 → PiCFGB/A[n] = 1/1

The port control bit combinations and the associated port configuration modes are shown

in Table 11 -2.

Table 11-2 I/O Port Configuration Modes

I/O Mode PiCFGB[n] PiCFGA[n] Comments

Input 1 0 Output driver is in the hi

h impedance

state.

Push-Pull Output 1 1 Normal output confi

uration.

Open Drain Output 0 0 Alternate output confi

uration.

Quasi-Bidirectional I/O 0 1 Default state from reset.

For more information about Quasi-bidirectional and Open Drain functions, see the

XA User Guide,

Section 3 of

16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25

Chapter 11: XA-SCC Pins 249

Multifunction Pins

11.4.4 Multifunction Pin Programming Example

Figure 11-3 Multifunction Pin Example, using Pin 94

Figure 11-3 shows Pin 94 (P0.4_TRClk0_SDS1), one of the XA-SCC multifunction pins.

The following example describes in detail the programming of Pin 94 to activate each of

its functions, and is typical of multifunction pin programming on the XA-SCC. The

following three functions can be activated on Pin 94:

Output Path

Pin 94 is configured as an output (Pu sh-Pull) by setting P0CFGB[ 4] = P0CFGA[4] = 1

(P0CFGB/A[4] = 1/1). The output path through the pin driver first passes through the

AND gate. Hence, the unused input to the AND gate m us t be set to logic ‘1’ to enable

the other AND gate input.

• To use P0[4] as an output, turn the IDL Interface “Off” by writing 111 to MSI

Control[2:0]. The state “ID LO ff” puts a ‘1’ on the lower inpu t to the AND gate, so the

state of Pin 94 will be controlled by the state of the P0[4] output latch.

• To enable the SDS1 output from the IDL Interface to appear on Pin 94, write ‘1’ to

P0[4] with the IDL Interface “On”. The state “IDLOn” (achieved with MSI

Control[2:0] ≠ 111) puts a ‘0’ on the lower input to the OR gate, enabling the SDS1

function to use the OR gate. For details about IDL, see Chapter 8, “IDL Interface.”

Function Description

P0.4 I/O Port 0 Bit[4], which can be confi

ured as either an input or an output.

TRClk0 An external clock input to SCC0.

SDS1 Synchronous Data Strobe 1 output si

nal from the IDL Interface.

TRClk

P0CFGB[4]

P0CFGA[4]

P0[4] Output Latch

P0.4_TRClk0_SDS1

PIN 94

Border of

XA-SCC Chip

PAD LOGIC SCC0

To P0[4] DataIn

SDS1

IDLOff*

*MSI Control[2:0] = 111 is IDLOff

IDL

250 Chapter 11: XA-SCC Pins

Multif un c ti on Pin s

Input Path

Pin 94 is configured as an input by writing P0CFGB/A[4] = 1/0. This puts the output

driver into its high impedance state, allowing the external device to drive the pin. The

signal on Pin 94 is then available to SCC0 on the TR Clk input and to the CPU as the

P0[4] input. SCC0 may or may not be configured to use the external clock TRClk0, and

the processor can read the state of Pin 94 by executing a read to P0[4].

The programming for Pin 94 is summarized in Table 11-3. All CPU I/O Port addresses

can be found in the SFR Address Tables in Appendix C.

Table 11-3 Programming Pin 94

11.4.5 Pin Multiplexing Control Register (PMCR), MMR 2D0h

Figure 11-4 Pin Mux Control Register (PMCR)

Chosen

Function Description Direction P0CFGB/A[4] Output

Latch P0[4] IDL

TRClk0 TRClk to SCC0 Input 1/0 X Off

P0.4 Input GPI/O Input Input 1/0 X SDS1 not

available for IDL

if input pin

P0.4 Output GPI/O Output Output 1/1 Output Data Off

SDS1 Output from IDL

Interface Output 1/1 1 On

P0.4 I/O GPI/O

Quasi-Bidirectional I/O 0/1 Output Data Off

P0.4 Output GPI/O Open Drain Output 0/0 Output Data Off

Note: MSI Control[2:0] = 111 is IDLOff, and MSI Control[2:0] ≠ 111 is IDLOn.

09876543210

RTS0_P0.1

RTS1_P3.1

RTS2_P1.6

RTS3_P2.6

SC1_NMSI_P3.6

SC2_NMSI_P1.1

HSWR0

HSWR1

HSWR2

HSWR3

Chapter 11: XA-SCC Pins 251

Multifunction Pins

The 16-bit Pin Multiplexing Control Register (PMCR) is shown in Figure 11-4. The high

four bits of the Pin Mux Co ntrol Register are the High Priority Software Interrupt Flags.

For details on th e High Priority Software Interrupts, see Section 10.4 in C hapter 10,

“Interrupts.”

Figure 11-5 shows the logic diagram for Pin 86, one of six XA-SCC multifunction pins

which use an additional control bit, lo cated in the Pin Multiplexing Control Register. The

six pins which use this register are Pins 57, 66, 69, 74, 86, and 91. These pins all have an

extra gate associated with their multifunction logic, which is dependent on the state of

their PMCR bit.

Inspection of Figure 11-5 shows that a logic ‘0’ in PMCR[3] insures a ‘1’ on the lower

input to the AND gate of the Pin 86 driver, enabling the P2[6] output path. In this case, a

state change on RTS will have n o effect on Pin 86. Conversely, a logic ‘1’ in PMCR [3]

enables the RTS outp ut path from SCC3 to the Pin 86 driver, where a logic ‘1’ in the

P2[6] Output Latch enables th e RTS3 output function to the pin. Both output paths

require that Pin 86 be configured as an output (see 11.4.4, “Multifunction Pin

Programming Example”).

The function of the PMCR bits for Pins 57, 66, 69, 74, and 91 are similar in concept to

that for Pin 86.

Figure 11-5 Pin 86, Showing the Use of PMCR[3]

RTS

P2CFGB[6]

P2CFGA[6]

PMCR[3]

P2.6_RTS3

PIN 86

Border of

XA-SCC Chip

PAD LOGIC SCC3

To P2[6] DataIn

P2[6] Output Latch

252 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5 Multifunction Pin Schematics

11.5.1 Pin 56: P3.0_CS4_RAS4_RTClk1

Figure 11-6 Pin 56

Table 11-4 Programming Pin 56

Chosen

Function Description Direction P3CFGB/A[0] CS4_RAS4 SC1isIDL

Output

Latch

P3[0]

RTClk1 RTClk to SCC1 Input 1/0 X 0 X

CS4_RAS4 Output from MIF Output 1/1 Output Strobe X 1

P3.0 Input GPI/O Input Input 1/0 X X X

P3.0 Output GPI/O Output Output 1/1 1 X Output

Data

P3.1 I/O GPI/O

Quasi-Bidirectional I/O 0/1 1 X Output

Data

P3.1 Output GPI/O Open Drain Output 0/0 1 X Output

Data

P3.0_CS4_RAS4_RTClk1

PIN 56

To P3.0 DataIn

P3[0] Output Latch

P3CFGB[0]

P3CFGA[0]

Border of

XA-SCC Chip

RTClk1

SC1isIDL

L1Clk RTClk

PAD LOGIC

IDL

MIF SCC1

CS4_RAS4

Chapter 11: XA-SCC Pins 253

Multifu nction Pin Schematics

11.5.2 Pin 57: P3.1_CS5_RAS5_RTS1

Figure 11-7 Pin 57

Table 11-5 Programming Pin 57

Chosen

Function Description Direction P3CFGB/A[1] SC1isIDL PMCR[1] CS5_RAS5 Output

Latc h P3 [ 1 ]

RTS1 Request To Send

from SCC1 Output 1/1 0 1 1 1

CS5_RAS5 Out put from MIF Output 1/1 X 0 Output

Strobe 1

P3.1 Input GPI/O Input Input 1/0 X X X X

P3.1 Output GPI/O Output Output 1/1 X 0 1 Output Data

P3.1 I/O GPI/O

Quasi-Bidirectional I/O 0/1 X 0 1 Output Data

P3.1 Output GPI/O Open Drain Output 0/0 X 0 1 Output Data

RTS

P3CFGB[1]

P3CFGA[1]

PMCR[6]

CS5_RAS5

P3.1_CS5_RAS5_RTS1

PIN 57

SC1isIDL

Border of

XA-SCC Chip

PAD LOGIC MIF SCC1

To P3.1 DataIn

P3[1] Output Latch

254 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.3 Pin 58: P3.2_Timer0_ResetOut

During reset, when ResetIn is low, Pin 58 can be in an unknown state for up to 128 PClk

cycles (where PClk = CClk/2 = system clock / 2) . After 128 PClk cycles, Pin 58 and the

ResetOut function can be programmed in the normal manner. See Chapter 2, “XA-SCC

CPU, ” Sec tion 2.8, for details.

Figure 11-8 Pin 58

Table 11-6 Programming Pin 58

Chosen

Function Description Dir ection P3CFGB/A[2] T imer 0 Output Latch

P3[2]

Timer0_In Input to Timer 0 Input 1/0 On X

Timer0_Out Timer 0 Output Output 1/1 Enable Output 1

ResetOut Internal reset output Output 1/1 I

nore Input

and Disable

Output

P3.2 Input GPI/O Input Input 1/0 I

nore Input X

P3.2 Output GPI/ O Output Output 1/1 Disable Output Out put Data

P3.2 I/O GPI/O Quasi-Bidirectional I/O 0/1 Disable Output Output Data

P3.2 Output GPI/ O Open Drain Output 0/1 Disable Output Output Data

P3.2_Timer0_ResetOut

PIN 58

P3[2] Output Latch

ResetOut

Timer0_Out_Disable

Timer0_Out

Border of

XA-SCC Chip

PAD LOGIC

Timer0

ResetOut

Timer0_In

P3CFGB[2]

P3CFGA[2]

To P3[2] DataIn

Chapter 11: XA-SCC Pins 255

Multifu nction Pin Schematics

11.5.4 Pin 63: P3.3_BRG1_Timer1_Sync1

Figure 11-9 Pin 63

Table 11-7 Programming Pin 63

Chosen

Function Description Direction P3CFGB/A[3] Output

Latc h P3 [3] Time r 1 WR11[1:0]

Sync1 Sync to SCC1 Input 1/0 X I

nore Input X

Timer1_In To T imer 1 Input 1/0 X Use Input X

Timer1_Out From Timer 1 Output 1/1 1 Enable Output 00

TxClk1 TxClk from SCC1 Output 1/1 1 Disable Output 01

BRGOut1 BRGOut from SCC1 Output 1/1 1 Disable Output 10

SyncOut1 SyncOut from SCC1 Output 1/1 1 Disable Output 11

P3.3 Output GPI/O Output Output 1/1 Output Data Disable Output 00

P3.3 Input GPI/O Input Input 1/0 X I

nore Input X

P3.3 I/O GPI/O

Quasi-Bidirectional I/O 0/1 Output Data Disable Output 00

P3.3 Output GPI /O Open Drain Output 0/0 Output Data Disable Output 00

P3.3_BRG1_Timer1_Sync1

PIN 63

To P3[3] DataIn

P3[3] Output Latch BRG1

Timer1_Out

Timer1_Out_Disable

P3CFGB[3]

P3CFGA[3]

Timer1_In

WR11[1:0]

Sync

0 (off)

TxClk

BRGOut

SyncOut

Border of

XA-SCC Chip

PAD LOGIC

SCC1

Timer1

256 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.5 Pin 64: P3.4_CTS1

Figure 11-10 Pin 64

Table 11-8 Programming Pin 64

Chosen

Function Description Direction P3CFGB/A[4] Output Latch

P3[4]

CTS1 Clear to Send to SCC1 Input 1/0 X

P3.4 Input GPI/O Input Input 1/0 X

P3.4 Output GPI/O Output Output 1/1 Output Data

P3.4 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P3.4 Output GPI/O Open Drain Output 0/0 Output Data

P3.4_CTS1

PIN 64

To P3[4] DataIn

P3[4] Output Latch

P3CFGB[4]

P3CFGA[4]

Border of

XA-SCC Chip

PAD LOGIC SCC1

CTS

Chapter 11: XA-SCC Pins 257

Multifu nction Pin Schematics

11.5.6 Pin 65: P3.5_RxD1

Figure 11-11 Pin 65

Table 11-9 Programming Pin 65

Chosen

Function Description Direction P3CFGB/A[5] SC1isIDL Output

Latch P3[5]

RxD1 RxD input to SCC1,

Autobaud 1, or V.54/2047

Unit B

Input 1/0 0 X

P3.5 Input GPI/O Input Input 1/0 X X

P3.5 Output GPI/O Output Output 1/1 X Output Data

P3.5 I/O GPI/O Quasi-Bidirectional I/O 0/1 X Output Data

P3.5 Output GPI/O Open Drain Output 0/0 X Output Data

IDL

P3.5_RxD1

PIN 65

Border of

XA-SCC Chip

PAD LOGIC

IDL_RxD1

SC1isIDL

To P3[5] DataIn

P3[5] Output Latch

P3CFGB[5]

P3CFGA[5]

RxD

SCC1

V.54/2047 Unit B

(for SCC1 & 3)

Autobaud 1

258 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.7 Pin 66: P3.6_TxD1

If Autobau d 1 i s enabl ed, AbdTxD1 propagates to TD1. If Autobaud 1 is di s abl ed an d the

V.54/2047 generator is enabled for SCC1, then V.54TxD1 propagates to TD1. If both

Autobaud 1 and the V.54/2047 generator for SCC1 are disabled, then SCC1 TxD1

propagates to TD1. Please see Section 7.2 in Chapter 7, “V.54/2047 Units,” for details.

Figure 11-12 Pin 66

Table 11-10 Programming Pin 66

Chosen

Function Descriptio n Direction P3CFGB/A[6] SC1isIDL PMCR[4] Output Latch P3[6]

TxD1 TxD output from SCC1,

Autobaud 1, or V.54/

2047 Unit B

Output 1/1 0 1 1

P3.6 Input GPI/O Input Input 1/0 X X X

P3.6 Output GPI/O Output Output 1/1 X 0 Output Data

P3.6 I/O GPI/O

Quasi-Bidirectional I/O 0/1 X 0 Output Data

P3.6 Output GPI/O Open Drain Output 0/0 X 0 Output Data

To P3[6] DataIn

P3[6] Output Latch

D1Out TD1

P3.6_TxD1

PIN 66

P3CFGB[6]

P3CFGA[6]

Border of

XA-SCC Chip

PAD LOGIC

To IDL

SC1isIDL*

*If SC1isIDL = 1, then

D1Out = 1, allowing

GPI/O P3[6] to use

Pin 66 as an output.

PMCR[4]

SCC1

V.54/2047 Unit B

(for SCC1 & 3)

Autobaud 1

V54TxD1

Generator Enabled

to SCC1

TxD1

ABD1E

AbdTxD1

Chapter 11: XA-SCC Pins 259

Multifu nction Pin Schematics

11.5.8 Pin 67: P3.7_INT 1_TRClk1

Figure 11-13 Pin 67

Table 11-11 Programming Pin 67

Chosen

Function Description Direction P3CFGB/A[7] Outpu t Latch

P3[7]

TRClk1 TRClk input to SCC1 Input 1/0 X

INT1 Ex tern al Interrupt 1 Input 1/0 X

P3.7 Input GPI/O Input Input 1/0 X

P3.7 Output GPI/O Output Output 1/1 Output Data

P3.7 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P3.7 Output GPI/O Open Drain Output 0/0 O utput Data

P3.7_INT1_TRClk1

PIN 67

Border of

XA-SCC Chip

XA Interrupt Controller

SCC1

TRClk

INT1

ToP3[7] DataIn

P3[7] Output Latch

P3CFGB[7]

P3CFGA[7]

PAD LOGIC

260 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.9 Pin 68: P1.0_RxD2

Figure 11-14 Pin 68

Table 11-12 Programming Pin 68

Chosen

Function Description Direction P1CFGB/A[0] SC2isIDL Output Latch P1[0]

RxD2 RxD to SCC2, Autobaud 2,

or V.54/2047 Unit A Input 1/0 0 X

P1.0 Input GPI/O Input Input 1/0 X X

P1.0 Output GPI/O Output Output 1/1 X Output Data

P1.0 I/O GPI/O Quasi-Bi direct ional I/O 0/1 X Output Data

P1.0 Output GPI/O Open Drain Output 0/0 X Output Data

IDL

P1.0_RxD2

PIN 68

Border of

XA-SCC Chip

PAD LOGIC

IDL_RxD2

SC2isIDL

To P1[0] DataIn

P1[0] Output Latch

P1CFGB[0]

P1CFGA[0]

RxD

SCC2

V.54/2047 Unit B

(for SCC1 & 3)

Autobaud 1

Chapter 11: XA-SCC Pins 261

Multifu nction Pin Schematics

11.5.10 Pin 69: P1.1_TxD2

If Autobau d 2 i s enabl ed, AbdTxD2 propagates to TD2. If Autobaud 2 is di s abl ed an d the

V.54/2047 generator is enabled for SCC2, then V.54TxD2 propagates to TD2. If both

Autobaud 2 and the V.54/2047 generator for SCC2 are disabled, then SCC2 TxD2

propagates to TD2. Please see Section 7.2 in Chapter 7, “V.54/2047 Units,” for details.

Figure 11-15 Pin 69

Table 11-13 Programming Pin 69

Chosen

Function Description Direction P1CFGB/A[1] SC2isIDL PMCR[5] Output Latch P1[1]

TxD2 TxD from SCC2,

Autobaud 2, or V.54/

2047 Unit A

Output 1/1 0 1 1

P1.1 Input GPI/O Input Input 1/0 X X X

P1.1 Output GPI/O Output Output 1/1 X 0 Output Data

P1.1 I/O GPI/O

Quasi-Bidirectional I/O 0/1 X 0 Output Data

P1.1 Output GPI/O Open Drain Output 0/0 X 0 Out put Data

To P1[1] DataIn

P1[1] Output Latch

D2Out TD2

P1.1_TxD2

PIN 69

P1CFGB[1]

P1CFGA[1]

Border of

XA-SCC Chip

PAD LOGIC

To IDL

SC2isIDL*

PMCR[5]

1SCC2

V.54/2047 Unit A

(for SCC0 & 2)

Autobaud 2

V54TxD2

Generator Enabled

to SCC2

TxD2

ABD2E

AbdTxD2

*If SC2isIDL = 1, then

D2Out = 1, allowing

GPI/O P1[1] to use

Pin 69 as an output.

262 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.11 Pin 70: P1.2_RTClk2

Figure 11-16 Pin 70

Table 11-14 Programming Pin 70

Chosen

Function Description Direction P1CFGB/A[2] SC2isIDL Output Latch P1[2]

RTClk2 RTClk input to SCC2 Input 1/0 0 X

P1.2 Input GPI/O Input Input 1/0 X X

P1.2 Output GPI/O Output Output 1/1 X Output Data

P1.2 I/O GPI/O

Quasi-Bidirectional I/O 0/1 X Output Data

P1.2 Output GPI/O Open Drain Output 0/0 X Output Data

P1.2_RTClk2

PIN 70

To P1[2] DataIn

P1[2] Output Latch

P1CFGB[2]

P1CFGA[2]

Border of

XA-SCC Chip SC2isIDL

L1Clk RTClk

PAD LOGIC IDL SCC2

IDL Logic

Chapter 11: XA-SCC Pins 263

Multifu nction Pin Schematics

11.5.12 Pin 71: P1.3_TRClk2

Figure 11-17 Pin 71

Table 11-15 Programming Pin 71

Chosen

Function Description Direction P1CFGB/A[3] Output Latch P1[3]

TRClk2 TRClk input to SCC2 Input 1/0 X

P1.3 Input GPI/O Input Input 1/0 X

P1.3 Output GPI/O Output Output 1/1 Output Data

P1.3 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P1.3 Output GPI/O Open Drain Output 0/0 Output Data

P1.3_TRClk2

PIN 71

To P1[3] DataIn

P1[3] Output Latch

P1CFGB[3]

P1CFGA[3]

Border of

XA-SCC Chip

PAD LOGIC SCC2

TRClk

264 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.13 Pin 72: P1.4_CD2

Figure 11-18 Pin 72

Table 11-16 Programming Pin 72

Chosen

Function Description Direction P1CFGB/A[4] Output Latch P1[4]

CD2 Carrier Detect to SCC2 Input 1/0 X

P1.4 Input GPI/O Input Input 1/0 X

P1.4 Output GPI/O Output Output 1/1 Output Data

P1.4 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P1.4 Output GPI/O Open Drain Output 0/0 Output Data

P1.4_CD2

PIN 72

To P1[4] DataIn

P1[4] Output Latch

P1CFGB[4]

P1CFGA[4]

Border of

XA-SCC Chip

PAD LOGIC SCC2

DCD

Chapter 11: XA-SCC Pins 265

Multifu nction Pin Schematics

11.5.14 Pin 73: P1.5_CTS2

Figure 11-19 Pin 73

Table 11-17 Programming Pin 73

Chosen

Function Description Direction P1CFGB/A[5] Output Latch P1[5]

CTS2 Clear to Send to SCC2 Input 1/0 X

P1.5 Input GPI/O Input Input 1/0 X

P1.5 Output GPI/O Output Output 1/1 Output Data

P1.5 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P1.5 Output GPI/O Open Drain Output 0/0 Output Data

P1.5_CTS2

PIN 73

To P1[5] DataIn

P1[5] Output Latch

P1CFGB[5]

P1CFGA[5]

Border of

XA-SCC Chip

PAD LOGIC SCC2

CTS

266 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.15 Pin 74: P1.6_RTS2

Figure 11-20 Pin 74

Table 11-18 Programming Pin 74

Chosen

Function Description Direction P1CFGB/A[6] SC2isIDL PMCR[2] Output Latch P1[6]

RTS2 Request to Send from

SCC2 Output 1/1 0 1 1

P1.6 Input GPI/O Input Input 1/0 X X X

P1.6 Output GPI/O Output Output 1/1 X 0 O utput Data

P1.6 I/O GPI/O

Quasi-Bidirectional I/O 0/1 X 1 Output Data

P1.6 Output GPI /O Open Drain Output 0/0 X 1 Output Data

P1CFGB[6]

P1CFGA[6]

P1.6_RTS2

PIN 74

Border of

XA-SCC Chip

PAD LOGIC

To P1[6] DataIn

P1[6] Output Latch RTS

PMCR[2]

SC2isIDL

SCC2

Chapter 11: XA-SCC Pins 267

Multifu nction Pin Schematics

11.5.16 Pin 75: P1.7_BRG2_Sync2

Figure 11-21 Pin 75

Table 11-19 Programming Pin 75

Chosen

Function Description Direction P1CFGB/A[7] Output

Latch P1[7] WR11[1:0]

Sync2 Sync input to SCC2 Input 1/0 X X

TxClk2 TxClk from SCC2 Output 1/1 1 01

BRGOut2 BRGOut from SCC2 Output 1/1 1 10

SyncOut2 SyncOut from SCC2 Output 1/1 1 11

P1.7 Input GPI/O input Input 1/0 X X

P1.7 Output GPI/O output Output 1/1 Output Data 00

P1.7 I/O GPI/O

Quasi-Bidirectional I/O 0/1 Output Data 00

P1.7 Output GPI/O Open Drain Output 0/0 Output Data 00

P1.7_BRG2_Sync2

PIN 75

To P1[7] DataIn

P1[7] Output Latch BRG2

P1CFGB[7]

P1CFGA[7]

Sync2

WR11[1:0]

Sync

0 (off)

TxClk

BRGOut

SyncOut

Border of

XA-SCC Chip

PAD LOGIC

SCC2

268 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.17 Pin 78: CD1_Int2 (Input Only)

Figure 11-22 Pin 78

Table 11-20 Programming Pin 78 (Input Only)

Chosen

Function Description Direction External Interrupt 2 SCC1

CD1 Carrier Detect to SCC1 Input I

nore input Use input

Int2 External Interrupt 2 Input Use input I

nore input

CD1_Int2

PIN 78

To XA

Interrupt

Controller

INPUT ONLY

Border of

XA-SCC Chip

SCC1

DCD

External Interrupt

2 Logic

Chapter 11: XA-SCC Pins 269

Multifu nction Pin Schematics

11.5.18 Pin 80: P2.0_RxD3

Figure 11-23 Pin 80

Table 11-21 Programming Pin 80

Chosen

Function Description Direction P2CFGB/A[0] Output Latch P2[0]

RxD3 RxD Input to SCC3 Input 1/0 X

P2.0 Input GPI/O Input Input 1/0 X

P2.0 Output GPI/O Output Output 1/1 Output Data

P2.0 I/O GPI/O Quasi-Bidirecti onal I/O 0/1 Output Data

P2.0 Output GPI/O Open Drain Output 0/0 Output Data

P2.0_RxD3

PIN 80

To P2[0] DataIn

P2[0] Output Latch

P2CFGB[0]

P2CFGA[0]

Border of

XA-SCC Chip

PAD LOGIC SCC3

RxD

270 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.19 Pin 81: P2.1_TxD3

If Autobau d 3 i s enabl ed, AbdTxD3 propagates to TD3. If Autobaud 3 is di s abl ed an d the

V.54/2047 generator is enabled for SCC3, then V.54TxD3 propagates to TD3. If both

Autobaud 3 and the V.54/2047 generator for SCC3 are disabled, then SCC3 TxD3

propagates to TD3. Please see Section 7.2 in Chapter 7, “V.54/2047 Units,” for details.

Figure 11-24 Pin 81

Table 11-22 Programming Pin 81

Chosen

Function Description Direction P 2CFGB/A[1] Output Latch P2[1]

TxD3 TxD from SCC3, Autobaud

3, or V.54/2047 Unit B Output 1/1 1

P2.1 Input GPI/O Input Input 1/0 X

P2.1 Output GPI/O Output Output 1/1 Output Data

P2.1 I/O GPI/O Quasi-Bidirect ional I/O 0/1 Output Data

P2.1 Output GPI/O Open Drain Output 0/0 Output Data

To P2[1] DataIn

P2[1] Output Latch TD3

P2.1_TxD3

PIN 81

P2CFGB[1]

P2CFGA[1]

Border of

XA-SCC Chip

PAD LOGIC

1SCC3

V.54/2047 Unit B

(for SCC1 & 3)

Autobaud 3

V54TxD3

Generator Enabled

to SCC3

TxD3

ABD3E

AbdTxD3

Chapter 11: XA-SCC Pins 271

Multifu nction Pin Schematics

11.5.20 Pin 82: P2.2_RTClk3

Figure 11-25 Pin 82

Table 11-23 Programming Pin 82

Chosen

Function Description Direction P2CFGB/A[2] Output Latch P2[2]

RTClk3 RTClk to SCC3 Input 1/0 X

P2.2 Input GPI/O Input Input 1/0 X

P2.2 Output GPI/O Output Output 1/1 Output Data

P2.2 I/O GPI/O Quasi-Bidirecti onal I/O 0/1 Output Data

P2.2 Output GPI/O Open Drain O u tput 0/0 Output Data

P2.2_RTClk3

PIN 82

To P2[2] DataIn

P2[2] Output Latch

P2CFGB[2]

P2CFGA[2]

Border of

XA-SCC Chip

PAD LOGIC SCC3

RTClk

272 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.21 Pin 83: P2.3_ComClk_TRClk3

Although ComClk appears to be redundant with TRClk3 for SCC3, ComClk can be

routed through the SCC3 Baud Rate Generator, while TRClk3 cannot (see Sectio n 5.5,

“Baud Rate Generator” and Figure 5-7, “SCC3 Clocks” for details). This connection to

TRClk3 is provided to keep the programming model consistent across all four SCC’s.

Figure 11-26 Pin 83

Table 11-24 Programming Pin 83

Chosen

Function Description Direction P2CFGB/A[3] Output Latch P2[3]

ComClk Common Clock to SCC0 - SCC3 Inpu t 1/0 X

TRClk3 TRClk to SCC3 Input 1/0 X

P2.3 Input GPI/O Input Input 1/0 X

P2.3 Output GPI/O Output Output 1/1 Output Data

P2.3 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P2.3 Output GPI/O Open Drain Output 0/0 Output Data

P2.3_ComClk_TRClk3

PIN 83

To P2[3] DataIn

P2[3] Output Latch

P2CFGB[3]

P2CFGA[3]

Border of

XA-SCC Chip

PAD LOGIC SCC3

TRClk

ComClk

SCC2

ComClk

SCC1

ComClk

SCC0

ComClk

Chapter 11: XA-SCC Pins 273

Multifu nction Pin Schematics

11.5.22 Pin 84: P2.4_CD3

Figure 11-27 Pin 84

Table 11-25 Programming Pin 84

Chosen

Function Description Direction P2CFGB/A[4] Output Latch

P2[4]

CD3 Carrier Detect to SCC3 Input 1/0 X

P2.4 Input GPI/ O Input Input 1/0 X

P2.4 Output GPI/O Output Output 1/1 Output Data

P2.4 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P2.4 Output GPI/O Open Drain Output 0/0 Output Data

P2.4_CD3

PIN 84

To P2[4] DataIn

P2[4] Output Latch

P2CFGB[4]

P2CFGA[4]

Border of

XA-SCC Chip

PAD LOGIC SCC3

DCD

274 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.23 Pin 85: P2.5_CTS3

Figure 11-28 Pin 85

Table 11-26 Programming Pin 85

Chosen

Function Description Direction P2CFGB/A[5] Output Latch

P2[5]

CTS Clear to Send to SCC3 Input 1/0 X

P2.5 Input GPI/O Input Input 1/0 X

P2.5 Output GPI/O Output Output 1/1 Output Data

P2.5 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P2.5 Output GPI/O Open Drain Output 0/0 Output Data

P2.5_CTS3

PIN 85

To P2[5] DataIn

P2[5] Output Latch

P2CFGB[5]

P2CFGA[5]

Border of

XA-SCC Chip

PAD LOGIC SCC3

CTS

Chapter 11: XA-SCC Pins 275

Multifu nction Pin Schematics

11.5.24 Pin 86: P2.6_RTS3

Figure 11-29 Pin 86

Table 11-27 Programming Pin 86

Chosen

Function Description Direction P2CFGB/A[6] PMCR[3] Output

Latch P2[6]

RTS3 Reques t to Send from

SCC3 Output 1/1 1 1

P2.6 Input GPI/O Input Input 1/0 X X

P2.6 Output GPI/O Output Output 1/1 0 Output Data

P2.6 I/O GPI/O Quasi-Bidirectional I/O 0/1 0 Output Data

P2.6 Output GPI/O Open Drain Output 0/0 0 Output Data

RTS

P2CFGB[6]

P2CFGA[6]

PMCR[3]

P2.6_RTS3

PIN 86

Border of

XA-SCC Chip

PAD LOGIC SCC3

To P2[6] DataIn

P2[6] Output Latch

276 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.25 Pin 87: P2.7_Sync3_BRG3

Figure 11-30 Pin 87

Table 11-28 Programming Pin 87

Chosen

Function Description Direction P2CFGB/A[7] Output Latch P2[7] WR11[1:0]

Sync3 Sync Input to SCC3 Input 1/0 X X

TxClk3 TxClk Output from

SCC3 Output 1/1 1 01

BRGOut3 BRGOut from SCC3 Output 1/1 1 10

SyncOut3 SyncOut from SCC3 Output 1/1 1 11

P2.7 Input GPI/O Input Input 1/0 X X

P2.7 Output GPI/O Output Output 1/1 Output Data 00

P2.7 I/O GPI/O

Quasi-Bidirectional I/O 0/1 Output Data 00

P2.7 Output GPI/O Open Drain Output 0/0 Output Data 00

P2.7_Sync3_BRG3

PIN 87

To P2[7] DataIn

P2[7] Output Latch BRG3

P2CFGB[7]

P2CFGA[7]

Sync3

WR11[1:0]

Sync

0 (off)

TxClk

BRGOut

SyncOut

Border of

XA-SCC Chip

PAD LOGIC

SCC3

Chapter 11: XA-SCC Pins 277

Multifu nction Pin Schematics

11.5.26 Pin 90: P0.0_Sync0_BRG0_SDS2

Figure 11-31 Pin 90

Table 11-29 Programming Pin 90

Chosen

Function Description Direction P0CFGB/A[0] Output

Latch P0[0] IDL WR11[1:0]

Sync0 Sync to SCC0 Input 1/0 X Off X

SDS2 SDS2 from IDL Output 1/1 1 On 00

TxClk0 TxClk from SCC0 Output 1/ 1 1 Off 01

BRGOut0 BRGOut from SCC0 Output 1/1 1 Off 10

SyncOut0 SyncOut from SCC0 Output 1/1 1 Off 11

P0.0 Input GPI/O Input Input 1/0 X SDS2 not

available for

IDL if input pin

P0.0 Output GPI/O Output Output 1/1 Output Data Off 00

P0.0 I/O GPI/O

Quasi-Bidirectional I/O 0/1 Output Data Off 00

P0.0 Output GPI/O Open Drain Output 0/0 Output Data Off 00

Note: MSI Control[2:0] = 111 is IDLOff, and M SI Control[2:0] ≠ 111 is IDLOn.

*MSI Control[2:0] ≠ 111 is IDLOn

**MSI Control[2:0] = 111 is IDLOff

P0.0_Sync0_BRG0_SDS2

PIN 90

To P0[0] DataIn

P0[0] Output Latch

SDS2

IDLOff**

P0CFGB[0]

P0CFGA[0]

Sync0

WR11[1:0]

Sync

0 (off)

TxClk

BRGOut

SyncOut

Border of

XA-SCC Chip

PAD LOGIC SCC0

IDL

IDLOn*

278 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.27 Pin 91: P0.1_RTS0_L1RQ

Figure 11-32 Pin 91

Table 11-30 Programming Pin 91

Chosen

Function Description Direction P0CFGB/A[1] Output

Latch P0[1] IDL PMCR[0]

RTS0 Reques t to Send from

SCC0 Output 1/1 1 Off 1

L1RQ Output from IDL Interface Output 1/1 1 On 0

P0.1 Input GPI/O Input Input 1/0 X Off X

P0.1 Output GPI/O Output Output 1/1 Outpu t Data Off 0

P0.1 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data Off 0

P0.1 Output GPI/O Open Drain Output 0/0 Output Data Off 0

Note: MSI Control[2:0] = 111 is IDLOff, and M SI Control[2:0] ≠ 111 is IDLOn.

L1RQ

IDLOff*

*MSI Control[2:0] = 111 is IDLOff

IDL

RTS

P0CFGB[1]

P0CFGA[1]

PMCR[0]

P0.1_RTS0_L1RQ

PIN 91 IDLOff*

Border of

XA-SCC Chip

PAD LOGIC

To P0[1] DataIn

P0[1] Output Latch

SCC0

Chapter 11: XA-SCC Pins 279

Multifu nction Pin Schematics

11.5.28 Pin 92: P0.2_CTS0_L1GR

Figure 11-33 Pin 92

Table 11-31 Programming Pin 92

Chosen

Function Description Direction P0CFGB/A[2] Output Latch

P0[2]

CTS0 Clear to Send to SCC0 Input 1/0 X

L1GR Input to IDL Input 1/0 X

P0.2 Input GPI/O Input Input 1/0 X

P0.2 Output GPI/O Output Output 1/1 Output Data

P0.2 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P0.2 Output GPI/O Open Drain Output 0/0 Output Data

P0.2_CTS0_L1GR

PIN 92

To P0[2] DataIn

P0[2] Output Latch

P0CFGB[2]

P0CFGA[2]

Border of

XA-SCC Chip

PAD LOGIC IDL

SCC0

CTS

L1GR

280 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.29 Pin 93: P0.3_CD0_L1SY1

Figure 11-34 Pin 93

Table 11-32 Programming Pin 93

Chosen

Function Description Direction P0CFGB/A[3] Output Latch

P0[3]

CD0 Carrier Detect to SCC0 Input 1/0 X

L1SY1 SYNC Input to IDL Input 1/0 X

P0.3 Input GPI/O Input Input 1/0 X

P0.3 Output GPI/O Output Output 1/1 Output Data

P0.3 I/O GPI/O Quasi-Bidirectional I/O 0/1 Output Data

P0.3 Output GPI/O Open Drain Output 0/0 Output Data

P0.3_CD0_L1SY1

PIN 93

To P0[3] DataIn

P0[3] Output Latch

P0CFGB[3]

P0CFGA[3]

Border of

XA-SCC Chip

PAD LOGIC IDL

SCC0

DCD

L1SY1

Chapter 11: XA-SCC Pins 281

Multifu nction Pin Schematics

11.5.30 Pin 94: P0.4_TRClk0_SDS1

Figure 11-35 Pin 94

Table 11-33 Programming Pin 94

Chosen

Function Description Direction P0CFGB/A[4] Output

Latch P0[4] IDL

TRClk0 TRClk to SCC0 Input 1/0 X Off

SDS1 Output from IDL

Interface Output 1/1 1 On

P0.4 Input GPI/O Input Input 1/0 X SDS1 not

available for IDL

if input pin

P0.4 Output GPI/O Output Output 1/1 Output Data Off

P0.4 I/O GPI/O

Quasi-Bidirectional I/O 0/1 Output Data Off

P0.4 Output GPI/O Open Drain Output 0/0 Output Data O ff

Note: MSI Control[2:0] = 111 is IDLOff, and MSI Control[2:0] ≠ 111 is IDLOn.

TRClk

P0CFGB[4]

P0CFGA[4]

P0[4] Output Latch

P0.4_TRClk0_SDS1

PIN 94

Border of

XA-SCC Chip

PAD LOGIC SCC0

To P0[4] DataIn

SDS1

IDLOff*

*MSI Control[2:0] = 111 is IDLOff

IDL

282 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.31 Pin 95: P0.5_RTClk0_L1Clk

Figure 11-36 Pin 95

Table 11-34 Programming Pin 95

Chosen

Function Description Direction P0CFGB/A[5] Output

Latch P0[5] I DL

RTClk0 RTClk to SCC0 Input 1/0 X Off

L1Clk Master IDL clock Input 1/0 X On

P0.5 Input GPI/O Input Input 1/0 X Off

P0.5 Output GPI/O Output Output 1/1 Output Data Off

P0.5 I/O GPI/O Quasi-

Bidirectional I/O 0/1 Output Data Off

P0.5 Output GPI/O Open Drain Output 0/0 Output Data Off

Note: MSI Control[2:0] = 111 is IDLOff, and MSI Control[2:0] ≠ 111 is IDLOn.

P0.5_RTClk0_L1Clk

PIN 95

To P0[5] DataIn

P0[5] Output Latch

P0CFGB[5]

P0CFGA[5]

Border of

XA-SCC Chip IDLOn*

*MSI Control[2:0] ≠111 is IDLOn

RTClk

RClk0

PAD LOGIC IDL SCC0

IDL Clock

Filter 1

Chapter 11: XA-SCC Pins 283

Multifu nction Pin Schematics

11.5.32 Pin 96: TxD0_L1TxD

If Autobau d 0 i s enabl ed, AbdTxD0 propagates to TD0. If Autobaud 0 is di s abl ed an d the

V.54/2047 generator is enabled for SCC0, then V.54TxD0 propagates to TD0. If both

Autobaud 0 and the V.54/2047 generator for SCC0 are disabled, then SCC0 TxD0

propagates to TD0. Please see Section 7.2 in Chapter 7, “V.54/2047 Units,” for details.

When IDL is on, the pin driver is tri-state enabled and disabled repeatedly during normal

operation (unl ike mos t mult i -fun ct io n pins , whi ch are us ual ly configured just once duri ng

initialization).

Figure 11-37 Pin 96

Table 11-35 Programming Pin 96 (Output Only)

Chosen Function Description Direction IDL

TxD0 TxD from SCC0, Autobaud 0, and V.54/2047

Unit A Output Off

L1TxD IDL Transmit Data Output On

Note: MSI Control[2:0] = 111 is IDLOff, and MSI Control[2:0] ≠ 111 is IDLOn.

TD0

TD1

L1TxD

TriStEn

D0Out

TD2

TxD0_L1TxD

PIN 96

Border of

XA-SCC Chip

PAD LOGIC

IDL

Logic

IDLOn*

*MSI Control[2:0] ≠111 is IDLOn

SCC0

V.54/2047 Unit A

(for SCC0 & 2)

Autobaud 0

V54TxD0

Generator Enabled

to SCC0

TxD0

ABD0E

AbdTxD0

IDL

284 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.33 Pin 97: RxD0_L1RxD

Figure 11-38 Pin 97

Table 11-36 Programming Pin 97 (Input Only)

Chosen Function Description Direction IDL

RxD0 RxD to SCC0, Autobaud 0, and V.54/2047 Unit

AInput Off

L1RxD IDL Receive Data Input On

Note: MSI Control[2:0] = 111 is IDLOff, and MSI Control[2:0] ≠ 111 is IDLOn.

RxD

SCC0

Autobaud 0

V.54/2047 Unit A

(for SCC0 & 2)

L1RxD

IDLOff*

IDL

RxD0_L1RxD

PIN 97

INPUT ONLY

Border of

XA-SCC Chip

RxD 1

IDL Logic

*MSI Control[2:0] = 111 is IDLOff

Chapter 11: XA-SCC Pins 285

Multifu nction Pin Schematics

11.5.34 Pin 99: P0.6_SCPTx

Figure 11-39 Pin 99

Table 11-37 Programming Pin 99

Chosen

Function Description Direction P0CFGB/A[6] Output

Latch P0[6] SCP

SCPTx Tx Output from SCP Output 1/1 1 On

P0.6 Input GPI/O Input Input 1/0 X Off

P0.6 Output GPI/O Output Output 1/1 Output Data Off

P0.6 I/O GPI/O

Quasi-Bidirectional I/O 0/1 Output Data Off

P0.6 Output GPI/O Open Drain Output 0/0 Output Data Off

SCPTx

P0CFGB[6]

P0CFGA[6]

P0[6] Output Latch

P0.6_SCPTx

PIN 99

Border of

XA-SCC Chip

PAD LOGIC SCP

To P0[6] DataIn

286 Chapter 11: XA-SCC Pins

Multifunction Pin Schematics

11.5.35 Pin 100: P0.7_SCPRx

Figure 11-40 Pin 100

Table 11-38 Programming Pin 100

Chosen

Function Description Direction P0CFGB/A[7] Output

Latc h P0 [7] SCP

SCPRx Rx Input to SCP Input 1/0 X On

P0.7 Input GPI/O Input Input 1/0 X Off

P0.7 Output GPI/O Output Output 1/1 Output Data Off

P0.7 I/O GPI/O Quasi- Bidirect ional I/O 0/1 Output Data Off

P0.7 Output GPI/O Open Drain Output 0/0 Output Data Off

P0.7_SCPRx

PIN 100

To P0[7] DataIn

P0[7] Output Latch

P0CFGB[7]

P0CFGA[7]

Border of

XA-SCC Chip

PAD LOGIC SCP

SCPRx

Chapter 11: XA-SCC Pins 287

XA-SCC Pinou t

11.6 XA-SCC Pinout

CS0

CS1_RAS1

CS2_RAS2

CS3_RAS3

ClkOut

VSS

VDD

D15

D14

D13

D12

D11

D10

VDD

VSS

A19

A18

A17 (A8_A18_A19)

A16 (A7_A20_A21)

VDD

VSS

A15 (A6_A22)

A14 (A5)

A13 (A4)

A12 (A3)

A11 (A2)

A10 (A1)

A9 (A0_A18)

A8 (A19_A20)

A7 (A21_A22)

VDD

VSS

VDD

CD1_Int2

Int0

P2.0_RxD3

P2.1_TxD3

P2.2_RTClk3

P2.3_ComClk_TRClk3

P2.4_CD3

P2.5_CTS3

P2.6_RTS3

P2.7_Sync3_BRG3

VSS

VDD

P0.0_Sync0_BRG0_SDS2

P0.1_RTS0_L1RQ

P0.2_CTS0_L1GR

P0.3_CD0_L1SY1

P0.4_TRClk0_SDS1

P0.5_RTClk0_L1Clk

TxD0_L1TxD

RxD0_L1RxD

SCPClk

P0.6_SCPTx

P0.7_SCPRx

P1.7_BRG2_Sync2

P1.6_RTS2

P1.5_CTS2

P1.4_CD2

P1.3_TRClk2

P1.2_RTClk2

P1.1_TxD2

P1.0_RxD2

P3.7_Int1_TRClk1

P3.6_TxD1

P3.5_RxD1

P3.4_CTS1

P3.3_Timer1_BRG1_Sync1

VDD

XTALOUT

XTALIN

VSS

P3.2_Timer0_ResetOut

P3.1_CS5_RTS1

P3.0_CS4_RTClk1

ResetIn

BLE_CASL

BHE_CASH

WAIT_Size8

1 5 10 15 20

5255606570

Top View 100 Pin LQFP

XA–SCC

Base Part Number P51XASCC

Note: Address lines output during various

DRAM CAS cycles are shown in parentheses.

See "Memory Interface (MIF) and DRAM

Controller" for details.

288 Chapter 11: XA-SCC Pins

XA-SCC Pinout

Appendix A: XA-SCC Pro

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Examples 289

Appendix A

XA-SCC Pro

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Exam

les A

Contents

A.1 Introduction...............................................................................................................................................290

A.2 Boot Code & Bank 0 / Bank 1 Swappin

(Assembly ) ..... .......... ..................... ................................ ...........290

A.3 Set Up SCC3/ DMA3 for Async Mode (C) .......... ......................................................... ............ ..................295

A.4 Set Up IDL (C) ..........................................................................................................................................297

A.5 Set Up SCC1/DMA1 for Clear Channel with IDL (C) ................................................................................299

A.6 Set Up SCC3/DMA3 for Clear Channel with NMSI (C).............................................................................302

A.7 Set Up SCC0/DMA0 for HDLC Tx Chainin

with IDL (C)....... ..................................................................304

A.8 Note About Reset External/Status Interrupts Command ..........................................................................307

290 Appendix A: XA-SCC Pro

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Examples

Introduction

A.1 Introduction

The programming examples in this Appendix are portions of fully tested XA-SCC

Assembly and C code. The C code examples demonstrate the configuration and set up

procedure of SCC and DMA channels for different communication protocols. The

assembly code example demonstrates a typical XA-SCC boot sequen ce, followed by code

moving and Bank 0/1 Swapping routines.

A.2 Boot Code & Bank 0 / Bank 1 Swapping (Assembly)

The following is an assembly language example of XA-SCC boot code, including Bank 0

/ Bank 1 Swapping. The example assumes that a 64K Byte Flash device is attached to

CS0 and a 512K Byte DRAM device is attached to CS1.

The memory arran gement befo re and after bank swapping is summarized in the following

tables:

Table A-1 Initial Configuration, Before Swapping

Table A-2 Final Configuration, After Swapping

These examples are not complete programs. By themselves, they are insufficient to run

the XA-SCC.

Bank Memory Type Size Address Range Remarks

0 Flash 64K 000000h - 00FFFFh This address ran

e activates Flash on CS0.

1 DRAM 512K 080000h - 0FFFFFh This address ran

e activates DRAM on CS1.

Bank Memory Type Size Address Range Remarks

1 unchan

ed 64K 080000h - 08FFFFh This address ran

e activates Flash on CS0.

0 unchan

ed 512K 000000h - 07FFFFh This address ran

e activates DRAM on CS1.

Appendix : Boot Code & Bank 0 / Bank 1 Swappin

(Assembly) 291

Boot Co de & B ank 0 / Bank 1 Swa pping ( Assemb ly)

Program execution for this example proceeds in the following manner:

• Since an XA reset is actually the Precedence 7 Exception Interrupt, the reset vector

(new PSW followed by new PC) must be located at address 000000h.

• On reset, the PC is loaded with the address of “CodeMover.” This is where the boot

code resides and execution commences from there:

– The Watchdog Timer is disabled.

– The base address for MMR space is selected.

– Bus timing is programmed.

– Memory Banks 0 and 1 are configured.

– Refresh timing is programmed and refresh is enabled.

• The entire block of code, from 000000h to CodeMover (which includes the User ’s

Application Code), is copied from Flash into DRAM.

• Program execution branches to the address labeled “SWAP” and Bank 0 / Bank 1

Swapping is executed.

• With the program executing from DRAM, a branch is taken to the label START, where

the User’s Application Code resides.

;**********************************************************************************

DRAM equ 08h ; Assembler directive. The DRAM bank will start at

; 080000h.

;** XA Reset is the Precedence 7 Exception Interrupt with vector address 0000h-0003h.

org 0h ; Forces the reset vector to load at address 000000h.

dw 8f00h ; New PSW for Reset Exception Interrupt.

dw CodeMover; New PC for Reset Exception Interrupt. Program

; execution begins at CodeMover.

;**********************************************************************************

org 200h

START:

; User’s Application Code goes here

;**********************************************************************************

org 2000h

SWAP:

;** Prepare Banks 1 and 0 for swapping. First unlock Memory Bank Configuration Locks.

mov.b ES,#0fh ; Explicitly set ES to be the segment 0Fh, for accessing

; MMRs using R5 as the pointer.

mov.w r5,#MBCL ; R5 points to MBCL MMR.

mov.b [r5],#00h ; MBCL = 00h unlocks all Memory Bank Configuration

; Locks.

;** Change Bank 1 Size.

mov.w r5,#B1CFG ; R5 points to Bank 1 Configuration Register.

292 Appendix A: XA-SCC Pro

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Examples

Boot Code & B ank 0 / Bank 1 Swa pping (Assembl y)

mov.b [r5],#0f8h ; B1CFG = 11111000. Bits [7:4] same as before. Bits

; [3:0] = 1000 select new Bank 1 Size = 64K Bytes,

; base address remains 080000h. So after swap,

; accesses to 080000h - 08FFFFh will activate CS0

; (the Flash).

;** Change Bank 0 Size.

mov.w r5,#B0CFG ; R5 points to Bank 0 Configuration Register.

mov.b [r5],#0cbh ; B0CFG = 11001011. Bits [7:4] same as before. Bits

; [3:0] = 1011 select Bank 0 Size = 512K Bytes with

; base address hardwired to 000000h. So after swap,

; accesses to 000000h - 07FFFFh will activate CS1

; (the DRAM).

;** Lock Memory Bank Configuration Locks for Banks 0 and 1.

mov.w r5,#MBCL ; R5 points to MBCL MMR.

mov.b [r5],#03fh ; Set lock bits for Banks 0 and 1.

nop ; Use NOPs to fill prefetch queue (7 max).

nop

mov.b [r5],#0bfh ; Setting MBCL[7] executes SWAP. Bit[6] is

; reserved. Bits [5:0] = 11111 locks MBCLs for all

; banks

nop ; Use NOPs to fill prefetch queue.

nop

Appendix : Boot Code & Bank 0 / Bank 1 Swappin

(Assembly) 293

Boot Co de & B ank 0 / Bank 1 Swa pping ( Assemb ly)

nop

;** Now, go to beginning of User’s Application Code after banks have been swapped.

jmp START ; Jump unconditionally to START.

;**********************************************************************************

CodeMover: ;Code execution vectored to here by reset.

;** Disable Watchdog Timer.

mov.b WDCON,#0 ; Write Watchdog Control Reg. to clear WDRUN.

mov.b WFEED1,#0a5h ; Do Watchdog feed part 1.

mov.b WFEED2,#5ah ; Do Watchdog feed part 2.

;** Set MMR base address = 0FF000h, and enable access to MMRs.

mov.b MRBH,#0fh ; MMR base address is formed by concatenating

; MRBH[7:0] MRBL[7:4] [0000b] [00h].

mov.b MRBL,#0f1h ; MRBL[0] = 1 enables access to MMRs.

;** Configure SSEL, DS, and ES SFRs.

mov.b SSEL,#0e0h ; SSEL = 11100000. Bit [7] = ESWEN = 1 enables

; write privileges to data segment via ES Register.

; Bits [6:5] = 11 make R6 and R5 pointers into

; Extra Segment. Bits [4:0] = 00000 make R4 - R0

; pointers into Data Segment.

mov.b DS,#00h ; Explicitly set DS = Segment 00h.

mov.b ES,#0fh ; Explicitly set ES = Segment 0Fh (same as MMRs).

;** Set up Bus Timing Registers. Values for prototype were BTRH = 55h and BTRL = 60h.

mov.b BTRH,#051h ; BTRH must be 51h!

mov.b BTRL,#040h ; BTRL must be 40h!

;** Unlock Memory Bank Configuration Locks, in prep. for setting up Memory Banks.

mov.w r5,#MBCL ; R5 points to MBCL MMR.

mov.b [r5],#00h ; Unlock Memory Bank Configuration Locks.

;** Set up Memory Bank 0. CS0 attached to 64K Byte Flash.

mov.w r5,#B0CFG ; R5 points to Bank 0 Configuration Reg. MMR.

mov.b [r5+],#0c8h ; B0CFG = 11001000. Bit [7] = 1 enables code

; memory access. Bit[6] = 1 enables data memory

; access. Bits [2:0] = 000 set Bank 0 size = 64K

294 Appendix A: XA-SCC Pro

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Examples

Boot Code & B ank 0 / Bank 1 Swa pping (Assembl y)

; Bytes, which yields address range 000000h -

; 00FFFFh.

mov.b [r5+],#00h ; B0AM is already hardwired to 00h.

mov.b [r5+],#048h ; B0TMG = 01001000. Bit [6] = 1 selects 1 cycle CS

; to BLE/BHE delay. Bits [5:3] = 001 select 2 cycle

; access time. Bits [2:1] = 00 select 2 cycle recovery

; time.

;** Set up Memory Bank 1. CS1 attached to 512K Byte DRAM.

mov.w r5,#B1AM ; R5 points to B1AM Register.

mov.b [r5+],#DRAM ; B1AM = 00001000.

mov.b [r5],#0ch ; B1TMG = 00001100. Bit [7] = 0 selects non-EDO

; DRAM. Bit [6] = 0 selects 2 cycle RAS to CAS

; delay. Bits[5:3] = 001 select 2 cycle Access Time.

; Bits [2:1] = 10 select 3 cycle Recovery Time.

mov.w r5,#B1CFG ; R5 points to B1CFG, must be programmed last.

mov.b [r5],#0fbh ; B1CFG = 11111011. Bit [7] = 1 enables code

; memory access. Bit [6] = 1 enables data memory

; access. Bit [5] = 1 selects 16-bit data bus width. Bit

; [4] = 1 selects DRAM Interface. Bits [3:0] =

; 1011 select Bank size = 512K Bytes. Therefore,

; base address is formed by concatenating

; B1AM[7:3][000b][00h][00h] = 080000h. So Bank 1

; address range is 080000h - 0FFFFFh.

;** Set up and enable Refresh Timing Register

mov.w r5,#RFSH ; R5 points to RFSH MMR.

mov.b [r5],#0ffh ; Generate refresh request every RFSH[6:0] * 8 =

; 1024 system clock cycles. RFSH[7] = 1 enables

; refresh.

;** Lock all Memory Bank Configuration Locks

mov.w r5,#MBCL ; R5 points to MBCL MMR

mov.b [r5],#3Fh ; Set MBCL bits for Banks 5 - 0.

;**********************************************************************************

; The next 7 lines copy the entire block of code (00000h through CodeMover) from

; the Flash device into the DRAM. Code Memory addresses for the movc instruction

; are formed one of two ways, depending on the state of the RiSEG bit in the SSEL

; Register, where Ri is the pointer register being used in the movc instruction.

;

; Case 0: RiSEG = 0. Address = [High Byte of PC][16-bit address pointed to by Ri].

; Case 1: RiSEG = 1. Address = [CS][16-bit address pointed to by Ri].

;

; In the example code below, R0SEG = 0 from above. It would be safer to write

; CS = 00h and R0SEG = 1 before executing this loop. R5 and R6 still point into the

; Extra Segment (R5SEG = R6SEG = 1, from above).

;**********************************************************************************

mov.b ES,#DRAM ; Make Extra Segment point to DRAM.

Appendix : Set Up SCC3/DMA3 for Async Mode (C) 295

Set Up SCC3/DMA3 for Async Mode (C)

mov.w r5,#0000h ; Starting offset into DRAM = 0.

mov.w r0,#0000h ; Starting offset into Code = 0.

copy: movc.w r1,[r0+] ; Move a word from @R0 (Flash) into R1, then

; increment R0.

mov.w [r5+],r1 ; Move the word into @R5 (DRAM), then increment

; R5.

cmp.w r0,#CodeMover ; Does R0 point to beginning of CodeMover?

bcs copy ; If no, loop again.

jmp SWAP ; If yes, code transfer done, jump unconditionally to

; SWAP.

end ; End of assembly code.

A.3 Set Up SCC3/DM A3 for Async Mode (C)

The C code below sets up SCC3 (and DMA3) for Asynchronous Mode operation with 8

data bits, 1 stop bit, no parity, and 9600 bps.

The frequency of C Clk is 29.4912 MHz. so the BRGTC calculation goes like this:

PClk = CClk / 2 = 14.7456 MHz. = (9600)(16)(96) Hz. Therefore, use 16x Clock mode

(divide by 16 ) and BRGTC = 2Eh (divide by 96).

Program execution for this example proceeds in the following manner:

• Set up the Asynchronous mode parameters for SCC3.

• Set up clocking scheme for SCC3.

• Program and enable Baud Rate Generator.

• Enable SCC3 Rx and Tx.

• Set up a 4096-byte circular buffer based at 001000h for Tx DMA3.

• Set up a 4096-byte circular buffer based at 002000h for Rx DMA3.

• Enable Rx DMA3 in Periodic Interrupt mode, with an interrupt every 100 received

bytes.

• Enable Tx DMA3 in Stop On TC mode, with a Byte Count of 10.

//*********************************************************************************

MMR.scc[SCC3].wr4 = 0xC0; // WR4 = 11000000 selects 16x Clock Mode.

MMR.scc[SCC3].wr4 |= 0x04; // WR4 = 11000100 selects Async Mode, 1 stop

// bit, parity disabled.

MMR.scc[SCC3].wr1 = 0x00; // WR1 = 00000000, all interrupts disabled.

MMR.scc[SCC3].wr3 = 0xC0; // WR3 = 11000000 selects 8 Rx Bits/Character.

MMR.scc[SCC3].wr5 = 0x60; // WR5 = 01100000 selects 8 Bits/Tx Character.

MMR.scc[SCC3].wr14 = 0x02; // WR14 = 00000010 selects PClk for BRG source.

MMR.scc[SCC3].wr0 = 0x00; // WR0[0] = 0 bypasses 7/8 prescaler.

MMR.scc[SCC3].wr12 = 0x2E; // BRGTC low byte = 2Eh.

296 Appendix A: XA-SCC Pro

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Examples

Set Up SCC3/DMA3 for Async Mode (C)

MMR.scc[SCC3].wr13 = 0x00; // BRGTC high byte = xxxxxx00.

MMR.scc[SCC3].wr14 |= 0x01; // Setting WR14[0] = 1 enables Baud Rate

// Generator.

MMR.scc[SCC3].wr11 = 0x50; // WR11[6:5] = WR11[4:3] = 10 selects BRGOut

// for RxClk and TxClk respectively.

MMR.scc[SCC3].wr15 = 0x05; // WR15 = 00000101, External/Status IE bits not

// enabled. Bits 2 and 0 reserved, must be

// written ‘1’.

MMR.scc[SCC3].wr3 |= 0x01; // Setting WR3[0] = 1 enables Receiver.

MMR.scc[SCC3].wr5 |= 0x08; // Setting WR5[3] enables Transmitter.

MMR.scc[SCC3].wr0 |= 0x10; // WR0[5:3] = 010 issues the Reset

// External/Status Interrupts command.

MMR.scc[SCC3].wr0 |= 0x10; //Please see the note in Section A.8.

MMR.scc[SCC3].wr0 |= 0x30; // WR0[5:3] = 110 issues Error Reset command.

//*********************************************************************************

// Set up a 4096-byte circular buffer with base address 001000h for use by Tx DMA

// Segment Reg. = 0h, Buffer Base Reg. = 10h, Buffer Bound Reg. = 2000h

//*********************************************************************************

MMR.Tx_DMA[SCC3].txcon = 0x14; // Tx3 DMA Control Reg. = 00010100. Bits[6:5]

// = 00 disables DMA3 Tx interrupts. Bit[4]

// = 1 because Tx SCC in Async Mode. Bit[3]

// = 0 allows auto-increment. Bit[2] = 1

// enables circular buffer. Bits[1:0] = 00 is

// DMA Stopped.

MMR.Tx_DMA[SCC3].txseg = 0x00; // Tx3 DMA Segment Reg. = 00h is A23-A16 of

// all circular buffer addresses.

MMR.Tx_DMA[SCC3].txbufbase = 0x10; // Tx3 DMA Buffer Base Reg. = 10h is A15-A8 of

// circular buffer base address.

MMR.Tx_DMA[SCC3].txaddptr = 0x1000; // Tx3 DMA Address Pointer Reg. = 1000h. Start

// at bottom of circular buffer.

MMR.Tx_DMA[SCC3].txbufbound = 0x2000; // Tx3 DMA Buffer Bound Reg. = 2000 is A15-A0

// of circular buffer top address (plus 1).

//*********************************************************************************

// Set up a 4096-byte circular buffer with base address 002000h for use by Rx DMA

// Segment Reg. = 00h ... Buffer Base Reg. = 20h ... Buffer Bound Reg. = 3000h

//*********************************************************************************

MMR.Rx_DMA[SCC3].rxcon = 0x04; // Rx3 DMA Control Reg. = 00000100. Bits[6:5] =

// 00 disables DMA3 Rx interrupts. Bit[4] = 0

// selects Rx 1Byte Mode. Bit[3] = 0 allows

// auto-increment. Bit[2] = 1 enables circular

// buffer.

// Bits[1:0] = 00 is DMA Stopped.

MMR.Rx_DMA[SCC3].rxseg = 0x00; // Rx3 DMA Segment Reg. = 00h is A23-A16 of

// all circular buffer addresses.

MMR.Rx_DMA[SCC3].rxbufbase = 0x20; // Rx3 DMA Buffer Base Reg. = 20h is A15-A8 of

// circular buffer base address.

MMR.Rx_DMA[SCC3].rxaddptr = 0x2000; // Rx3 DMA Address Pointer Reg. = 2000h. Start

// at bottom of circular buffer.

Appendi x : Set Up IDL (C ) 297

Set Up IDL (C)

MMR.Rx_DMA[SCC3].rxbufbound = 0x3000; // Rx3 DMA Buffer Bound Reg. = 3000 is A15-A0

// of circular buffer top address (plus 1).

//***********************************************************************************

// Enable Rx DMA in Periodic Interrupt mode, and Tx DMA in Stop On TC mode.

//*********************************************************************************

MMR.Rx_DMA[SCC3].rxcount = 100; // Rx3 DMA Byte Count Reg. = 100d for periodic

// interrupt every 100 Rx Bytes.

MMR.Tx_DMA[SCC3].txcount = 10; // Tx3 DMA Byte Count Reg. = 10d to transmit 10

// bytes from buffer.

MMR.Tx_DMA[SCC3].txcon |= 0x63; // Set bits[6:5] and [1:0] of Tx3 DMA Control

// Reg. Bits[6:5] = 11 enables Tx interrupt and

// steers it to DMAH. Bits[1:0] = 11 enables Tx

// DMA in Stop on TC mode.

MMR.Rx_DMA[SCC3].rxcon |= 0x42; // Set bit [6] and bit [1] of Rx3 DMA Control

// Reg. Bits [6:5] = 10 enables Rx interrupt and

// steers it to DMAL. Bits[1:0] = 10 enables Rx

// DMA in Periodic Interrupt mode.

A.4 Set Up IDL (C)

The following three functions are uncompiled, untested C code, which are called by the

examples in Sections A.5 and A.7. At the time of this writing, no hardware was available

upon which to tes t this code. These functions should be used as illustrative examples

only.

//*********************************************************************************

// Function PinProgIDL

// This function configures the pins associated with the eight IDL Bus Signals,

// Pins 96, 95, 93, 94, 90, 92, 91, 97.

// This function takes no parameters and returns no value.

// The data writes in this example may be combined into fewer instructions. They are

// broken out into individual instructions here for illustrative purposes only.

//*********************************************************************************

void PinProgIDL()

{

// Pin 96 needs no configuration to output L1TxD.

// Pin 97 needs no configuration to input L1RxD.

// Configure Pin 95 for Hi-Z to input L1Clk. Write P0CFGB/A[5] = 1/0.

P0CFGB |= 0x20; // Set P0CFGB[5] = 1

P0CFGA &= 0xDF; // Clear P0CFGA[5] = 0

// Configure Pin 93 for Hi-Z to input L1SY1. Write P0CFGB/A[3] = 1/0.

P0CFGB |= 0x08; // Set P0CFGB[3] = 1

P0CFGA &= 0xF7; // Clear P0CFGA[3] = 0

298 Appendix A: XA-SCC Pro

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Examples

Set Up IDL (C)

// Configure Pin 94 for Push-Pull to output SDS1. Write P0CFGB/A[4] = 1/1.

// Also write P0[4] = 1 to enable Pin 94 AND driver.

P0CFGB |= 0x10; // Set P0CFGB[4] = 1.

P0CFGA |= 0x10; // Set P0CFGA[4] = 1.

P0 |= 10h; // Set P0[4] = 1.

// Configure Pin 90 for Push-Pull to output SDS2. Write P0CFGB/A[0] = 1/1.

// Also write P0[0] = 1 to enable Pin 90 AND driver.

P0CFGB |= 0x01; // Set P0CFGB[0] = 1.

P0CFGA |= 0x01; // Set P0CFGA[0] = 1.

P0 |= 01h; // Set P0[0] = 1.

// Configure Pin 92 for Hi-Z to input L1GR. Write P0CFGB/A[2] = 1/0.

P0CFGB |= 0x04; // Set P0CFGB[2] = 1.

P0CFGA &= 0xFB; // Clear P0CFGA[2] = 0.

// Configure Pin 91 for Push-Pull to output L1RQ. Write P0CFGB/A[1] = 1/1.

// Also write P0[1] = 1 to enable Pin 91 AND driver.

P0CFGB |= 0x02; // Set P0CFGB[1] = 1.

P0CFGA |= 0x02; // Set P0CFGA[1] = 1.

P0 |= 0x02; // Set P0[1] = 1.

// Write zeros to Pin Mux Control Register Bits[5:4]. Bit[5] = 0 enables GPI/O P1[1]

// to use Pin 69 as an output (if desired). Bit[4] = 1 enables GPI/O P3[6] to use

// Pin 66 as an output (if desired).

PinMuxCon &= 0xCf; // Clear Pin Mux Control[5:4] = 00.

Return;

}

//*********************************************************************************

// Function ConfigIDL

// This function sets up the IDL Interface in the following configuration:

// * 10-Bit Frame IDL Format

// * SDS2 assigned to B2, and SDS1 assigned to B1

// * B2 assigned to SCC2, and B1 assigned to SCC1

// * DataMask = FFFFh

// * D channel will be assigned to SCC0 later, leaving the IDL ‘Off’ for now.

// This function takes no parameters and returns no value.

// The data writes in this example may be combined into fewer instructions. They are

// broken out into individual instructions here for illustrative purposes only.

//*********************************************************************************

void ConfigIDL()

{

MSIControl &= 0x3FFF; // Bits[15:14] = 00, reserved.

MSIControl &= 0xDFFF; // Bit[13] = 0, 10-Bit Frame IDL Format.

MSIControl |= 0x1000; // Bit[12] = 1, B2 Enabled.

MSIControl |= 0x0800; // Bit 11] = 1, B1 Enabled.

Appendi x : Set Up SCC1 /DMA1 fo r Clear Channel with ID L (C) 299

Set Up SCC1/DMA 1 for C lear Ch annel w ith IDL ( C)

MSIControl &= 0xFBFF; // Bit[10] = 0, SDS2 assigned to B2.

MSIControl &= 0xFDFF; // Bit[9] = 0, SDS1 assigned to B1.

MSIControl |= 0x0100; // Bit[8] = 1, SCC2 connected to IDL (SC2isIDL).

MSIControl |= 0x0080; // Bit[7] = 1, SCC1 connected to IDL (SC1isIDL).

MSIControl |= 0x0040; // Bits[6:5] = 10, B2 assigned to SCC2...

MSIControl &= 0xFFDF; // ...continued.

MSIControl &= 0xFFEF; // Bits[4:3] = 01, B1 assigned to SCC1...

MSIControl |= 0x0008; // ...continued.

// Assigning D Channel to SCC0 also turns IDL on. Don’t do it yet.

DataMask = 0xFFFF; // Set all DataMask Register bits.

Return;

}

//*********************************************************************************

// Function StartIDL

// This function assigns the D Channel to SCC0 by writing MSIControl[2:0] = 100.

// This data write also turns on the IDL Interface.

// This function takes no parameters and returns no value.

//*********************************************************************************

void StartIDL()

{

MSIControl |= 0x0004; // Bit[2] = 1.

MSIControl &= 0xFFFC; // Bits[1:0] = 00.

Return;

}

A.5 Set Up SCC1/DMA1 for Clear Channel with IDL (C)

The C code below sets up SCC1 (and DMA1) for Clear Channel operation, using the

RTClk1 and TRClk1 clocks from the IDL Interface. Program execution for this example

proceeds as follows:

• Call functi on PinProgIDL.

• Call function ConfigIDL.

• Set up SCC1 in External Sync mode.

• Set up clock structure for SCC1.

• Enter Hunt Mode, and enable SCC1 Rx and Tx.

• Force Sync inpu t active.

• Set up a 4096-byte circular buffer based at 001000h for Tx DMA1.

• Set up a 4096-byte circular buffer based at 002000h for Rx DMA1.

• Enable Tx and Rx DMA1 in Periodic Interrupt mode, for an interrupt every 100 bytes.

• Call function StartIDL.

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Set U p SCC1/ DMA1 for Clear Channe l with ID L (C)

//*********************************************************************************

PinProgIDL(); // Call function PinProgIDL.

ConfigIDL(); // Call function ConfigIDL.

MMR.scc[SCC1].wr1 = 0x00; // WR1 = 00h disables all SCC1 interrupts.

MMR.scc[SCC1].wr3 = 0xC0; // WR3 = 11000000 selects 8 Rx Bits/Character,

// no Rx Enable.

MMR.scc[SCC1].wr5 = 0x60; // WR5 = 01100000 selects 8 Tx Bits/Character,

// no Tx Enable.

MMR.scc[SCC1].wr6 = 0xFF; // WR6 = FF: Single byte Sync Character

// (not used).

MMR.scc[SCC1].wr7 = 0xFF; // WR7 = FF: High byte of 2-byte Sync Character

// (not used).

MMR.scc[SCC1].wr4 = 0x30; // WR4 = 00110000 selects 1x Clock mode,

// External Sync Mode, and Synchronous Modes

// enable.

MMR.scc[SCC1].wr11 = 0x08; // WR11 = 00001000. Bits[6:5] = 00 selects

// RClk to be RxClk. Bits[4:3] = 01 selects

// TRClk to be TxClk. Bits[1:0] = 00 forces BRG1

// high.

MMR.scc[SCC1].wr12 = 0x00; // BRG not used.

MMR.scc[SCC1].wr13 = 0x00; // BRG not used.

MMR.scc[SCC1].wr15 = 0x00; // All External/Status Interrupts disabled.

MMR.scc[SCC1].wr3 |= 0x11; // WR3[4] = 1 issues Enter Hunt Mode command.

// WR3[0] = 1 Enables Receiver.

MMR.scc[SCC1].wr5 |= 0x08; // WR5[3] = 1 Enables Transmitter.

MMR.scc[SCC1].wr8 = 0xFF; // Write FFh to Tx Data Buffer (WR8).

MMR.scc[SCC1].wr0 |= 0x10; // WR0[5:3] = 010 issues Reset External/Status

// Interrupts command. Please see the note in

MMR.scc[SCC1].wr0 |= 0x10; // Section A.8.

MMR.scc[SCC1].wr0 |= 0x30; // WR0[5:3] = 110 issues Error Reset command.

MMR.scc[SCC1].wr0 |= 0x04; // WR0[2] = 1 forces Sync input active.

//*********************************************************************************

// Set up a 4096-byte circular buffer with base address 001000h for use by Tx DMA

// Segment Reg. = 00h ... Buffer Base Reg. = 10h ... Buffer Bound Reg. = 2000h

//*********************************************************************************

MMR.Tx_DMA[SCC1].txcon = 0x04; // Tx1 DMA Control Reg. = 00000100. Bits[6:5]

// = 00 disables DMA1 Tx interrupts. Bit[4]

// = 0 because Tx SCC in Synchronous mode.

// Bit[3] = 0 allows auto-increment. Bit[2] = 1

// enables circular buffer. Bits[1:0] = 00 is

// DMA Stopped.

MMR.Tx_DMA[SCC1].txseg = 0x00; // Tx1 DMA Segment Reg. = 00h is A23-A16 of

// all circular buffer addresses.

MMR.Tx_DMA[SCC1].txbufbase = 0x10; // Tx1 DMA Buffer Base Reg. = 10h is A15-A8 of

// circular buffer base address.

MMR.Tx_DMA[SCC1].txaddptr = 0x1000; // Tx1 DMA Address Pointer Reg. = 1000h. Start

Appendi x : Set Up SCC1 /DMA1 fo r Clear Channel with ID L (C) 301

Set Up SCC1/DMA 1 for C lear Ch annel w ith IDL ( C)

// at bottom of circular buffer.

MMR.Tx_DMA[SCC1].txbufbound = 0x2000; // Tx1 DMA Buffer Bound Reg. = 2000 is A15-A0

// of circular buffer top address (plus 1).

MMR.Tx_DMA[SCC1].txcount = 100; // Tx1 DMA Byte Count Reg. = 100d for periodic

// interrupt every 100 Tx bytes.

//*********************************************************************************

// Set up a 4096-byte circular buffer with base address 002000h for use by Rx DMA

// Segment Reg. = 00h ... Buffer Base Reg. = 20h ... Buffer Bound Reg. = 3000h

//*********************************************************************************

MMR.Rx_DMA[SCC1].rxcon = 0x04; // Rx1 DMA Control Reg. = 00000100. Bits[6:5]

// = 00 disables DMA1 Rx interrupts. Bit[4] = 0

// selects Rx 1Byte Mode. Bit[3] = 0 allows

// auto-increment. Bit[2] = 1 enables circular

// buffer. Bits[1:0] = 00 is DMA Stopped.

MMR.Rx_DMA[SCC1].rxseg = 0x00; // Rx1 DMA Segment Reg. = 00h is A23-A16 of

// all circular buffer addresses.

MMR.Rx_DMA[SCC1].rxbufbase = 0x20; // Rx1 DMA Buffer Base Reg. = 20h is A15-A8 of

// circular buffer base address.

MMR.Rx_DMA[SCC1].rxaddptr = 0x2000; // Rx1 DMA Address Pointer Reg. = 2000h. Start

// at bottom of circular buffer.

MMR.Rx_DMA[SCC1].rxbufbound = 0x3000; // Rx1 DMA Buffer Bound Reg. = 3000 is A15-A0

// of circular buffer top address (plus 1).

MMR.Rx_DMA[SCC1].rxcount = 100; // Rx Byte Count Reg. = 100d for periodic

// interrupt every 100 received bytes.

//*********************************************************************************

// Enable Rx DMA and Tx DMA in Periodic Interrupt mode.

//*********************************************************************************

MMR.Rx_DMA[SCC1].rxcon |= 0x02; // Write 10 to Rx DMA Control[1:0]. Starts Rx

// DMA in Periodic Interrupt mode.

MMR.Tx_DMA[SCC1].txcon |= 0x02; // Write 10 to Tx DMA Control[1:0]. Starts

// Tx DMA in Periodic Interrupt mode.

StartIDL(); // Call function StartIDL.

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Set Up SC C3/DM A3 for Cl ear Ch annel wi th NMSI ( C)

A.6 Set Up SCC3/DMA3 for Clear Channel with NMSI (C)

The C code below sets up SCC3 (and DMA3) for Clear Channel operation at 64K bps,

using ComClk as the master clock source. The frequency of ComClk is assumed to be

512 KHz, so the BRGTC calculati on goes like this:

With the 7/8 Prescaler bypassed, BRGClk = ComClk = 512 KHz. Also, BRGOut = 64

KHz. Therefore

Program execution for this example proceeds as follows:

• Set up SCC3 in External Sync mode.

• Set up SCC3 clock structure.

• Program and enable Baud Rate Generator.

• Ente r Hunt mode.

• Enable SCC3 Tx and Rx.

• Force RTS output active.

• Force Sync inpu t active.

• Set up a 4096-byte circular buffer based at 001000h for Tx DMA3.

• Set up a 4096-byte circular buffer based at 002000h for Rx DMA3.

• Enable Tx and Rx DMA3 in Periodic Interrupt mode, for an interrupt every 100 bytes.

//*********************************************************************************

MMR.scc[SCC3].wr0 = 0x00; // Bypass 7/8 Prescaler, issue no other

// commands.

MMR.scc[SCC3].wr11 = 0x52; // WR11 = 01010010. Bits[6:5] = 10 select

// BRGOut to be RxClk. Bits[4:3] = 10 select

// BRGOut to be TxClk. Bits[1:0] = 10 select

// BRGOut to appear on BRG3.

MMR.scc[SCC3].wr4 = 0x00; // Selects 1x Clock mode, Monosync mode

// (for now), Synchronous modes enabled, and

// Parity disabled.

MMR.scc[SCC3].wr1 = 0x00; // Disable all SCC3 interrupts.

MMR.scc[SCC3].wr3 = 0xC0; // WR3 = 11000000 selects 8 Rx Bits/Character,

// no Receiver Enable.

MMR.scc[SCC3].wr5 = 0x60; // WR5 = 01100000 selects 8 Tx Bits/Character,

// no Transmitter Enable.

MMR.scc[SCC3].wr6 = 0xFF; // (Not being used) Monosync mode Sync Char

MMR.scc[SCC3].wr7 = 0xFF; // (Not being used) Bisync mode Sync Char High

MMR.scc[SCC3].wr4 |= 0x30; // Setting WR4[5:4] = 11 selects External Sync

// mode.

BRGTC BRGClk

2 BRGOut

()

----------------------------- 2– 524 288,

265536

,()

--------------------------2–2===

Appendi x : Set Up SCC3 /DMA3 fo r Clear Channel with N MSI (C) 303

Set Up SCC3/DMA3 for Clear Channel with NMSI (C)

MMR.scc[SCC3].wr12 = 0x02; // BRGTC low byte

MMR.scc[SCC3].wr13 = 0x00; // BRGTC high byte

MMR.scc[SCC3].wr14 = 0x01; // WR14[1] = 0 selects RClk as input to BRG

// (later, ComClk will be chosen for RClk).

// WR14[0] = 1 enables BRG.

MMR.scc[SCC3].wr15 = 0x00; // All External/Status IE bits disabled.

MMR.scc[SCC3].wr3 |= 0x11; // Setting WR3[4] issues Enter Hunt Mode

// command, setting WR3[0] enables Receiver.

MMR.scc[SCC3].wr5 |= 0x0A; // Setting WR5[3] enables transmitter, setting

// WR5[1] forces the RTS output low.

MMR.scc[SCC3].wr8 = 0xFF; // Write FF to Tx Data Buffer; send mark for

// now.

MMR.scc[SCC3].wr0 |= 0x12; // WR0[5:3] = 010 issues Reset External Status

// Interrupts command. Setting WR0[1] = 1

// selects ComClk to be RClk.

MMR.scc[SCC3].wr0 |= 0x10; // Issue Reset External/Status Interrupts

// command again. Please see the note in

MMR.scc[SCC3].wr0 |= 0x10; // Section A.8.

MMR.scc[SCC3].wr0 |= 0x30; // WR0[5:3] = 110 issues Error Reset command.

MMR.scc[SCC3].wr0 |= 0x04; // Setting WR0[2] = 1 forces Sync input active.

//*********************************************************************************

// Set up a 4096-byte circular buffer with base address 001000h for use by Tx DMA*/

// Segment Reg. = 00h ... Buffer Base Reg. = 10h ... Buffer Bound Reg. = 2000h

//*********************************************************************************

MMR.Tx_DMA[SCC3].txcon = 0x04; // Tx3 DMA Control Reg. = 00000100.

// Bits[6:5] = 00 disables DMA3 Tx interrupts.

// Bit[4] = 0 because Tx SCC in Synchronous

// mode. Bit[3] = 0 allows auto-increment.

// Bit[2] = 1 enables circular buffer.

// Bits[1:0] = 00 is DMA Stopped.

MMR.Tx_DMA[SCC3].txseg = 0x00; // Tx3 DMA Segment Reg. = 00h is A23-A16 of

// all circular buffer addresses.

MMR.Tx_DMA[SCC3].txbufbase = 0x10; // Tx3 DMA Buffer Base Reg. = 10h is A15-A8 of

// circular buffer base address.

MMR.Tx_DMA[SCC3].txaddptr = 0x1000; // Tx3 DMA Address Pointer Reg. = 1000h.

// Start at bottom of circular buffer.

MMR.Tx_DMA[SCC3].txbufbound = 0x2000; // Tx3 DMA Buffer Bound Reg. = 2000 is A15-A0

// of circular buffer top address (plus 1).

MMR.Tx_DMA[SCC3].txcount = 100; // Tx3 DMA Byte Count Reg. = 100d for periodic

// interrupt every 100 Tx Bytes.

//*********************************************************************************

// Set up a 4096-byte circular buffer with base address 002000h for use by Rx DMA

// Segment Reg. = 00h ... Buffer Base Reg. = 20h ... Buffer Bound Reg. = 3000h

//*********************************************************************************

MMR.Rx_DMA[SCC3].rxcon = 0x04; // Rx3 DMA Control Reg. = 00000100.

// Bits[6:5] = 00 disables DMA3 Rx interrupts.

// Bit[4] = 0 selects Rx 1Byte Mode. Bit[3] = 0

// allows auto-increment. Bit[2] = 1 enables

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Set Up SCC 0/DMA0 for HDLC Tx Chain ing with IDL (C)

// circular buffer. Bits[1:0] = 00 is DMA

// Stopped.

MMR.Rx_DMA[SCC3].rxseg = 0x00; // Rx3 DMA Segment Reg. = 00h is A23-A16 of

// all circular buffer addresses.

MMR.Rx_DMA[SCC3].rxbufbase = 0x20; // Rx3 DMA Buffer Base Reg. = 20h is A15-A8 of

// circular buffer base address.

MMR.Rx_DMA[SCC3].rxaddptr = 0x2000; // Rx3 DMA Address Pointer Reg. = 2000h.

// Start at bottom of circular buffer.

MMR.Rx_DMA[SCC3].rxbufbound = 0x3000; // Rx3 DMA Buffer Bound Reg. = 3000 is A15-A0

// of circular buffer top address (plus 1).

MMR.Rx_DMA[SCC3].rxcount = 100; // Rx DMA Byte Count Reg. = 100d for periodic

// interrupt every 100 Rx bytes.

//*********************************************************************************

// Start DMA

//*********************************************************************************

MMR.Rx_DMA[SCC3].rxcon |= 0x02; // Rx DMA Control[1:0] = 10 starts Rx DMA in

// Periodic Interrupt mode.

MMR.Tx_DMA[SCC3].txcon |= 0x02; // Tx DMA Control[1:0] = 10 starts Tx DMA in

// Periodic Interrupt mode.

A.7 Set Up SCC0/DMA0 for HDLC Tx

Chaining with IDL (C)

The C code below sets up SCC0 (and DMA0) for SDLC/HDLC Tx Chaining mode

operation, using the RTClk0 and TRClk0 clocks from the IDL Interface. Program

execution for this example proceeds as f ollows:

• Call functi on PinProgIDL.

• Call function ConfigIDL.

• Set up SCC0 for 8 Data Bits, LSB First, Right Justified, SDLC/HDLC mode with CRC

preset and enabled.

• Store the SDLC/HDLC Flag character in WR7.

• Select clocking structure and disable BRG.

• Enter Hunt mode, and enable SCC0 Rx and Tx.

• Set up circular buffers for Rx and Tx DMA0.

• Start Rx DMA0 in SDLC/HDLC mode, and Tx DMA0 in Tx Chaining Mode.

• Call function StartIDL.

//*********************************************************************************

PinProgIDL(); // Call function PinProgIDL.

ConfigIDL(); // Call function ConfigIDL.

//MMR.scc[SCC0].wr9 = 0x08; // WR9[3] = 1 is Master Interrupt Enable for

// SCC0/SCC1 interrupt group.

Appendi x : Set Up SCC0 /DMA0 fo r HDLC Tx Chainin

with I DL (C) 305

Set Up SCC0/DMA 0 for H DLC Tx C haining with ID L (C)

//MMR.scc[SCC0].wr1 |= 0x18; // WR1[4:3] = 11 selects Rx Interrupt on

// Special Conditions Only.

MMR.scc[SCC0].wr3 = 0xC8; // WR3 = 11001000. Bits[7:6] = 11 selects

// 8 Bits/Rx Character. Bit[3] = 1 enables Rx

// CRC.

MMR.scc[SCC0].wr5 = 0x61; // WR5 = 01100001. Bits[6:5] = 11 selects

// 8 Bits/Tx Character. Bit[0] = 1 enables Tx

// CRC.

MMR.scc[SCC0].wr6 = 0x00; // WR6 holds the SDLC/HDLC Address field.

MMR.scc[SCC0].wr7 = 0x7E; // Store the SDLC/HDLC Flag character in WR7.

MMR.scc[SCC0].wr7p = 0x23; // WR7P (WR2) = 00100011. Bits[7:5] are

// reserved, must be 001. Always set bits[1:0]

// = 11 for SDLC/HDLC operation with DMA.

MMR.scc[SCC0].wr10 = 0x88; // WR10 = 10001000. Bit[7] = 1 presets CRC

// checker and generator to all ones.

// Bit[3] = 1 selects SDLC/HDLC Mark Idle.

MMR.scc[SCC0].wr4 |= 0x20; // WR4 = 00100000. Bits[7:6] = 00 selects

// 1x Clock mode. Bits[5:4] = 10 selects

// SDLC/HDLC mode. Bits[3:2] = 00 is

// Synchronous modes enable.

MMR.scc[SCC0].wr11 = 0x08; // WR11 = 00001000. Bits[6:5] = 00 sends RClk

// to RxClk (RTClk0 is sent to RClk later).

// Bits[4:3] = 01 sends TRClk0 to TxClk. Bits

// [1:0] = 00 forces BRG0 = 1.

MMR.scc[SCC0].wr12 = 0x00; // BRG not used.

MMR.scc[SCC0].wr13 = 0x00; // BRG not used.

MMR.scc[SCC0].wr14 = 0x00; // Bit [7] = 0 selects LSB first. Bit [6] = 0

// selects Right Justified.

MMR.scc[SCC0].wr15 = 0x00; // All External/Status IE bits disabled.

MMR.scc[SCC0].wr3 |= 0x11; // Writing WR3[4] = 1 issues Enter Hunt Mode

// command. WR3[0] = 1 is Receiver Enable.

MMR.scc[SCC0].wr5 |= 0x08; // WR5[3] = 1 is Transmitter Enable.

MMR.scc[SCC0].wr0 |= 0x10; // WR0[5:3] = 010 issues Reset External/Status

// Interrupts command.

MMR.scc[SCC0].wr0 |= 0x10; // Please see the note in Section A.8.

MMR.scc[SCC0].wr0 |= 0x30; // WR0[5:3] = 110 issues Error Reset command.

//*********************************************************************************

/* Set up a 4096-byte circular buffer with base address 001000h for use by Tx DMA

// Segment Reg. = 00h ... Buffer Base Reg. = 10h ... Buffer Bound Reg. = 2000h

//*********************************************************************************

MMR.Tx_DMA[SCC0].txcon = 0x04; // Tx0 DMA Control Reg. = 00000100.

// Bits[6:5] = 00 disables DMA0 Tx interrupts.

// Bit[4] = 0 because Tx SCC in Synchronous

// mode. Bit[3] = 0 allows auto-increment.

// Bit[2] = 1 enables circular buffer.

// Bits[1:0] = 00 is DMA Stopped.

MMR.Tx_DMA[SCC0].txseg = 0x00; // Tx0 DMA Segment Reg. = 00h is A23-A16 of

// all circular buffer addresses.

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Examples

Set Up SCC 0/DMA0 for HDLC Tx Chain ing with IDL (C)

MMR.Tx_DMA[SCC0].txbufbase = 0x10; // Tx0 DMA Buffer Base Reg. = 10h is A15-A8 of

// circular buffer base address.

MMR.Tx_DMA[SCC0].txaddptr = 0x1000; // Tx0 DMA Address Pointer Reg. = 1000h. Start

// at bottom of circular buffer.

MMR.Tx_DMA[SCC0].txbufbound = 0x2000; // Tx0 DMA Buffer Bound Reg. = 2000 is A15-A0

// of circular buffer top address (plus 1).

MMR.Tx_DMA[SCC0].txcount = 0; // Not used. Load Tx DMA Byte Count Reg. = 00h.

//*********************************************************************************

// Set up a 4096-byte circular buffer with base address 002000h for use by Rx DMA

// Segment Reg. = 00h ... Buffer Base Reg. = 20h ... Buffer Bound Reg. = 3000h

// Also, enable DMA Rx Interrupt. Then, DMA0 will generate an Rx Interrupt after

// storing each packet in memory.

//*********************************************************************************

MMR.Rx_DMA[SCC0].rxcon = 0x54; // Rx0 DMA Control Reg. = 01010100. Bits[6:5] =

// 10 enables DMA0 Rx interrupt, steers to

// DMAL. Bit[4] = 1 selects Rx 2Byte Mode.

// Bit[3] = 0 allows auto-increment. Bit[2] = 1

// enables circular buffer. Bits[1:0] = 00 is

// DMA Stopped.

MMR.Rx_DMA[SCC0].rxseg = 0x00; // Rx0 DMA Segment Reg. = 00h is A23-A16 of

// all circular buffer addresses.

MMR.Rx_DMA[SCC0].rxbufbase = 0x20; // Rx0 DMA Buffer Base Reg. = 20h is A15-A8 of

// circular buffer base address.

MMR.Rx_DMA[SCC0].rxaddptr = 0x2000; // Rx0 DMA Address Pointer Reg. = 2000h. Start

// at bottom of circular buffer.

MMR.Rx_DMA[SCC0].rxbufbound = 0x3000; // Rx0 DMA Buffer Bound Reg. = 3000 is A15-A0

// of circular buffer top address (plus 1).

MMR.Rx_DMA[SCC0].rxcount = 0; // Not used. Load Rx DMA Byte Count Reg. = 00h.

//*********************************************************************************

// Start Rx and Tx DMA channels

//*********************************************************************************

MMR.Rx_DMA[SCC0].rxcon |= 0x01; // Rx DMA Control[1:0] = 01 enables DMA Rx0 in

// SDLC/HDLC mode.

MMR.Tx_DMA[SCC0].txcon |= 0x01; // Tx DMA Control[1:0] = 01 enables DMA Tx0 in

// Tx Chaining mode.

StartIDL(); // Call function StartIDL.

Appendix : Note Ab out Reset Ext ernal/Statu s Interrupts Comman d 307

Note About Reset External/Status Interrupts Command

A.8 Note Abo ut

Reset External/St atus Interrup ts Command

The Reset External/Status Interrupts command was always issu ed at least twice

consecutively on the prototype. This may not be necessary with the final part, depending

on the frequency of CClk and the minimum time interval between potential External/

Status Interrupts for a given application.

At the time of this writing, the safest approach is to issue the command twice.

For details on th e op eration and timing of SCC External/Status Interrupts, please refer to

Section 5.7. 6.

308 Appendix A: XA-SCC Pro

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Note About Reset External/Status Interrupts Comman d

Appendix B: Bus Timin

Examples 309

Appendix B

Bus Timin

Exam

les B

Contents

B.1 SRAM (or other

eneric memory) Timin

Examples ................................................................................310

B.2 DRAM Timi n

Examples...........................................................................................................................325

310 Appendix B: Bus Timin

Examples

SRAM (or other generic memory) Timing Examples

B.1 SRAM (or other generic memory) Timing Examples

The timing examples in this appendix in tentionally omit A C tim ing parameters such as

setup time, hold time, etc. These examples are intended to demonstrate the effects of

changing MIF Bank Timing Register settings only. For AC timing d e tails, please refer to

the relevant XA-SCC data-sheets.

This section describes the accompanying SRAM timing diagrams, and will demonstrate

how the bits in the BiTMG Register affect a Generic Memory Interface Bank’s read and

write timing. Each “family” of bus cycles begins with the timing diagram for a “typical”

case. The typical case is then reprinted above each successive timing diagram for that

family, to demonstrate the effects of changing various bit values in the BiTMG Register.

For write cycles, the OE signal stays inactive (high), and is not shown. For read cycles,

the WE signal stays in active (high), and is n ot shown. Sin ce the timing is applicable to

any bank configured as a Generic Memory Interface, the subscript “i” will be omitted in

this discussion. For a Generic Memory Interface, the bits in the BTMG Register have the

following functions (see Section 3.12.3 for details):

Figure B-1 Typical SRAM 16-Bit Bus Read Cycle

This timing diagram depicts a typical SRAM 16-bit bus read cycle, using the fo llowing

BTMG Register settings:

BRWT = don’t care...not applicable for a read.

BCBL = 0...no C S to BLE/BHE delay.

76543210

BRWT BCBL BAC BEC BWEX

CS to WE

Delay

Data

Strobe

Delay Access Time Recovery Time Write

Exchange

ClkOut

12345678

BLE/BHE

Appendix : SRAM (or other

eneric memory) Timin

Ex ampl es 311

SRAM (or other generic memory) Timing Examples

BAC = 001...Access Time = 1 + 1 = 2 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = don’t care...not applicable for a read.

• On a rising edge of CLKOUT, the address is driven onto the Address Bus.

• One clock cycle after the address changes, CS and OE go active. BLE/BHE go active

on the same cycle (because BCBL = 0...no Data Strobe Delay) .

• The Data Bus is sampled on the rising edge of CLKOUT, 2 cycles later (because

Access Ti me = 2). At this point the read cycle is terminated as CS, BLE/BHE, and OE

are negated, and the Address and Data Busses begin to change.

• For at least 2 clock cycles after CS high (because Recovery Time = 2), no CS for any

bank will be asserted.

Figure B-2 SRAM 16-Bit Bus Read Cycle with Longer Access Time

The effect, on the typical SRAM 16-bit bus read cycle, of increasing the Access Time is

demonstrated by Figure B-2. For this example, only the following settin g was changed:

BAC = 010...Access Time = 3 clock cycles.

Notice that the length of BLE/BHE low to the Data Bus sample (and to BLE/BHE and

CS high) is now 3 clock cycles. Again, the next bus cycle may begin after the minimum

Recovery Time of 2 cycles has elapsed.

ClkOut

12345678

BLE/BHE

312 Appendix B: Bus Timin

Examples

SRAM (or other generic memory) Timing Examples

Figure B-3 SRAM 16-Bit Bus Read Cycle with CS to BLE/BHE Del ay

The effect, on the typical SRAM 16-bit bus read cycle, of changing the CS to BLE/BHE

delay, is demonstrated by Figure B-3. For this example, only the following settin g was

changed:

BCBL = 1...CS to BL E/BHE Delay = 1 clock cycle.

Notice that the assertion of BLE/BHE (and OE) comes one clock cycle after CS goes

active (because BCBL = 1). The length of the BLE/BHE (and OE) active strobe is still 2

clock cycles (because Access Time = 2), but the rising edge of CS has been delayed by

one clock cycle, and the strobes all terminate together. After a minimum 2 clock cycle

Recovery Time, the next bus cycle may begin.

BLE/BHE

ClkOut

12345678

BLE/BHE

Appendix : SRAM (or other

eneric memory) Timin

Ex ampl es 313

SRAM (or other generic memory) Timing Examples

Figure B-4 SRAM 16-Bit Bus Read Cycle with Longer Recovery Time

The effect, on the typical SRAM 16-bit bus read cycle, of increasing the Recovery Time,

is demonstrated by Figure B-4. For this example, only the following setting was changed:

BEC = 10...Recovery Time = 3 clock cycles.

Notice that the required minimum delay from CS high to CS low has been increased from

2 to 3 clock cycles.

Figure B-5 Typical SRAM 16-Bit Bus Write Cycle

BLE/BHE

ClkOut

12345678

BLE/BHE

ClkOut

12345678

BLE/BHE

314 Appendix B: Bus Timin

Examples

SRAM (or other generic memory) Timing Examples

This timing diagram depicts a typical SRAM write cycle on a 16-bit bus, using the

following BTMG R egister setting s:

BRWT = 0...no CS to WE delay.

BCBL = 0...no C S to BLE/BHE delay.

BAC = 001...Access Time = 1 + 1 = 2 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = 0...BLE/BHE are normal data strobes, not converted to WEL/WEH.

• On a rising edge of CLKOUT, the address is driven onto the Address Bus.

• One clock cycle later, CS goes active. BLE/BHE go active on the same cycle (because

BCBL = 0) and s o does WE. At this point, the data are driven onto the Data Bus.

• Two clock cycles later (because Access Time = 2) on the rising edge of CLKOUT, the

data are latched into memory by the rising edge of BLE/BHE. CS is also negated on

this cycle.

• One clock cycle later, WE is negated, terminating the write cycle, and the Address and

Data Busses change.

•No CS

for any bank will b e asserted for at least two clock cycles after the rising edge

of CS (because Recovery Time = 2).

Figure B-6 SRAM 16-Bit Bus Write Cycle with Longer Access Time

BLE/BHE

ClkOut

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BLE/BHE

Appendix : SRAM (or other

eneric memory) Timin

Ex ampl es 315

SRAM (or other generic memory) Timing Examples

The effect, on the typical SRAM 16-bit bus write cycle, of increasing the Access Time, is

demonstrated by Figure B-6. For this ex ample, th e following setting was changed:

BAC = 010...Access Time = 3 clock cycles.

Notice that the length of the data strobe, BLE/BHE low to BLE/BHE high, has been

increased to 3 cycles. This has the effect of delaying the rising edges of both CS and WE.

At least two clock cycles after CS goes high, the next bus cycle may begin.

Figure B-7 SRAM 16-Bit Bus Write Cycle with CS to BLE/BHE Delay

The effect, on the typical SRAM 16-bit bus write cycle, of changing the CS to BLE/BHE

delay, is demonstrated by Figure B-7. For this example, the following setting was

changed:

BCBL = 1...CS to BLE/BHE Delay = 1 clock cycle.

Notice that the assertion of BLE/BHE comes one clock cycle after CS goes active. The

length of the BLE/BHE active s trobe is st ill 2 clock cycles (because Access Time = 2),

but the rising edges of CS and WE have been delayed by one clock cycle. After a

minimum 2 clock cycle Recovery Time (CS high to CS low), the next bus cycle may

begin.

BLE/BHE

ClkOut

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BLE/BHE

316 Appendix B: Bus Timin

Examples

SRAM (or other generic memory) Timing Examples

Figure B-8 SRAM 16-Bit Bus Write Cycle with Longer Access Time and CS to

BLE/BHE Delay

The effect, on the typical SRAM 16-bit bus write cycle, of changing the Access Time and

the CS to BLE/BHE delay, is demonstrated by Figure B-8. For this example, the

following settings were changed:

BAC = 010...Access Time = 3

BCBL = 1...CS to BL E/BHE Dela y = 1.

Notice that the assertion of BLE/BHE comes one clock cy cle after C S goes active (BCBL

= 1), and that the length of the BLE/BHE active strobe is now 3 cycles (Access Time =

3). This has the effect of ex tending both the CS and WE active strobes. At least two clock

cycles after CS high, CS may be asserted again to begin the next bus cycle (Recovery

Time = 2 ).

BLE/BHE

ClkOut

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BLE/BHE

Appendix : SRAM (or other

eneric memory) Timin

Ex ampl es 317

SRAM (or other generic memory) Timing Examples

Figure B-9 SRAM 16-Bit Bus Write Cycle with CS to WE Delay

The effect, on the typical SRAM 16-bit bus write cycle, of changing the CS to WE delay,

is demonstrated by Figure B-9. For this example, the following setting was changed:

BRWT = 1...CS to WE Delay = 1 clock cycle.

Notice that the assertion of BLE/BHE is coincidental with CS active (BCBL = 0), but the

assertion of WE comes one clock cycle after CS active (BRWT = 1). The length of the

BLE/BHE active strobe is still 2 clock cycles (because Access Time = 2). After a

minimum 2 clock cycle Recovery Time (CS high to CS low), the next bus cycle may

begin.

BLE/BHE

ClkOut

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BLE/BHE

318 Appendix B: Bus Timin

Examples

SRAM (or other generic memory) Timing Examples

Figure B-10 SRAM 16-Bit Bus Write Cycle with CS to WE Delay and BLE/BHE

Conversion to WEL/WEH

The effect, on the typical SRAM 16-bit bus write cycle, of changing the CS to WE delay

and converting BLE/BHE to WEL/WEH, is demonstrated by Figure B-10. For this

example, the following settings were changed:

BRWT = 1...CS to WE Delay = 1 clock cycle

BWEX = 1...BLE/BHE converted to WEL/WEH.

Notice that BLE and BHE are asserted o ne clock cycle after CS, even though BCBL =

0. This is because BLE and BHE have been converted to WEL and WEH, and there is a

one cycle CS to WE delay. Also, BLE/BHE and WE terminate together, one cycle after

CS terminates. After a minimum 2 clock cycle Recovery Time (CS high to CS low), the

next bus cycle may begin.

BLE/BHE

ClkOut

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BLE/BHE

Appendix : SRAM (or other

eneric memory) Timin

Ex ampl es 319

SRAM (or other generic memory) Timing Examples

Figure B-11 SRAM 16-Bit Bus Write Cycle with Longer Recovery Time

The effect, on the typical SRAM 16-bit bus write cycle, of increasing the Recovery Time,

is demonstrated by Fig ure B-11. For this example, the followin g s e tting was changed:

BEC = 10...Recovery Time = 3 clock cycles.

Notice that the required minimum delay from CS high (at the termination of the write

cycle) to CS low again (at the start of the next bus cycle) has been increased from 2 to 3

clock cycles.

BLE/BHE

ClkOut

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BLE/BHE

320 Appendix B: Bus Timin

Examples

SRAM (or other generic memory) Timing Examples

Figure B-12 Typical SRAM Word Read Cycle on an 8-Bit Bus, or 2-Word Burst

Code Fetch on a 16-Bit Bus

This timing diagram depicts a typical SRAM Word Read cycle on an 8-bit bus, or a

typical Two-Word Burst Code Fetch on a 16-bit bus. The example uses the following

BTMG Register settings:

BRWT = 0...not applicable for a read.

BCBL = 0...no C S to BLE/BHE delay.

BAC = 001...Access Time = 1 + 1 = 2 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = 0...BLE/BHE are normal data strobes, not converted to WEL/WEH.

• On a rising edge of CLKOUT, the address is driven onto the Address Bus.

• One clock cycle later, CS goes active. BLE/BHE go active on the same cycle (because

BCBL = 0) and so does OE. Valid data begin to appear on the Data Bus.

• Two cycles after BLE /BHE (because Access Time = 2), on the rising edge of

CLKOUT, the Data Bu s is sampled, the address is incremented, and the Data Bus

changes.

• Two clock cycles later (because Access Time = 2), the second byte (or second word of

Code) is sampled from the Data Bus, and the simultaneous negation of CS, BLE/BHE,

and OE terminate the read cycle.

•No CS

will be asserted by any bank for at least two clock cycles after the rising edge

of CS (because Recovery Time = 2).

ClkOut

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BLE/BHE

Appendix : SRAM (or other

eneric memory) Timin

Ex ampl es 321

SRAM (or other generic memory) Timing Examples

Figure B-13 SRAM 8-Bit Bus Word Read Cycle with CS to BLE Delay

The ef fect, on the typ ical SRAM 8-b it bus word read cy cle, of addin g CS to BLE delay, is

demonstrated by Figure B-13. For this example, the following setting was changed:

BCBL = 1...CS to BL E delay = 1.

Notice that BLE (and OE) are asserted one clock cycle after CS (because BCBL = 1).

The first Byte is still sam pled from the Data Bus 2 clock cycles after BLE active, and the

second byte is still sampled 2 cycles later (because Access Time = 2).

ClkOut

12345678910

BLE/BHE

BLE

322 Appendix B: Bus Timin

Examples

SRAM (or other generic memory) Timing Examples

Figure B-14 Typical SRAM Word Write Cycle on an 8-Bit Bus

This timing diagram depicts a typical SRAM word write cycle on an 8-bit bus. The

example uses the following BTMG Register settings:

BRWT = 1...CS to WE delay = 1 clock cycle.

BCBL = 1...CS to BL E delay = 1 clock cycle.

BAC = 010...Access Time = 2 + 1 = 3 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = 0...BLE is normal data strobe, not converted to WEL.

• On a rising edge of CLKOUT, the address is driven onto the Address Bus.

• One clock cycle later, CS goes active, and valid data begin to appear on the Data Bus.

• One cycle after CS is asserted, BLE goes active (BCBL = 1), and so does WE (BRWT

= 1).

• Three cycles after BLE (because Access Time = 3), on the rising edge of CLKOUT,

the first Byte is latched into memory by the rising edge of BLE. Note: the WE strobe

is negated on the same clock as BLE, which differs from the 16-Bit Bus Write Cycle

timing.

• One clock cycle after BLE goes high, the address is incremented, and the Data Bus

changes.

• One clock cycle after the address changes, both BLE and WE are asserted again.

• Three clock cycles after BLE low (because Access Time = 3), the second byte is

latched into me mory by the rising edge of BLE. Also, CS and WE are negated, and the

write cycle is terminated.

• Address and Data will h ol d for one cloc k cycle after the negation of CS and BLE.

•No CS

for any bank will b e asserted for at least two clock cycles after the rising edge

of CS (because Recovery Time = 2).

ClkOut

1234567891011121314

BLE

Appendix : SRAM (or other

eneric memory) Timin

Ex ampl es 323

SRAM (or other generic memory) Timing Examples

Figure B-15 SRAM 8-Bit Bus Word Write Cycle with BLE converted to WEL

The effect, on the Typical SRAM 8-bit bus word write cycle, of converting BLE to WEL,

is demonstrated by Fig ure B-15. For this example, the following setting was changed:

BWEX = 1... BLE converted to WEL.

Notice that the timing is the same as in the ty pical SRAM 8-bit bus word write. In that

example, BLE and WE were both asserted one cycle after CS due to BCBL = 1 and

BRW T = 1. In this case, BLE is mimicking the behavior of WE regardless of the state of

the BCBL bit. If the BRWT bit were cleared, WE would be asserted coincidentally with

CS, and so would BLE, overriding the BCBL = 1 setting.

BLE

ClkOut

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BLE

324 Appendix B: Bus Timin

Examples

SRAM (or other generic memory) Timing Examples

Figure B-16 SRAM 8-Bit Bus Word Write Cycle with No CS to WE Delay

The effect, on the Typical SRAM 8-bit bus word write cycle, of removing the CS to WE

delay, is demonstrated by Figure B-16. For this example, the following setting was

changed:

BRWT = 0...no CS to WE delay.

Notice that the assertion of WE is coincidental with CS (BRWT = 0), but that BLE goes

active 1 cycle later (BCBL = 1). Since Access Time = 3, three cycles after BLE goes

active, the first Byte is latched in to memory by the rising edge of BLE. WE is also

negated on this cycle. One cycle later, the address and data begin to change. Since BRWT

= 0, there is no delay on WE, and it is asserted on this same cycle.

Note: WE would be active du ring the data change, so this is probably a dangerous tim ing

configuration. However, it could be appropriate for interfacing to 68000 style devices, or

any device that disables its Write while BLE is inactive.

One cycle after the address changes, BLE is asserted again. Three cycles later, the second

Byte is latched into memory by the rising edge of BLE. CS and WE are also negated on

this clock cycle, and the write is terminated. Two clock cycles after the rising edge of CS

(because Recovery Time = 2), CS may be asserted again to begin the next bus cycle.

BLE

ClkOut

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BLE

Appendix : DRAM Timin

Examples 325

DRAM Tim ing Examp les

B.2 DRAM Timing Examples

The timing examples in this appendix in tentionally omit A C tim ing parameters such as

setup time, hold time, etc. These examples are intended to demonstrate the effects of

changing MIF Bank Timing Register settings only. For AC timing d e tails, please refer to

the relevant XA-SCC data-sheets.

This section describes the accompanying DRAM timing diagrams, and will demonstrate

how the bits in the BiTMG Register effect a DRAM Interface Bank’s read and write

timing. Each “family” of bus cycles begins with the timing diagram for a “typical” case.

The typical case is then reprinted above each successive timing diagram for that family,

to demonstrate the effects of changing various bit values in the BiTMG Register.

For write cycles, the OE signal stays inactive (high), and is not shown. For read cycles,

the WE signal stays in active (high), and is n ot shown. RAS is asserted on the CSi_RASi

pins, CASL on the BLE_CASL pi n, and CASH on the BHE _CASH pin. Since the timing

is applicable to any bank (except Bank 0) configured as a DRAM Interface, the subscript

“i” will be omitted in this discussion. For a DRAM Interface, the bits in the BTMG

Figure B-17 Typical DRAM 16-Bit Bus Word Write Cycle

76543210

BRWT BCBL BAC BEC BWEX

Fast Page

Mode or

EDO

RAS to

CAS Delay Access Time Recovery Time Reserved,

write 0.

ClkOut

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CS (RAS)

BLE/BHE (CAS)

Valid Data

Row Column

326 Appendix B: Bus Timin

Examples

DRAM Timing Examples

This timing diagram depicts a typical DRAM 16-bit bus word write cycle, using the

following BTMG R egister setting s:

BRWT = 0 or 1...Same write cycle for FPM or EDO DRAM.

BCBL = 0...2 clock cycle RAS to CAS delay.

BAC = 001...Access Time = 1 + 1 = 2 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = 0...Reserved for DRAM Interface Banks.

• On a rising edge of CLKOUT, the row address is mu ltiplexed onto the Address Bus

(on pins A17-A6).

• One clock cycle later, CS (RAS) and WE go active, and the data are driven onto the

Data Bus.

• One clock cycle after CS (RAS) (because BCBL = 0), the column address is

multiplexe d onto the Address Bus.

• Two clock cycles after CS (RAS) (because RAS to CAS delay = 2), BLE/BHE (CAS)

go active.

• Two clock cycles after BLE/BHE (CAS) (because Access Time = 2), the data are

latched into memory by the rising edge of BLE/BHE (CAS), and CS (RAS) is negated

simultaneously. Write data wi ll remain valid for an other clock cycle.

• One clock cycle after CS (RAS) goes high, the Address Bus changes, and the write

cycle is terminated by the rising edge of WE.

•No CS

(RAS) will be asserted, by any bank, for two clock cycles after the rising edge

of CS (RAS) (because Recovery Time = 2).

Appendix : DRAM Timin

Examples 327

DRAM Tim ing Examp les

Figure B-18 DRAM Word Write Cycle on 16-Bit Bus, with longer RAS to CAS

delay, and Longer Recovery T ime

The effects, on the typical DRAM 16-bit bus word write cycle, of increasing the RAS to

CAS delay and the Recovery Time are demonstrated by Figure B-18. For this example,

only the follo wing settings were change d:

BCBL = 1 ... RAS to CAS delay = 3 clock cycles.

BEC = 10...Recovery Time = 3 clock cycles.

Notice that the output of the column address has been delayed by 1 clock cycle, and BLE/

BHE (CAS) are asserted 3 clock cycles after CS (RAS). As a result, the latching of the

data to memory and the termination of the write cycle are delayed by 1 clock cycle. No

CS (RAS) will be asserted, by any bank, for 3 clock cycles after the rising edge of CS

(RAS).

ClkOut

1234567891011

CS (RAS)

BLE/BHE (CAS)

Valid Data

Row Column

CS (RAS)

BLE/BHE (CAS)

Row Column

328 Appendix B: Bus Timin

Examples

DRAM Timing Examples

Figure B-19 Typical DRAM 8-Bit Bus Word Write Cycle

This figure depicts a Typical DRAM word write cycle on an 8-bit bus, using the

following BTMG R egister setting s:

BRWT = 0 or 1...Same write cycle for FPM or EDO DRAM.

BCBL = 0 ... RAS to CAS delay = 2 clock cycles.

BAC = 001...Access Time = 1 + 1 = 2 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = 0...Reserved for DRAM Interface Banks.

• On a rising edge of CLKOUT, the row address is mu ltiplexed onto the Address Bus

(on pins A17-A6).

• One clock cycle later, CS (RAS) and WE go active on the rising edge of CLKOUT,

and the data for the even addressed byte are driven onto the Data Bus.

• One clock cycle after CS (RAS) (because BCBL = 0), the even column address is

multiplexe d onto the Address Bus.

• Two clock cycles after CS (RAS) (because RAS to CAS delay = 2), BLE (CAS) goes

active.

• Two clock cycles after BLE (CAS) (because Access Time = 2), the even byte data are

latched into memory by the rising edge of BLE (CAS). The odd column address is

multiplexed onto the Address Bus, and the odd byte data are driven onto the Data Bus.

• One clock later, BLE (CAS) is asserted again.

• Two clock cycles after BLE (CAS) (because Access Time = 2), the odd byte data are

latched into memory by the rising edge of BLE (CAS), and CS (RAS) is negated

simultaneously. Write data wi ll remain valid for an other clock cycle.

• One clock cycle after CS (RAS) goes high, the Address Bus changes, and the write

cycle is terminated by the rising edge of WE.

•No CS

(RAS) will be asserted, by any bank, for two clock cycles after the rising edge

of CS (RAS) (because Recovery Time = 2).

ClkOut

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CS (RAS)

BLE (CAS)

Row Column Even Column Odd

Data Even Data Odd

Appendix : DRAM Timin

Examples 329

DRAM Tim ing Examp les

Figure B-20 Typical DRAM 16-Bit Bus Data Read Cycle

This timing diagram depicts a typical DRAM 16-bit bus data read cycle, using the

following BTMG R egister setting s:

BRW T = 0 or 1...Same data read cycle for FPM or EDO DRAM.

BCBL = 0 ... RAS to CAS delay = 2 clock cycles.

BAC = 001...Access Time = 1 + 1 = 2 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = 0...Reserved for DRAM Interface Banks.

• On a rising edge of CLKOUT, the row address is mu ltiplexed onto the Address Bus

(on pins A17-A6).

• One clock cycle later, CS (RAS) and OE go acti v e.

• One clock cycle after CS (RAS) (because BCBL = 0), the column address is

multiplexe d onto the Address Bus.

• Two clock cycles after CS (RAS) (because RAS to CAS delay = 2), BLE/BHE (CAS)

go active.

• After the DRAM’s access time has elapsed, the DRAM drives the data onto the Data

Bus.

• One clock cycle before the negation of BLE/BHE (CAS), CS (RAS) is negated.

• Two clock cycles after BLE/BHE (CAS) are asserted (because Access Time = 2), the

Data Bus is sampled on the rising edge of BLE/BHE (CAS ). OE is also negated, and

the Address Bus changes.

•No CS

(RAS) will be asserted, by any bank, for two clock cycles after the rising edge

of CS (RAS) (because Recovery Time = 2).

ClkOut

123456789

CS (RAS)

BLE/BHE (CAS)

Row Column

Valid Data

330 Appendix B: Bus Timin

Examples

DRAM Timing Examples

Figure B-21 DRAM 16-Bit Bus Data Read Cycle, with Longer Recovery Time

The effect, on the typical DRAM 16-bit bus data read cycle, of increasing the Recovery

Time is demonstrated by Figure B-21. Only the following setting was changed for this

example:

BEC = 10...Recovery Time = 3 clock cycles.

The minimum time from CS (RAS) high to CS (RAS) low again, for any bank, has been

increased to 3 clock cycles.

ClkOut

123456789

CS (RAS)

BLE/BHE (CAS)

Row Column

Valid Data

CS (RAS)

BLE/BHE (CAS)

Row Column

Valid Data

Appendix : DRAM Timin

Examples 331

DRAM Tim ing Examp les

Figure B-22 Typical Fast Page Mode DRAM Burst Code Read (x2) on 16-Bit Bus

This timing diagram depicts a typical Fast Page Mode DRAM burst code read, of two

bytes duration, on a 16-bit bus. The following BTMG Register settings were used:

BRWT = 0...Select Fast Page Mode DRAM.

BCBL = 0 ... RAS to CAS delay = 2 clock cycles.

BAC = 001...Access Time = 1 + 1 = 2 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = 0...Reserved for DRAM Interface Banks.

• On a rising edge of CLKOUT, the row address is mu ltiplexed onto the Address Bus

(on pins A17-A6).

• One clock cycle later, CS (RAS) and OE go acti v e.

• One clock cycle after CS (RAS) (because BCBL = 0), the word 1 column address is

multiplexe d onto the Address Bus.

• Two clock cycles after CS (RAS) (because RAS to CAS delay = 2), BLE/BHE (CAS)

go active.

• After the DRAM’s access time has elapsed, the DRAM drives the word 1 data onto the

Data Bus.

• Two clock cycles after BLE/BHE (CAS) (because Access Time = 2), the word 1 data

are sampled from the Data Bus, and BLE/BHE (C AS) are ne gated. Th e next s equen t ial

column address (word 2) is multiplexe d onto the Address Bus, and the word 2 data are

driven onto the Data Bus.

• One clock cycle after BLE/BHE (CAS) go high, BLE/BHE (CAS) are asserted again.

• Two clock cycles after BLE/BHE (CAS) (because Access Time = 2), the word 2 data

are sampled from the Data Bus. BLE/BHE (CAS), CS (RAS), and OE are negated,

ending the burst code read cycle.

•No CS

(RAS) will be asserted, by any bank, for two clock cycles after the rising edge

of CS (RAS) (because Recovery Time = 2).

ClkOut

1234567891011121314

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

332 Appendix B: Bus Timin

Examples

DRAM Timing Examples

Figure B-23 Fast Page Mode DRAM Burst Code Read (x2) on 16-Bit Bus, with

Longer RAS to CAS Delay

The effect on the typical FPM DRAM burst code read, of increasing the RAS to CAS

delay, is demonstrated in Figure B-23. The only setting changed for this example was:

BCBL = 1 ... RAS to CAS delay = 3 cycles.

Notice that the byte 1 column address is put out 2 clock cycles after CS (RAS), and BLE/

BHE (CAS) is asserted 3 clock cycles after CS (RAS). As a result, all subsequent

transitions in the burst code read have been delayed by 1 clock cycle.

ClkOut

1234567891011121314

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

Appendix : DRAM Timin

Examples 333

DRAM Tim ing Examp les

Figure B-24 Fast Page Mode DRAM Burst Code Read (x2) on 16-Bit Bus, with

Longer Access Time

The effect on the typical FPM DRAM burst code read, of increasing the Access Time, is

demonstrated in Figure B-24. The only setting changed for this example was:

BAC = 010...Access Time = 3 clock cycles.

Notice that the duration of the BLE/BHE (CAS) low-to-high strobes (and consequently

the intervals from BLE/BHE (CAS) low to sampling of the Data Bus) have been

increased to 3 clock cycles.

ClkOut

12345678910111213

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

334 Appendix B: Bus Timin

Examples

DRAM Timing Examples

Figure B-25 Fast Page Mode DRAM Burst Code Read (x2) on 16-Bit Bus, with

Longer Recovery T im e

The effect on the typical FPM DRAM burst code read, of increasing the Recovery Time,

is demonstrated in Figure B-25. The only setting changed for this example was:

BEC = 10...Recovery Time = 3 clock cycles.

Notice that no C S (RAS) from any bank may be asserted for at least 3 clock cycles after

CS (RAS) goes high.

ClkOut

1234567891011121314

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

Appendix : DRAM Timin

Examples 335

DRAM Tim ing Examp les

Figure B-26 Typical EDO DRAM Burst Code Read (x2) on 16-Bit Bus

This timing diagram depicts a typical EDO DRAM burst code read, of two bytes

duration, on a 16-bit bus. The following BTMG Register settings were used:

BRWT = 1...Select EDO DRAM.

BCBL = 0 ... RAS to CAS delay = 2 clock cycles.

BAC = 001...Access Time = 1 + 1 = 2 clock cycles.

BEC = 00 or 01...Recovery Time = 2 clock cycles.

BWEX = 0...Reserved for DRAM Interface Banks.

• On a rising edge of CLKOUT, the row address is mu ltiplexed onto the Address Bus

(on pins A17-A6).

• One clock cycle later, CS (RAS) and OE go acti v e.

• One clock cycle after CS (RAS) (because BCBL = 0), the byte 1 column address is

multiplexe d onto the Address Bus.

• Two clock cycles after CS (RAS) (because RAS to CAS delay = 2), BLE/BHE (CAS)

go active.

• After the DRAM’s access time has elapsed, the DRAM drives the word 1 data onto the

Data Bus.

• One clock cycle after BLE/BHE (CAS) low, BLE/BHE (CAS) are negated, and the

next sequential column address (byte 2) is multiplexed onto th e Address Bus.

• One clock cycle after BLE/BHE (CAS) high, the word 1 data are sampled from the

Data Bus. Then, BLE/BHE (CAS) are asserted again and the word 2 data are driven

onto the Data Bus. Notice that the duration of the interval , from the assertion of BLE/

BHE (CAS) for word 1 to the sampling of the word 1 data, is 2 clock cycles (because

Access Ti me = 2).

• One clock cycle after BLE/BHE (CAS) low, BLE/BHE (CAS) are negated.

ClkOut

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CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

336 Appendix B: Bus Timin

Examples

DRAM Timing Examples

• One clock cycle after BLE/BHE (CAS) high, the word 2 data are sampled from the

Data Bus. Notice that the duration of the interval, from the assertion of BLE/BHE

(CAS) for byte 2 to the sampling of the byte 2 data, is 2 clock cycles (because Access

Time = 2). Then, CS (RAS) and OE are negated, ending the burst code read cycle.

•No CS

(RAS) will be asserted, by any bank, for two clock cycles after the rising edge

of CS (RAS) (because Recovery Time = 2).

Figure B-27 EDO DRAM Burst Code Read (x2) on 16-Bit Bus, with Longer RAS to

CAS Delay

The effect, on the typical EDO DRAM burst code read, of increasing the RAS to CAS

delay, is demonstrated by Figure B-27. The only setting changed for this example was:

BCBL = 1 ... RAS to CAS delay = 3 clock cycles.

Notice that the byte 1 column address is put out 2 clock cycles after CS (RAS), and BLE/

BHE (CAS) is asserted 3 clock cycles after CS (RAS). As a result, all subsequent

transitions in the burst code read have been delayed by 1 clock cycle.

ClkOut

1234567891011121314

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

Appendix : DRAM Timin

Examples 337

DRAM Tim ing Examp les

Figure B-28 EDO DRAM Burst Code Read (x2) on 16-Bit Bus, with Longer Access

Time

The effect, on the typical EDO DRAM burst code read, of increasing the Access Time, is

demonstrated by Figure B-28. The only setting changed for this example was:

BAC = 010...Access Time = 3 clock cycles.

Notice that the duration of the intervals, from BLE/BHE (CAS) low to samp ling of the

Data Bus, is now 3 clock cycles.

ClkOut

1234567891011121314

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1

3 Clocks

Data 2

3 Clocks

338 Appendix B: Bus Timin

Examples

DRAM Timing Examples

Figure B-29 EDO DRAM Burst Code Read (x2) on 16-Bit Bus, with Longer

Recovery Time

The effect, on the typical EDO DRAM burst code read, of increasing the Recovery Time,

is demonstrated by Figure B-29. The only setting changed for this example was:

BEC = 10...Recovery Time = 3 clock cycles.

Notice that no C S (RAS) from any bank will be asserted for at least 3 clock cycles after

CS (RAS) high.

ClkOut

1234567891011121314

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

CS (RAS)

BLE/BHE (CAS)

Row Column 1 Column 2

Data 1 Data 2

Appendix C: SFR and MMR Addresses 339

Appendix C

SFR and MMR Addresses C

Contents

C.1 Special Function Re

ister (SFR) Addresses............................ ..................... ................................ ...........340

C.2 Memory Mapped Re

ister (MMR) Addresses ..........................................................................................343

340 Appendix C: SFR and MMR Addresses

Special Function Register (SFR) Addresses

C.1 Special Function Register (SFR) Addresses

Table C-1 Special Function Register (SFR) Addresses

NAME DESCRIPTION SFR

Address

BIT FUNCTIONS AND ADDRESSE S

MSB LSB

RESET

VALUE

BCR Bus Configuration Reg 46Ah - CLKD XSFR WAITD BUSD BC2 BC1 BC0 07h

BTRH Bus Timing Reg High 469h FFh

BTRL Bus Timing Reg Low 468h EFh

MRBL MMR Base Address Low 496h MA15 MA14 MA13 MA12 - - - MRBE x0h

MRBH MMR Base Address High 497h MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 xx

MICFG 499h -------CLKOE01h

CS Code Segment 443h 00h

DS Data Segment 441h 00h

ES Extra Segment 442h 00h

33F 33E 33D 33C 33B 33A 339 338

IEH* Interrupt Enable High 427h EHSWR3 EHSWR2 EHSWR1 EHSWR0 ESCP EAuto ESC23 ESC01 00h

337 336 335 334 333 332 331 330

IEL* Interrupt Enable Low 426h EA ED MAH EDMAL EX2 ET1 EX1 ET0 EX0 00h

IPA0 Interrupt Priority A0 4A0h - PT0 - PX0 00h

IPA1 Interrupt Priority A1 4A1h - PT1 - PX1 00h

IPA2 Interrupt Priority A2 4A2h - PDMAL - PX2 00h

IPA3 Interrupt Priority A3 4A3h Reserved - PDMAH 00h

IPA4 Interrupt Priority A4 4A4h - PSC23 - PSC01 00h

IPA5 Interrupt Priority A5 4A5h - PSCP - PAutoB 00h

IPA6 Interrupt Priority A6 4A6h - PHSWR1 - PHSWR0 00h

IPA7 Interrupt Priority A7 4A7h - PHSWR3 - PHSWR2 00h

Reserved 4A8h Reserved Reserved 00h

387 386 385 384 383 382 381 380

P0* Port 0 430h FFh

38F 38E 38D 38C 38B 38A 389 388

P1* Port 1 431h FFh

397 396 395 394 393 392 391 390

P2* Port 2 432h FFh

39F 39E 39D 39C 39B 39A 399 398

P3* Port 3 433h FFh

3A7 3A6 3A5 3A4 3A3 3A2 3A1 3A0

Reserved* 434h FFh

3AF 3AE 3AD 3AC 3AB 3AA 3A9 3A8

Reserved* 435h FFh

3E7 3E6 3E5 3E4 3E3 3E2 3E1 3E0

Reserved* 43Ch 00h

Appendix : Special Function Re

ister (SFR) Addresses 341

Special Function Register (SFR) Addresses

P0CFGA Port 0 Configuration A 470h Note 5

P1CFGA Port 1 Configuration A 471h Note 5

P2CFGA Port 2 Configuration A 472h Note 5

P3CFGA Port 3 Configuration A 473h Note 5

Reserved 474h Note 5

Reserved 475h Note 5

Reserved 476h Note 5

P0CFGB Port 0 Configuration B 4F0h Note 5

P1CFGB Port 1 Configuration B 4F1h Note 5

P2CFGB Port 2 Configuration B 4F2h Note 5

P3CFGB Port 3 Configuration B 4F3h Note 5

Reserved 4F4h Note 5

Reserved 4F5h Note 5

Reserved 4F6h Note 5

227 226 225 224 223 222 221 220

PCON* Power Control Reg 404h ------PDIDL00h

20F 20E 20D 20C 20B 20A 209 208

PSWH* Program Status Word

High 401h SM TM RS1 R S0 IM3 IM2 IM1 IM0 Note 2

207 206 205 204 203 202 201 200

PSWL* Program Status Word Low 400h C AC - - - V N Z Note 2

217 216 215 214 213 212 211 210

PSW51* 80C51 compatible PSW 402h C AC F0 RS1 RS0 V F1 P Note 3

RSTSRC Reset Source Reg 463h ROEN ----R_WDR_CMDR_EXTNote 7

RTH0 Timer 0 Reload High 455h 00h

RTH1 Timer 1 Reload High 457h 00h

RTL0 Timer 0 Reload Low 454h 00h

RTL1 Timer 1 Reload Low 456h 00h

SCR System Configuration Reg 440h ----PT1PT0CMPZ00h

21F 21E 21D 21C 21B 21A 219 218

SSEL* Segment Selection Reg 403h ESWEN R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG 00h

Table C-1 Special Function Register (SFR) Addresses (continued)

NAME DESCRIPTION SFR

Address

BIT FUNCTIONS AND ADDRESSE S

MSB LSB

RESET

VALUE

342 Appendix C: SFR and MMR Addresses

Special Function Register (SFR) Addresses

NOTES:

*SFRs marked wi th an asterisk (*) are bit addressable.

1. Never mind.

2. SFR is loaded from the reset vector.

3. F1, F0, and P reset to 0. All other bits are loaded from the reset vector.

4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may

be used for other purposes in future XA derivatives. The reset value shown for these bits is 0.

5. Port confi

urations default to quasi-bidirectional when the XA be

ins execution after reset. Thus all PnCFGA

isters will contain FFh and PnCFGB re

ister will contain 00h.

6. The WDCON reset value is E6 for a Watchdo

reset, E4 for all other reset causes.

7. The RSTSRC re

ister reflects the cause of the last XA reset. One bit will be set to 1, the others will be 0.

RSTSRC[7] enables the ResetOut function; 1 = Enabled, 0 = Disabled.

8. The XA

uards writes to certain bits (typically interrupt fla

s) that may be written by a peripheral function. This

prevents loss of an interrupt or other status if a bit was written directly by a peripheral action between the read and

write of an instruction that performs a read-modify-write operation. XA-SCC SFR bits that are

uarded in this

manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in WDCON).

SWE Software Interrupt Enable 47Ah - SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1 00h

357 356 355 354 353 352 351 350

SWR* Soft w ar e I nt errupt

Request 42Ah - SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00h

35F 35E 35D 35C 35B 35A 359 358

Reserved* 42Bh 00h

287 286 285 284 283 282 281 280

TCON* Timer 0/1 Control 410h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h

TH0 Timer 0 High 451h 00h

TH1 Timer 1 High 453h 00h

TL0 Timer 0 Low 450h 00h

TL1 Timer 1 Low 452h 00h

TMOD Timer 0/1 Mode 45Ch GATE C/T M1 M0 GATE C/T M1 M0 00h

28F 28E 28D 28C 28B 28A 289 288

TSTAT* Timer 0/1 Extended Status 411h -----T1OE-T0OE00h

2FF 2FE 2FD 2FC 2FB 2FA 2F9 2F8

WDCON* Wat chdog Contro l 41Fh PRE2 PRE1 PRE0 - - WDRUN WDTOF - Note 6

WDL Watchdog Timer Reload 45Fh 00h

WFEED1 Watchdog Feed 1 45Dh xx

WFEED2 Watchdog Feed 2 45Eh xx

Table C-1 Special Function Register (SFR) Addresses (continued)

NAME DESCRIPTION SFR

Address

BIT FUNCTIONS AND ADDRESSE S

MSB LSB

RESET

VALUE

Appendix : Memory Mapped Re

ister (MMR) Addresses 343

Memory Mapped Register (MMR) Addresses

C.2 Memory Mapped Register (MM R) Addresses

Table C-2 Memory Mapped Register (MMR) Addresses

MMR Name

Read/Write

Read Only Size

Address

Offset Description

SCCO Registers

SCC0 Write Register 0 R/W 8 800h Command register

SCC0 Write Register 1 R/W 8 802h Tx/Rx Interrupt & data transfer mode

SCC0 Write Register 2 R/W 8 804h Extended Features Control

SCC0 Write Register 3 R/W 8 806h Receive Parameter and Control

SCC0 Write Register 4 R/W 8 808h Tx/Rx misc. parameters & mode

SCC0 Write Register 5 R/W 8 80Ah Tx. parameter and control

SCC0 Write Register 6 R/W 8 80Ch Sync character or SDLC address field or Match Character 0

SCC0 Write Register 7 R/W 8 80Eh Sync character or SDLC flag or Match Character 1

SCC0 Write Register 8 R/W 8 810h Transmit Data Buffer

SCC0 Write Register 9 R/W 8 812h Master Interrupt control

SCC0 Write Register 10 R/W 8 814h Misc. Tx/Rx control register

SCC0 Write Register 11 R/W 8 816h Clock Mode Control

SCC0 Write Register 12 R/W 8 818h Lower Byte of Baud rate time constant

SCC0 Write Register 13 R/W 8 81Ah Upper Byte of Baud rate time constant

SCC0 Write Register 14 R/W 8 81Ch Misc. Control bits

SCC0 Write Register 15 R/W 8 81Eh External / Status interrupt control

SCC0 Write Register 16 R/W 8 828h Match Character 2 ( WR16 )

SCC0 Write Register 17 R/W 8 82Ah Match Character 3 ( WR17 )

SCC0 Read Register 0 RO 8 820h Tx/Rx buffer and external status

SCC0 Read Register 1 RO 8 822h Receive condition status/residue code

Reserved 824h

SCC0 Read Register 3 RO 8 826h Interrupt Pending Bits

see WR16 and 17 828-82Ah see WR16 and WR17 above

SCC0 Read Register 6 RO 8 82Ch SDLC byte count low register

SCC0 Read Register 7 RO 8 82Eh SDLC byte count high & FIFO status

SCC0 Read Register 8 RO 8 830h Receive Buffer

Reserved 832h

SCC0 Read Register 10 RO 8 834h Loop/clock status

Reserved 836-83Eh

SCC1 Registers

SCC1 Write Register 0 R/W 8 840h Command register

SCC1 Write Register 1 R/W 8 842h Tx/Rx Interrupt & data transfer mode

SCC1 Write Register 2 R/W 8 844h Extended Features Control

SCC1 Write Register 3 R/W 8 846h Receive Parameter and Control

SCC1 Write Register 4 R/W 8 848h Tx/Rx misc. parameters & mode

SCC1 Write Register 5 R/W 8 84Ah Tx. parameter and control

344 Appendix C: SFR and MMR Addresses

Memory Mapped Register (MMR) Addresses

SCC1 Write Register 6 R/W 8 84Ch Sync character or SDLC address field or Match Character 0

SCC1 Write Register 7 R/W 8 84Eh Sync character or SDLC flag or Match Character 1

SCC1 Write Register 8 R/W 8 850h Transmit Data Buffer

SCC1 Write Register 9 R/W 8 852h Master Interrupt control

SCC1 Write Register 10 R/W 8 854h Misc. Tx/Rx control register

SCC1 Write Register 11 R/W 8 856h Clock Mode Control

SCC1 Write Register 12 R/W 8 858h Lower Byte of Baud rate time constant

SCC1 Write Register 13 R/W 8 85Ah Upper Byte of Baud rate time constant

SCC1 Write Register 14 R/W 8 85Ch Misc. Control bits

SCC1 Write Register 15 R/W 8 85Eh External / Status interrupt control

SCC1 Write Register 16 R/W 8 868h Match Character 2 ( WR16 )

SCC1 Write Register 17 R/W 8 86Ah Match Character 3 ( WR17 )

SCC1 Read Register 0 RO 8 860h Tx/Rx buffer and external status

SCC1 Read Register 1 RO 8 862h Receive condition status/residue code

Reserved 864h

SCC1 Read Register 3 RO 8 866h Interrupt Pending Bits

see WR16 and 17 868-86Ah see WR16 and WR17 above

SCC1 Read Register 6 RO 8 86Ch SDLC byte count low register

SCC1 Read Register 7 RO 8 86Eh SDLC byte count high & FIFO status

SCC1 Read Register 8 RO 8 870h Receive Buffer

Reserved 872h

SCC1 Read Register 10 RO 8 874h Loop/clock status

Reserved 876-87Eh

SCC2 Registers

SCC2 Write Register 0 R/W 8 880h Command register

SCC2 Write Register 1 R/W 8 882h Tx/Rx Interrupt & data transfer mode

SCC2 Write Register 2 R/W 8 884h Extended Features Control

SCC2 Write Register 3 R/W 8 886h Receive Parameter and Control

SCC2 Write Register 4 R/W 8 888h Tx/Rx misc. parameters & mode

SCC2 Write Register 5 R/W 8 88Ah Tx. parameter and control

SCC2 Write Register 6 R/W 8 88Ch Sync character or SDLC address field or Match Character 0

SCC2 Write Register 7 R/W 8 88Eh Sync character or SDLC flag or Match Character 1

SCC2 Write Register 8 R/W 8 890h Transmit Data Buffer

SCC2 Write Register 9 R/W 8 892h Master Interrupt control

SCC2 Write Register 10 R/W 8 894h Misc. Tx/Rx control register

SCC2 Write Register 11 R/W 8 896h Clock Mode Control

SCC2 Write Register 12 R/W 8 898h Lower Byte of Baud rate time constant

SCC2 Write Register 13 R/W 8 89Ah Upper Byte of Baud rate time constant

SCC2 Write Register 14 R/W 8 89Ch Misc. Control bits

Table C-2 Memory Mapped Register (MMR) Addresses (continued)

MMR Name

Read/Write

Read Only Size

Address

Offset Description

Appendix : Memory Mapped Re

ister (MMR) Addresses 345

Memory Mapped Register (MMR) Addresses

SCC2 Write Register 15 R/W 8 89Eh External / Status interrupt control

SCC2 Write Register 16 R/W 8 8A8h Match Character 2 ( wr16 )

SCC2 Write Register 17 R/W 8 8AAh Match Character 3 ( wr17 )

SCC2 Read Register 0 RO 8 8A0h Tx/Rx buffer and external status

SCC2 Read Register 1 RO 8 8A2h Receive condition status/residue code

Reserved 8A4h

SCC2 Read Register 3 RO 8 8A6h Interrupt Pending Bits

see WR16 and 17 8A8-8AAh see WR16 and WR17 above

SCC2 Read Register 6 RO 8 8ACh SDLC byte count low register

SCC2 Read Register 7 RO 8 8AEh SDLC byte count high & FIFO status

SCC2 Read Register 8 RO 8 8B0h Receive Buffer

Reserved 8B2h

SCC2 Read Register 10 RO 8 8B4h Loop/clock status

Reserved 8B6-8BEh

SCC3 Registers

SCC3 Write Register 0 R/W 8 8C0h Command register

SCC3 Write Register 1 R/W 8 8C2h Tx/Rx Interrupt & data transfer mode

SCC3 Write Register 2 R/W 8 8C4h Extended Features Control

SCC3 Write Register 3 R/W 8 8C6h Receive Parameter and Control

SCC3 Write Register 4 R/W 8 8C8h Tx/Rx misc. parameters & mode

SCC3 Write Register 5 R/W 8 8CAh Tx. parameter and control

SCC3 Write Register 6 R/W 8 8CCh Sync character or SDLC address field or Match Character 0

SCC3 Write Register 7 R/W 8 8CEh Sync character or SDLC flag or Match Character 1

SCC3 Write Register 8 R/W 8 8D0h Transmit Data Buffer

SCC3 Write Register 9 R/W 8 8D2h Master Interrupt control

SCC3 Write Register 10 R/W 8 8D4h Misc. Tx/Rx control register

SCC3 Write Register 11 R/W 8 8D6h Clock Mode Control

SCC3 Write Register 12 R/W 8 8D8h Lower Byte of Baud rate time constant

SCC3 Write Register 13 R/W 8 8DAh Upper Byte of Baud rate time constant

SCC3 Write Register 14 R/W 8 8DCh Misc. Control bits

SCC3 Write Register 15 R/W 8 8DEh External / Status interrupt control

SCC3 Write Register 16 R/W 8 8E8h Match Character 2 ( wr16 )

SCC3 Write Register 17 R/W 8 8EAh Match Character 3 ( wr17 )

SCC3 Read Register 0 RO 8 8E0h Tx/Rx buffer and external status

SCC3 Read Register 1 RO 8 8E2h Receive condition status/residue code

Reserved 8E4h

SCC3 Read Register 3 RO 8 8E6h InterruptPending Register

SCC3 Read Register 6 RO 8 8ECh SDLC byte count low register

SCC3 Read Register 7 RO 8 8EEh SDLC byte count high & FIFO status

Table C-2 Memory Mapped Register (MMR) Addresses (continued)

MMR Name

Read/Write

Read Only Size

Address

Offset Description

346 Appendix C: SFR and MMR Addresses

Memory Mapped Register (MMR) Addresses

SCC3 Read Register 8 RO 8 8F0h Receive Buffer

Reserved 8F2h

SCC3 Read Register 10 RO 8 8F4h Loop/clock status

Reserved 8F6-8FEh

Rx DMA Registers

DMA Control Register Ch.0 Rx R /W 8 100h Control Register

FIFO Control & Status Reg Ch.0 Rx R/W 8 101h Control & Status Register

Segment Register Ch.0 Rx R/W 8 102h Points to 64K data segment

Buffer Base Register Ch.0 Rx R/W 8 104h Wrap Reload Value for A15 -A8, A7 - A0 reloaded to zero by

hardware

Buffer Bound Register Ch.0 Rx R/W 16 106h Upper Bound (plus 1) on A15 - A0

Address Pointer Reg Ch.0 Rx R/W 16 108h Current Address pointer A15 - A0

Byte Count Register Ch.0 Rx R/W 16 10Ah Corresponds to A15 - A0 Byte Count, generates interrupt if enabled

and byte count exceeded.

Data FIFO Register Ch.0 Lo Rx R/W 8

810Ch

10Dh 10Ch = Byte 0 = older,

10Dh = Byte 1 = younger

Data FIFO Register Ch.0 Hi Rx R/W 8

810Eh

10Fh 10Eh = Byte 2 = older,

10Fh = Byte 3 = younger

DMA Control Register Ch.1 Rx R /W 8 110h Control Register

FIFO Control & Status Register Ch.1 Rx R/W 8 111h Control & Status Register

Segment Register Ch. 1 Rx R/W 8 112h Points to 64K data segment

Buffer Base Register Ch. 1 Rx R/W 8 114h Wrap Reload Value for A15 -A8, A7 - A0 reloaded to zero by

hardware

Buffer Bound Register Ch.1 Rx R/W 16 116h Upper Bound (plus 1) on A15 - A0

Address Pointer Reg Ch.1 Rx R/W 16 118h Current Address pointer A15 - A0

Byte Count Register Ch.1 Rx R/W 16 11Ah Corresponds to A15 - A0 Byte Count, generates interrupt if enabled

and byte count exceeded.

Data FIFO Register Ch.1 Lo Rx R /W 16 11Ch 11Ch = Byte 0 = older,

11Dh = Byte 1 = younger

Data FIFO Register Ch.1 Hi Rx R/W 16 11Eh 11Eh = Byte 2 = older,

11Fh = Byte 3 = younger

DMA Control Register Ch.2 Rx R /W 8 120h Control Register

FIFO Control & Status Register Ch.2 Rx R/W 8 121h Control & Status Register

Segment Register Ch. 2 Rx R/W 8 122h Points to 64K data segment

Buffer Base Register Ch. 2 Rx R/W 8 124h Wrap Reload Value for A15 -A8, A7 - A0 reloaded to zero by

hardware

Buffer Bound Register Ch.2 Rx R/W 16 126h Upper Bound (plus 1) on A15 - A0

Address Pointer Reg Ch.2 Rx R/W 16 128h Current Address pointer A15 - A0

Byte Count Register Ch.2 Rx R/W 16 12Ah Corresponds to A15 - A0 Byte Count, generates interrupt if enabled

and byte count exceeded.

Data FIFO Register Ch.2 Lo Rx R /W 16 12Ch 12Ch = Byte 0 = older,

12Dh = Byte 1 = younger

Data FIFO Register Ch.2 Hi Rx R/W 16 12Eh 12Eh = Byte 2 = older,

12Fh = Byte 3 = younger

DMA Control Register Ch.3 Rx R /W 8 130h Control Register

Table C-2 Memory Mapped Register (MMR) Addresses (continued)

MMR Name

Read/Write

Read Only Size

Address

Offset Description

Appendix : Memory Mapped Re

ister (MMR) Addresses 347

Memory Mapped Register (MMR) Addresses

FIFO Control & Status Register Ch.3 Rx R/W 8 131h Control & Status Register

Segment Register Ch. 3 Rx R/W 8 132h Points to 64K data segment

Buffer Base Register Ch. 3 Rx R/W 8 134h Wrap Reload Value for A15 -A8, A7 - A0 reloaded to zero by

hardware

Buffer Bound Register Ch.3 Rx R/W 16 136h Upper Bound (plus 1) on A15 - A0

Address Pointer Reg Ch.3 Rx R/W 16 138h Current Address pointer A15 - A0

Byte Count Register Ch.3 Rx R/W 16 13Ah Corresponds to A15 - A0 Byte Count, generates interrupt if enabled

and byte count exceeded.

Data FIFO Register Ch.3 Lo Rx R /W 16 13Ch 13Ch = Byte 0 = older,

13Dh = Byte 1 = younger

Data FIFO Register Ch.3 Hi Rx R/W 16 13Eh 13Eh = Byte 2 = older,

13Fh = Byte 3 = younger

Tx DMA Registers

DMA Control Register Ch.0 Tx R/W 8 140h Control Register

FIFO Control & Status Register Ch.0 Tx R/W 8 141h Control & Status Register

Segment Register Ch. 0 Tx R/W 8 142h Points to 64K data segment

Buffer Base Register Ch. 0 Tx R/W 8 144h Wrap Reload Value for A15 -A8, A7 - A0 reloaded to zero by

hardware

Buffer Bound Register Ch.0 Tx R/W 16 146h Upper Bound (plus 1) on A15 - A0

Address Pointer Reg Ch.0 Tx R/W 16 148h Current Address pointer A15 - A0

Byte Count Register Ch.0 Tx R/W 16 14Ah Corresponds to A15 - A0 Byte Count, generates interrupt if enabled

and byte count exceeded.

Data FIFO Register Ch.0 Tx R /W 16 14Ch Byte0

Byte 1

Data FIFO Register Ch.0 Tx R /W 16 14Eh Byte2

Byte3

DMA Control Register Ch.1 Tx R/W 8 150h Control Register

FIFO Control & Status Register Ch.1 Tx R/W 8 151h Control & Status Register

Segment Register Ch.1 Tx R/W 8 152h Points to 64K data segment

Buffer Base Register Ch.1 Tx R/W 8 154h Wrap Reload Value for A15 -A8, A7 - A0 reloaded to zero by

hardware

Buffer Bound Register Ch.1 Tx R/W 16 156h Upper Bound (plus 1) on A15 - A0

Address Pointer Reg Ch.1 Tx R/W 16 158h Current Address pointer A15 - A0

Byte Count Register Ch.1 Tx R/W 16 15Ah Corresponds to A15 - A0 Byte Count, generates interrupt if enabled

and byte count exceeded.

Data FIFO Register Ch.1 Lo Tx R/W 16 15Ch Byte0 & 1

Data FIFO Register Ch.1 Hi Tx R/W 16 15Eh Byte2 & 3

DMA Control Register Ch.2 Tx R/W 8 160h Control Register

FIFO Control & Status Register Ch.2 Tx R/W 8 161h Control & Status Register

Segment Register Ch.2 Tx R/W 8 162h Points to 64K data segment

Buffer Base Register Ch.2 Tx R/W 8 164h Wrap Reload Value for A15 -A8, A7 - A0 reloaded to zero by

hardware

Buffer Bound Register Ch.2 Tx R/W 16 166h Upper Bound (plus 1) on A15 - A0

Address Pointer Reg Ch.2 Tx R/W 16 168h Current Address pointer A15 - A0

Table C-2 Memory Mapped Register (MMR) Addresses (continued)

MMR Name

Read/Write

Read Only Size

Address

Offset Description

348 Appendix C: SFR and MMR Addresses

Memory Mapped Register (MMR) Addresses

Byte Count Register Ch.2 Tx R/W 16 16Ah Corresponds to A15 - A0 Byte Count, generates interrupt if enabled

and byte count exceeded.

Data FIFO Register Ch.2 Lo Tx R/W 16 16Ch Byte0 & 1

Data FIFO Register Ch.2 Hi Tx R/W 16 16Eh Byte2 & 3

DMA Control Register Ch.3 Tx R/W 8 170h Control Register

FIFO Control & Status Register Ch.3 Tx R/W 8 171h Control & Status Register

Segment Register Ch. 3 Tx R/W 8 172h Points to 64K data segment

Buffer Base Register Ch. 3 Tx R/W 8 174h Wrap Reload Value for A15 -A8

A7 - A0 reloaded to zero by hardware

Buffer Bound Register Ch.3 Tx R/W 16 176h Upper Bound (plus 1) on A15 - A0

Address Pointer Reg Ch.3 Tx R/W 16 178h Current Address pointer A15 - A0

Byte Count Register Ch.3 Tx R/W 16 17Ah Corresponds to A15 - A0 Byte Count, generates interrupt if enabled

and byte count exceeded.

Data FIFO Register Ch.2 Lo Tx R/W 16 17Ch Byte0 & 1

Data FIFO Register Ch.2 Hi Tx R/W 16 17Eh Byte2 & 3

R/W 180-1FEh RESERVED for future DMA

Miscellaneous DMA Registers

Rx Character Time Out Register Ch.0 R/W 8 200h 0 value disables counter interrupt.

Rx Character Time Out Register Ch.1 R/W 8 202h Same as above, for Rx1

Rx Character Time Out Register Ch.2 R/W 8 204h Same as above, for Rx2

Rx Character Time Out Register Ch.3 R/W 8 206h Same as above, for Rx3

Global DMA Interrupt Register R/W 16 210h DMA Interrupt Flags

V.54/2047 Registers

VACS R/W 8 240h V.54 2047 Unit A Control & Status

VACFG R/W 8 241h V.54 2047 Unit A Configuration

VATCL R/W 8 242h V.54 2047 Unit A Threshold Cntr Lo

VATCH R/W 8 243h V.54 2047 Unit A Threshold Cntr Hi

VAEC R/W 8 244h V.54 2047 Unit A Error Counter

VBCS R/W 8 248h V.54 2047 Unit B Control & Status

VBCFG R/W 8 249h V.54 2047 Unit B Configuration

VBTCL R/W 8 24Ah V.54 2047 Unit B Threshold Cntr Lo

VBTCH R/W 8 24Bh V.54 2047 Unit B Threshold Cntr Hi

VBEC R/W 8 24Ch V.54 2047 Unit B Error Counter

SCP Interface Registers

SCPCFG R/W 8 260h SCP Configuration

SCPD R/W 8 262h SCP Data Byte

SCPCS R/W 8 263h SCP Control & Status

Autobaud Registers

Table C-2 Memory Mapped Register (MMR) Addresses (continued)

MMR Name

Read/Write

Read Only Size

Address

Offset Description

Appendix : Memory Mapped Re

ister (MMR) Addresses 349

Memory Mapped Register (MMR) Addresses

BDAEE R/W 8 270h Autobaud Echo Enable

BDCS R/W 8 272h Autobaud Control & Status

Memory Interface (MIF) Registers

B0CFG R/W 8 280h MIF Bank 0 Config

B0AM R/W 8 281h MIF Bank 0 Base Address

B0TMG R/W 8 282h MIF Bank 0 Timing Params

R/W

B1CFG R/W 8 284h MIF Bank 1 Config

B1AM R/W 8 285h MIF Bank 1 Base Address

B1TMG R/W 8 286h MIF Bank 1 Timing Params

R/W

B2CFG R/W 8 288h MIF Bank 2 Config

B2AM R/W 8 289h MIF Bank 2 Base Address

B2TMG R/W 8 28Ah MIF Bank 2 Timing Params

R/W

B3CFG R/W 8 28Ch MIF Bank 3 Config

B3AM R/W 8 28Dh MIF Bank 3 Base Address

B3TMG R/W 8 28Eh MIF Bank 3 Timing Params

R/W

B4CFG R/W 8 290h MIF Bank 4 Config

B4AM R/W 8 291h MIF Bank 4 Base Address

B4TMG R/W 8 292h MIF Bank 4 Timing Params

R/W

B5CFG R/W 8 294h MIF Bank 5 Config

B5AM R/W 8 295h MIF Bank 5 Base Address

B5TMG R/W 8 296h MIF Bank 5 Timing Params

R/W

MBCL R/W 8 2BEh MIF Memory Bank Configuration Lock Register

RFSH R/W 8 2BFh MIF Refresh Control

IDL Interface Registers

MSI Control Register R/W 16 2C0h IDL Mode Control Register

DataMask Register R/W 16 2C2h IDL Mask Register

Miscellaneous Registers

Hi-Pri Soft Ints & Pin Mu x Control Reg. R/W 16 2D0h Control bits for Hi-Priority Soft Ints, and Pin Mux

XInt2 R/W 8 2D2h External Interrupt 2 Control

Table C-2 Memory Mapped Register (MMR) Addresses (continued)

MMR Name

Read/Write

Read Only Size

Address

Offset Description

350 Appendix C: SFR and MMR Addresses

Memory Mapped Register (MMR) Addresses

Appendix D: V.54 & 2047 Generator Output 351

Appendix D

V.54 & 2047 Generator Out

ut D

Contents

D.1 V.54 Generator Scrambled Zeros Output (VxGP = 0).............................................................................. 352

D.2 V.54 Generator Scrambled Ones Output (VxGP = 1)............................................................................... 353

D.3 2047 Generator Output.............................................................................................................. ...............354

352 Appendix D: V.54 & 2047 Generator Output

V.54 Generator Scrambled Zeros Output (VxGP = 0)

D.1 V.54 Generator Scrambled Zeros Output (VxGP = 0)

Start: 11110100 10100011 01110001 11111100 00111011 11001011 00100100 00001000

10011000 10111010 11011000 00110011 01010011 10011110 11010000 10101011 11101001

01000110 11100011 11111000 01110111 10010110 01001000 00010001 00110001 01110101

10110000 01100110 10100111 00111101 10100001 01010111 11010010 10001101 11000111

11110000 11101111 00101100 10010000 00100010 01100010 11101011 01100000 11001101

01001110 01111011 01000010 10101111 10100101 00011011 10001111 11100001 11011110

01011001 00100000 01000100 11000101 11010110 11000001 10011010 10011100 11110110

10000101 01011111 01001010 00110111 00011111 11000011 10111100 10110010 01000000

10001001 10001011 10101101 10000011 00110101 00111001 11101101 00001010 10111110

10010100 01101110 00111111 10000111 01111001 01100100 10000001 00010011 00010111

01011011 00000110 01101010 01110011 11011010 00010101 01111101 00101000 11011100

01111111 00001110 11110010 11001001 00000010 00100110 00101110 10110110 00001100

11010100 11100111 10110100 00101010 11111010 01010001 10111000 11111110 00011101

11100101 10010010 00000100 01001100 01011101 01101100 00011001 10101001 11001111

01101000 01010101

Start: F4 A3 71 FC 3B CB 24 08 98 BA D8 33 53 9E D0 AB E9 46 E3 F8 77 96 48 11 31 75

B0 66 A7 3D A1 57 D2 8D C7 F0 EF 2C 90 22 62 EB 60 CD 4E 7B 42 AF A5 1B 8F E1 DE 59 20

44 C5 D6 C1 9A 9C F6 85 5F 4A 37 1F C3 BC B2 40 89 8B AD 83 35 39 ED 0A BE 94 6E 3F 87

79 64 81 13 17 5B 06 6A 73 DA 15 7D 28 DC 7F 0E F2 C9 02 26 2E B6 0C D4 E7 B4 2A FA 51

B8 FE 1D E5 92 04 4C 5D 6C 19 A9 CF 68 55

Appendix : V.54 Generator Scrambled Ones Output (VxGP = 1) 353

V.54 Generator Scrambled Ones Output (VxGP = 1)

D.2 V.54 Generator Scrambled Ones Output (VxGP = 1)

Start: 00000101 10101110 01000111 00000001 11100010 00011010 01101101 11111011

10110011 10100010 10010011 11100110 01010110 00110000 10010111 10101010 00001011

01011100 10001110 00000011 11000100 00110100 11011011 11110111 01100111 01000101

00100111 11001100 10101100 01100001 00101111 01010100 00010110 10111001 00011100

00000111 10001000 01101001 10110111 11101110 11001110 10001010 01001111 10011001

01011000 11000010 01011110 10101000 00101101 01110010 00111000 00001111 00010000

11010011 01101111 11011101 10011101 00010100 10011111 00110010 10110001 10000100

10111101 01010000 01011010 11100100 01110000 00011110 00100001 10100110 11011111

10111011 00111010 00101001 00111110 01100101 01100011 00001001 01111010 10100000

10110101 11001000 11100000 00111100 01000011 01001101 10111111 01110110 01110100

01010010 01111100 11001010 11000110 00010010 11110101 01000001 01101011 10010001

11000000 01111000 10000110 10011011 01111110 11101100 11101000 10100100 11111001

10010101 10001100 00100101 11101010 10000010 11010111 00100011 10000000 11110001

00001101 00110110 11111101 11011001 11010001 01001001 11110011 00101011 00011000

01001011 11010101

Start: 05 AE 47 01 E2 1A 6D FB B3 A2 93 E6 56 30 97 AA 0B 5C 8E 03 C4 34 DB F7 67 45

27 CC AC 61 2F 54 16 B9 1C 07 88 69 B7 EE CE 8A 4F 99 58 C2 5E A8 2D 72 38 0F 10 D3 6F

DD 9D 14 9F 32 B1 84 BD 50 5A E4 70 1E 21 A6 DF BB 3A 29 3E 65 63 09 7A A0 B5 C8 E0 3C

43 4D BF 76 74 52 7C CA C6 12 F5 41 6B 91 C0 78 86 9B 7E EC E8 A4 F9 95 8C 25 EA 82 D7

23 80 F1 0D 36 FD D9 D1 49 F3 2B 18 4B D5

354 Appendix D: V.54 & 2047 Generator Output

2047 Ge nera tor Ou tput

D.3 2047 Generator Output

Start: 10101010 10100000 00000100 00000010 10000001 00010000 10101010 01000000

01101000 00111001 00011011 10101110 10100010 10000101 00010010 00101011 01010000

11000010 01111001 01110011 10010111 10111001 00101011 10110000 10101110 01000010

11101001 00101001 10110001 11101110 11001010 10111100 00001001 10000101 11110010

01000111 01101011 01011000 11000111 01111011 01010010 11000011 00111001 11111011

11000010 10011001 00011111 10101100 00100011 10010101 10111000 01101011 00111000

11111011 01100010 11011101 00110101 00111100 00111001 10011011 11111110 10000000

10010000 01011010 00100110 01010111 11100001 00001100 10100111 11000111 00011011

01101110 11011010 10110110 00001101 11000111 01011011 01000110 11001011 10111100

10101001 11000001 11011000 11010111 01110001 01010110 10000001 10010000 11111010

01100010 01111101 01110001 00010110 10101001 10000001 11110000 11000110 01111011

11110010 10000111 00010011 01101011 11011000 10010111 01011001 01000111 10001011

00110100 11111100 11100001 11101100 11001011 11111100 10000001 11010000 11010010

01110011 01110111 11010101 00010000 00101010 00010000 01001010 00101100 01010011

10100011 10100101 10100110 01100111 11111111 00000000 01100000 00111100 00011001

10001111 11110110 00000101 11000010 01011001 01100111 10011111 00111100 01111001

10110011 11101111 10001010 00110100 01011100 10100101 11000110 01011011 11100110

10001111 10010110 00111001 11011011 11010110 10010001 10011010 11111110 00100000

11010100 01110000 10110110 01001101 11101111 01001010 01001100 01101111 10111010

00101010 01010000 01100010 00111101 01011001 00000111 10100011 00100101 11110110

01000101 11101010 01001000 01101101 00111011 00111010 11111010 00100010 01010101

01100000 00011100 00001101 10000111 01110011 01010111 11000001 00011000 10101111

01000010 01001001 01101101 10011011 01111110 11010000 10110010 01001111 01101110

01011010 11100110 00101111 11010010 00010011 01001011 11001100 10011111 11011100

00010101 10001000 01110101 00110100 00111100 10011001 11011111 11010100 00010000

10001010 01010100 01100000 10111100 01001001 10101101 11100011 01001101 11001111

01011110 01000100 11101010 11101000 00101001 00010001 10101010 11100000 00101100

00010011 10001011 10110100 10101100 11000011 11111001 10000011 11110001 10000110

11110011 10100111 10100111 00100111 01110111

Start: AA A0 04 02 81 10 AA 40 68 39 1B AE A2 85 12 2B 50 C2 79 73 97 B9 2B B0 AE 42

E9 29 B1 EE CA BC 09 85 F2 47 6B 58 C7 7B 52 C3 39 FB C2 99 1F AC 23 95 B8 6B 38 FB 62

DD 35 3C 39 9B FE 80 90 5A 26 57 E1 0C A7 C7 1B 6E DA B6 0D C7 5B 46 CB BC A9 C1 D8 D7

71 56 81 90 FA 62 7D 71 16 A9 81 F0 C6 7B F2 87 13 6B D8 97 59 47 8B 34 FC E1 EC CB FC

81 D0 D2 73 77 D5 10 2A 10 4A 2C 53 A3 A5 A6 67 FF 00 60 3C 19 8F F6 05 C2 59 67 9F 3C

79 B3 EF 8A 34 5C A5 C6 5B E6 8F 96 39 DB D6 91 9A FE 20 D4 70 B6 4D EF 4A 4C 6F BA 2A

50 62 3D 59 07 A3 25 F6 45 EA 48 6D 3B 3A FA 22 55 60 1C 0D 87 73 57 C1 18 AF 42 49 6D

9B 7E D0 B2 4F 6E 5A E6 2F D2 13 4B CC 9F DC 15 88 75 34 3C 99 DF D4 10 8A 54 60 BC 49

AD E3 4D CF 5E 44 EA E8 29 11 AA E0 2C 13 8B B4 AC C3 F9 83 F1 86 F3 A7 A7 27 77

355

Glossary

2047 One of two line testing protocols available

on the XA-SCC.z

A23 - A0 Address Bus, bits 23 - 0.

ABD3E - ABD0E Autobaud Enable for

SCC3 - SCC0.

ABD3F - ABD0F Autob aud Detect ion Flag s for

SCC3 - SCC0.

AdrFrz Address Freeze.

AEE3 - AEE0 Autobaud Echo Enable for SCC3

- SCC0.

Autobaud Automatic baud rate detection.

BCR Bus Configuration Register.

BDAEE Autobaud Echo Enable Register.

BDCS Autobaud Control and Status Register.

BiAC2 BiAC1 BiAC0 Bank i BLE/BHE Access

Time.

BiAM Bank i Base Address/DRAM Address

Multiplexer Co ntrol Reg.

BiBW Bank i Bus Width.

BiCBL Bank i CS to BLE/BHE delay.

BiCE Bank i Code Memory Enable

BiCF G Bank i Configuration Register (i = 0-5).

BiDE Bank i Data Memory Enable.

BiEC1 BiEC0 Bank i Recovery Time.

BiMS3 BiMS2 BiMS1 BiMS0 Bank i Mem ory

Size.

BiMX1 BiMX0 Row/Column Address

Multiplexer Control B its.

BiRWT Bank i Read/Write Timing .

BiTMG Bank i Timing Register.

BiTYP Bank i Type.

BiWEX Bank i BLE/BHE Conversion to

WEL/WEH.

BLE / BHE Byte Low Enable / Byte High

Enable.

BRG B a ud Rate Generator.

BRG3 - BRG0 BRG outputs from

SCC3 - SCC0.

BRGClk Clock input to Baud Rate Generator.

BRGDivdr 10-bi t down count er inte rnal to Bau d

Rate Generator.

BRGO ut Output signal from Baud Rate

Generator.

BTRH BT RL Bus Timing Register High and

Low bytes.

CAS Column Addr ess Strobe.

CASH CASL Column Addr ess S trobe High an d

Low.

CClk Internal XA-SCC system clock, same

frequency as XTALIN.

CD3 - CD0 Carrier Detect inputs to

SCC3 - SCC0.

CHPO (DMA) Channel High Priority Ov erride.

356

Glossary

CLKOE ClkOut Enable.

ClkOut Clock Output, same frequency as

XTALIN.

CODEC CODer-DECoder or

COmpression-DECompression.

ComClk Common Communications Clock.

CRC Cyclic Redundancy Check Cyclic

Redundancy Check ...

CS Chip Select.

CS5 - CS0 Chip Select 5 - 0.

CTS Clear To Send.

CTS3 - CTS0 Clear To Send inputs to

SCC3 - SCC0.

D15 - D0 Data Bus, bits 15 - 0.

DCD Data Carrier Detect ( uses the CD inputs to

SCC3 - SCC0).

DMA Di rect Memory Access.

DMAH DMAL DMA High and Low interrupts.

EAuto Enable bit for the Autobaud and V.54/

2047 interrupt.

EDMAL and EDMAH Enable bits for the

DMAL and DMAH interrupts.

EDO DRAM Extended Data-Out Dynamic

Random Access Memory.

EEPROM Electrically Erasable Programmable

Read Only Memory.

EHSWR3 - EHSWR0 Enabl e bits for High

Priority Software Interrupts 3 - 0.

EPROM Erasable Programmable Read Only

Memory.

EOF End Of Frame.

EOM End Of Message.

ESC01 and ESC23 Enable bits for the SCC0/1

and SCC2 /3 interrupts.

ESCP Enable bit for the SCP in terrupt.

ET0 and ET1 Enable bits for the Timer 0 and

Timer 1 interrupts.

EX0 EX1 EX2 Enable b its for External

Interrupts 0, 1, and 2.

FIFO First In First Out.

FM0 and FM1 Bit center transition data

encoding methods.

FPM DRAM Fast Page Mode Dy namic

Random Access Memory.

GPI/O General Purpose Input/Output.

HDLC High level Data Link Control.

HSWR3 - HSWR0 Flag bits for High Prio rity

Software Interrupts 3 - 0.

IDLOff IDL block, as a whole, is off. Defined

by MSI Control[2:0] = 111.

IDLOn IDL block, as a whole, is on. Defi ned

by MSI Control[2:0] ≠ 111.

IE Interrupt Enable.

IE0 I E1 IE2 Flag bits for Extern al Interrupts 0,

1, and 2.

INT0 INT1 INT2 External Interrupts 0, 1, and

IP Interrupt Pending.

IPA0 - IPA7 Interrupt Priority Registers 0 - 7.

ISDN Integrated Services Dig ital Network.

L1Clk IDL Clock.

L1GR IDL Grant.

357

Glossary

L1RQ IDL Request.

L1RxD IDL Receive Data.

L1SY1 IDL Sync.

L1Tx D IDL Transmit Data.

LastFrag Last Fragment of Packet bit.

MBCL Memory Bank Configuration Lock

MCIP Match Character Interrupt Pending.

MCIPEnable MCIP Interru pt Enable bit in Rx

SCC channel.

MICFG Memory Mapped Register

Configuration Register.

MIF Memory Interface.

MMR Memory Mapped Register.

MRBE Memory Mapped Register Enable bit.

MRBH MRBL Memory Mapped Register Base

Addr ess High a nd Low bytes.

MSI Multiplexed Serial Interface.

NMSI Non-Multiplexed Serial Interface.

NRZ and NRZI Non-Return to Zero and

Non-Return to Zero Inverted.

OE Output Enable.

P3.7 - P0.0 GPI/O Port 3 bit 7 - Port 0 bit 0.

Packet SDLC/HD LC data block consisting of

one or more Fragments.

PAutoB Priority bit field for the Autobaud and

V.54/2047 interrupt.

PClk An internal clock with freque ncy = system

clock / 2.

PCON Power Control Register.

PDMAL and PDMAH Priority bit fields for the

DMAL and DMAH interrupts.

PHSWR3 - PHSWR0 Priority bit fields for

Hig h Priority Soft ware I nterrupts 3 - 0.

PSC01 and PSC23 Priority bit fields for

SCC0/1 and SCC2/3 interrupts.

PSCP Priority bit field for the SCP interrupt.

PSEN Program Store Enable.

PT0 and PT1 Priority bit fields for Timer 0 and

Timer 1 interrupts.

PX0 PX1 PX2 Priority bit fields for External

Interrupts 0 - 2.

RAS Row Address Strobe.

RAS5 - RAS1 Row Address Strobes 5 - 1.

RClk An internal clock signal in each SCC.

RFEN Refresh Enable bit.

RFSH Refresh T iming Register.

RFTM6 - RFTM0 Bit field which holds the

Refresh Timer time constan t.

ROM Read Only Memory.

RSTSRC Reset Source Register.

RTClk Receive or Transmit Clock (or both).

RTClk3 - RTClk0 Receive or Transmit Clock

(or both) for SCC3 - SCC0.

RTS Request To Se nd.

RTS3 - RTS0 RTS outputs from SCC3 - SCC0.

Rx Receive.

RxClk Receive clock, an internal signal in each

SCC.

RxCTOR Receive Character Time Out Register.

358

Glossary

SC1isIDL Bit which connects SCC 1 to the IDL

Interface.

SC2isIDL Bit which connects SCC 2 to the IDL

Interface.

SCC Serial Communications Controller.

SCPCFG SCP Configuration Register.

SCPClk SCP Clock.

SCPRx SCP Receive Data.

SCPTx SCP Transmit Data.

SDC1 SDC2 Bits which assign SDS1 and SDS2

to the B1 or B2 channels.

SDLC Synchronous Data Link Control.

SDS1 SDS2 IDL Serial Data Strobes 1 and 2.

SFR Special Function Register.

Size8 Bus width selection feat ure avail abl e on

Pin 52 during reset.

SPB2 SPB1 SPB0 Bit field for selecting the

SCP Byte length.

SPC3 SPC2 SPC1 SPC0 Bit field for selecting

the frequency of SCPClk.

SPCI SCP Clock Invert bit.

SCPCS SCP Device Control and Status

SCPD SCP Data Byte Regis ter.

SPFG Flag bit for the SCP interrupt.

SPIDL SCP Idle State bit.

SPSTT SC P Start bit.

SRAM Static Random Access Memory.

SWP01 Swap Banks 0 and 1 bit.

Sync3 - Sync0 Sync input or Sync output (at the

pin) for SCC3 - SCC0.

SYNCOut Sync output signal (internal) from

each SCC.

TCC Two or More Control Characters bit.

TD1 a nd TD2 Internal signals in the IDL

Interface.

TF0 and TF1 Flag bits for Timer 0 and Timer 1

interrupts.

TRClk Transmit or Receive Clock (or both).

TRClk0 - TRClk3 Transmit or Receive Clock

(or both) for SCC0 - SCC3.

Tx Transmit.

Tx Er Transmit Error Status bit.

Tx IP Transmit Interrupt Pend i ng.

TxClk Transm itter Clock, internal clock signal

in each SCC.

UART Universal Asynchronous Receiver/

Transmitter.

Underrun When an SCC Transmitter runs out

of data.

V.54 One of two line testing p r otocols available

on the XA-SCC.

VADFG V.54/2047 Unit A Threshold Counter

interrupt flag.

VAVFG V.54/2047 Unit A Error Counter

interrupt flag.

VAGE VBGE V.54/2047 Units A and B

Generator Enable bits

VASCC Bit for assigning V.54/2047 Unit A to

SCC0 or SCC2.

359

Glossary

VBDFG V.54/2047 Unit B Threshold Counter

interrupt flag.

VBSCC Bit for assigning V.54/2047 Unit B to

SCC1 or SCC3.

VBVFG V.54/2047 Unit B Error Counter

interrupt flag.

VDD and VSS P os itive voltage and ground

pins.

VxCFG V.54/2047 Unit x (x = A or B)

Configuration Register.

VxDFG V.54/2047 Unit x Receiver Threshold

Detected Flag.

VxEC V.54/2047 Unit x Receiver Error

Counter.

VxGE V.54/204 7 Unit x Generator Enable bit.

VxGP V.54/2047 Unit x Generator Pattern

select bit.

VxRE V.54/2047 Unit x Receiver Enable bit.

VxRP V.54/2047 Unit x Receiver Pattern select

bit.

VxSCC V.54/2047 Unit x SCC Select bit.

VxSEL V.54/2047 Unit x V.54 or 2047 mode

select bit.

VxT11 - VxT7 V.54/2047 Unit x Receiver

Threshold bit field.

VxTCH V.54/2047 Unit x Receiver Threshold

Counter High byte.

VxTCL V.54/2047 Unit x Receiver Threshold

Counter Low byte.

VxVFG V.54/2047 Unit x Receiver Error

Counter Overflow Flag.

VxWT2 - VxWT0 V.54/2047 Unit x Receiver

Error Weight bit field.

WAIT External WA IT function available on Pin

52 after reset.

Watchdog U nderflow of this timer causes

internal reset.

WE Write Enable.

WEL WEH Write Enable Low and High.

WRAP Bit for enabling DMA circular buffers.

XInt2 External Interrupt 2 Control Register.

XTALIN XTALO UT Crystal o scillator

connection pins.

360
Index
Numerics
10-Bit Frame IDL Format 211
12-bit Sync character 107, 147
16-bit Sync character 107, 147
1Clock 112
2Byte mode 89
68000 type 38
6-bit Sync character 147
7/8Clock 112
8-Bit Frame IDL Format 211
8-bit Sync Character 147
A
A23 - A0 242
ABD3E through ABD0E 177
ABD3F through ABD0F 177, 229
Abort 75, 87, 101, 102
Abort Character 101
Abort due to Underrun 70
Access Time 57
Address Freeze 89
Address Multiplexer 33
Address Multiplexer Control Register 35
address multiplexin g 35
Address Pointer Register 62, 74, 75, 91
Address  Sear ch mo de 137
AdrFrz 89
AEE bit 174
AEE3 through AEE0 177
All Sent 161
Arbiter 41
Async Match Characters 156
Async/Sync mode 89
Asynchronous Character Match mode 92, 143
Asynchronous Framing Error (Special Receive
Condition) 
125
Asynchronous mode 89, 99
Auto Echo mode 152
Auto Enables 137
Auto EOM Reset 136
Auto RTS Deactivate 135
Auto Tx Flag 136
Autobaud and V.54/2047 Interrupts 229
Autobaud Control and Status Register 177
Autobaud Echo 169, 174
Autobaud Echo Enable Register 177
Autobaud Interrupts 174
B
B Channel Bit Masking 203
B Channel Enab le 204
B1, B2, and D channels, assigning to SCCs 203
B1Enable and B2Enable bits 204, 209
B5TMG Register 37
Back to Back Allowed 135
Bank 0 28
Bank i base address 30
Bank i Bus Width 52
Bank i Code Memory Enable 52
Bank i Data Memory Enable 52
Bank i Memory Size 54
Bank i Timing 55
Bank i Type 53
Baud Rate Error Windows 173
Baud Rate Generator 97, 111, 150, 152
Baud Rate Generator Time Constant 111
BCR (Bus Configuration Register) 20
BDAEE 177
BDCS 177
BHE, BLE 242
BiAC2 BiAC1 BiAC0 57
BiAM 55
BiBW 52
BiCBL 56
BiCE 52
BiCFG 30
BiDE 52
BiEC1 BiEC0 57
BiMS3 BiMS2 BiMS1 BiMS0 54
BiMX1 and BiMX0 35, 55

361
Index
BiRWT 56
Bisync mode 106, 140, 144
bit clock 79
bit clock rat e 113
bit-counter 192
bit-streaming 109
BiTYP 53
BiWEX 58
boot-up 28
Break condition 100
Break Sequence 157
Break/Abort 157
Break/Abort External/Status Interrupt 127
Break/Abort interrupt 100
Break/Abort Interrupt Enable 154
Break/Abort status bit 100
BRG 97, 111
BRG Enable 152
BRG output signal select 149
BRG Source Select 152
BRG3 - BRG0 242
BRGClk 112, 132, 152
BRGDivdr 111
BRGOut 111, 119
BRGTC 111, 150
BTRH (Bus Timing Register High Byte) 20
BTRH and BTRL (Bus Timing Register High and
Low Bytes) 50
BTRL (Bus Timing Register Low Byte) 20
Buffer Base Register 62, 64, 75, 90
Buffer Bound Register 62, 64, 75, 90
Buffer Empty 126, 159
Burst 27
Bus Signals, IDL 199
Bus Timing Register High and Low Bytes (BTRH
and BTRL) 50
Bus width 29
Byte Count 163
Byte Count Register 62, 91
Byte Counter  66, 74, 91
Byte High Enable, Byte Low Enable 242
Byte Order Status 92
C
Carrier Detect 242
CAS before RAS 37
CASH, CASL 242
CClk 115, 216
CD3 - CD0 242
Chaining, Tx 67
Channel Reset Codes 145
Character Time Out 79
Chip Select 27, 242
CHPO 41
circular buffer 63, 75, 89
Clear Channel 109
Clear To Send 242
CLKOE 51
ClkOut 242
clock frequencies, maximum 115
Clock mode 113, 119, 140
Clock Mode Control Register 148
Clock Output 242
Clocks, IDL Interface 200
Closing Flag 75, 87, 101, 102
Code Memory 16
Code Memory access (code space) 52
CODEC 205
Column Address Strobes 242
ComClk 97, 112, 242
Command Register 130
Common Communications Clock 242
Configuration Lock 58
Configuration Regi ster, V.54/2047 Unit x 191
Conversion to WEL/WEH 58
CRC 75, 102
CRC Error (Special Receive Condition) 125
CRC Polynomia l 142
CRC Preset 146
CRC Reset Code Bits 131
CRC/Framing Error 160
CS to BLE/BHE delay 56
CS5 - CS0 242
CTS 137, 152, 158
CTS External/Status Interrupt 127
CTS Interrupt Enable 155
CTS3 - CTS0 242
D
D channel grant 199
D15 - D0 242
Data Buffer, Rx 164
Data Buffer, Tx 144
data encod ing 146
Data FIFO Registers 62, 89, 91, 92
Data Memory access (data space) 52

362
Index
DataMask Register 203, 205, 210
DCD 137, 155, 159
DCD External/Status Interrupt 127
DCD Interrupt Enable 155
dead air 88
Direct Addressing 15
divide by 113
divisor 113
DMA Control Register 62, 75
DMA Interrupts 235
DMAH and DMAL 84
down-counter 88, 91, 93
DRAM Interface 34
DTACK 38
E
EAuto bit 174, 188, 229
Edge Triggered mode 238
EDMAL and EDMAH 84, 235
EDO DRAM 35
EEPROM 34
EHSWR3 - EHSWR0 228
empty byte in Data FIFO 92
emulators 51
Enable, B Channel 204
Enable, Receiver 138
Encoding 146
End of Frame 160
Enter Hunt Mode command 104, 137
EPROM 34
error bit ( V.54/2047 receive) 185
Error Counter, Receiver 187
Error Weight, Receiver 185
Error Windows, Baud Rate 173
Error, CRC 77
Error, Framing 99
Error, Parity 100
Error, Rx Overrun (Pac ket Status Byte) 76
ESC01 and ESC23 124, 230
ESCP 219, 229
ET0 and ET1 238
Event Interrupts 224, 226
EX0 and EX1 238
EX2 237
Excepti on Inte rrupt s 224
External Data Memory 15
External Interrupt 2 (INT2) 237
External Interrupts 0 and 1 238
external Sync input 132
External Sync mode 108, 140
External/Status Interrupt Control Register 154
External/Status Interrupts 126
External/Status IP 162
F
Fast Page Mode DRAM 35
FIFO 91, 92
FIFO BS 92
FIFO Byte Status 92
FIFO Control & Status Register 62, 83, 91
First Character 134
Flag 101
Flag Idle 102
Flag, SDLC/HDLC 101
Flash Memory 34
FM0 and FM1 146
Force Sync 132
FPM DRAM 35
fragment 66
Framing Error 99, 157
Freeze, Address 89
G
Generator Enable, V.54/2047 190
Generator Pattern 190
Gener ic Memory 34
Global DMA Interrupt Register 62, 75, 87
good bit (V.54/2047 receive) 185
GPI/O (General Purpose I/O) Ports 247
grouped pair (SCC interrupts) 124
H
handshaking 137
hardware reset 29, 37
Hardwired 45
Harvard Architecture 27
High Priority Override 41
High Priority Software Interrupts 15, 228
HSWR3 - HSWR0 21, 228
Hunt mode 104, 108, 137
I
idle state for SDLC mode 147
Idle, Mark and Flag 102

363
Index
IDLOff formally defined 196
IDLOn formally defined 196
IE (Interrupt Enable) bits 125
IE0 and IE1 238
IE2 238
Indirect Addressing 15, 20
insertion, zero 101
INT0 and INT1 238
INT2 237
Internal Data Me mo ry 15
internal reset 18
Interrupt Controller 224
Interrupt Pending Register (SCC) 161
Interrupt Priority Registers 226
Interrupt Status Bits (SCC) 157
interrupt vectors 31
invalid da ta in DMA Data FIFO 92
IP (Interrupt Pending) bits 125
IPA0 through IPA7 226
IPA6 and IPA7 (new Registers, Inte rrupt Priority 6
and 7) 21
ISDN (typic al) config uration , pin group ings fo r 244
L
L1Clk, L1SY1, L1GR, L1RxD, L1TxD, L1RQ 199
L1Clk,  Maximum frequency for 201
Last Matched Code 80, 83, 165
LastFrag bit 67, 69
latch 126
Least Significant Bit first 151
left justified 151, 215
Lev el Sensitive mode 238
Linear Buffers 65
Load Inhibit, Sync Char 138
Local Loopback mode 152
Lock, Memory Bank Configuration 58
Loop mode 142
Loop Sending 165
M
Mark Idle 99, 102
Masking a B channel bit time slot 203
Master External/Status Interrupt Enable bit 126,
134
master IDL clock signal 199
Master Interrupt Enable bit 124, 145
match character 92
Match Character Interrupt 80, 84, 87
MBCL 58
MCIP Interrupt 80, 83, 87, 92, 235
MCIPEnable 80, 92, 133, 235
Memory Mapped Registers 17, 42
MICFG 21, 51
Microwire 214
MMR 17, 42
MMR Base Address High and Low Bytes 51
Monosync mode 104, 140, 144
Most Significant Bit first 151
MOVX instruction 15
MRBE 42, 51
MRBH and MRBL 17, 21, 42, 51
MSI Control Register 196, 208
Multifunction Pin Programming 249
Multifunction Pins 247
N
NMSI 2, 10, 244
Non-Multiplexed Serial Interface 2, 10
Normal Ending 70, 75, 101, 102
NRZ and NRZI 146
Null Character 100, 157
O
OE 242
On Loop 166
Open Drain 248
Opening Flag 102
Output Enable 242
ove rlapping address ranges 27
Overrun Error, Rx (Packet Status Byte) 76
P
P3.7 - P0.0 242
Packet Byte Count 75
Packet Status Byte 75, 76
Packet, SDLC/HDLC 66, 101
pad byte 66, 75
Parity 141
Parity Error 100, 161
Parity is Special Condition 134
Partial Byte 77, 78
Pause 83
PAutoB 229
PClk 97, 112, 115, 171

364
Index
PCON (Power Control Register) 21
PDMAL and PDMAH 84, 235
Periodic Interrupt mode 73, 79, 88, 90
PHSWR3 - PHSWR0 228
Pin Groupings 244
Pin Multiplexing Control Register 181, 183, 251
Pins, Multifunction 247
Polynomial, CRC 142
Ports, GPI/O 247
Power Pins 243
Prescale, 7/8 132
Programming, Multifunction Pin 249
PSC01 and PSC23 124, 230
PSCP 219, 229
PSEN 27
PT0 and PT1 238
pull-up 44
Push-Pull 248
PX0 and PX1 238
PX2 237
Q
Quasi-Bidirectional 248
queuing 91
R
RAS to CAS delay 56
RAS5 - RAS1 243
RClk 112, 118, 132
Read/Write Timing 56
Receive Char acter Time Out Timer 93
Receive Clock 148
Receive Data Buffer 74
receive data signal, IDL 199
Receive DMA 74
Receive or Transmit Clock 243
Receive Sync chara c ter 105
Receiver Enable, SCC 138
Receiver Enable, V.54/2047 190
Receiver Error Counter 186, 192
Receiver Error Weight 185, 186, 191
Receiver Pattern 190
Receiver Thr eshold  185, 186, 191
Receiver Thr eshold  Counter 187, 192
Receiver Threshold Detected Flag 191
Recovery Time 57
refresh 48
Refresh Enable 59
Refresh Timer 37
refresh timer 49
Refresh Timing 59
Request to Send 243
Reset External/Status Interrupts command 126,
131, 
230
RESET instruction 19
Reset Out function 18
Reset Tx Interrupt Pending 230
Reset Tx Underrun/EOM Latch 131
Reset, CRC 131
Reset, Watchdog 14
ResetIn 18, 19
Residue 77, 78
RFEN 59
RFSH 59
RFTM6 - RFTM0 59
right justif ied  151, 215
ROM 34
Row Address Strobes  243
Row/Column Address Multiplexer 35
RSTSRC (Reset Source) Regi ster 18, 21
RTClk 97, 112
RTClk3 - RTClk0 243
RTS 135
RTS Control bit 143
RTS3 - RTS0 243
Rx Bits/Char 136
Rx Char Time Out Interrupt 79, 84, 88, 93, 235
Rx Character Available 159
Rx Character Time Out Register (RxCTOR) 62,
235
Rx CRC Enable 137
Rx Data Buffer 97, 164
Rx Enable (DMA) 75
Rx Interrupt 75, 79, 84, 88
Rx Interrupt Control Bits 134
Rx IP 162
Rx Overrun 134, 161
Rx Overrun (Special Receive Condition) 125
Rx Overrun Error (Packet Status Byte) 76
Rx Parity Error (Special Receive Condition) 125
Rx SDLC/HDLC mode 75, 89, 90
Rx Shift Register 97
RxClk 118, 148
RxCTOR 62, 79, 88, 93

365
Index
S
SC1isIDL 197, 209
SC2isIDL 197, 209
SCC Bit Clock 79
SCP Configuration Register 219
SCP Data Byte 220
SCP Device Control and Status Register 220
SCP Flag bit 220
SCP Idle State bit 221
SCP Interrupt 229
SCP State Machine 215
SCPCFG 214, 219
SCPClk 214
SCPCS 214, 220, 229
SCPD 214, 220
SCPRx 214
SCPTx 214, 215
Scramble Zeros and Scramble Ones 185, 187
SDC1 and SDC2 bits 200, 209
SDLC Byte Count 163
SDLC EOF 160
SDLC Id le Mode 147
SDLC Underrun Mo de 147
SDLC/HDLC End Of Packet (Special Receive
Condition) 
125
SDLC/HDLC Flag character 101, 144
SDLC/HDLC mode 89, 101, 140
SDS1 and SDS2 199
segment 64
Segment Regi ster 62, 74, 75, 90
Send Break 142
Serial Data Strobe, IDL 199
Serial Ports 15
SFR bit addres s 225
Shift Register, SCP 215
Short Frame IDL Format 211
Size8 243
Software Interrupts 15, 225
SPB2 SPB1 SPB0 215, 220
SPC3 SPC2 SPC1 SPC0 219
SPCP 219
Special Condition Interrupt 99, 134
Special Receive Condition Register 160
Special Receive Conditions 125, 134
SPFG 215, 218, 220, 229
SPI 214
SPIDL 215, 221
SPSTT 215, 218, 220
SRAM 34
start bit 99, 168
State Machine, SCP 215
Station Address 143
Status Byte, Packet 75, 76
Steering DMA Interrupts 84
Stop 83, 90
stop bit 99
stop bits, number of 141
Stop on TC mo de 73, 90
streaming 73
stuffing, zero 101
Swap 50, 58
Swapping, Bank 0 / Bank 1 31
SWP01 50, 58
Sync 97, 158
Sync Char Load Inhibit 138
Sync character 104, 143, 144
Sync character length 147
Sync Enable/Stop Bits 140
Sync input, external 132
Sync mode 140
Sync signal, IDL 199
Sync/Hunt 158
Sync/Hunt bit 105, 108, 137
Sync/Hunt External/Status Interrupt 127
Sync/Hunt Interrupt Enable 155
Sync3 - Sync0 243
Synchronous Modes Enable 140
SYNCOut 119
System Clock 115
T
TCC 81, 92
TD1 183
TD2 181
Terminal Count 73
TF0 and TF1 238
Threshol d, Re ce iv er  185
Timer 0 and Timer 1 14, 238
Timer 0 during ResetOut 18
Timer 2 14
Timer/Counters 14
Timing bits, SCPCLK 219
Timing Configuration Registers 36
Transmit Cl ock 149
transmit data signal, IDL 199
Transmit DMA 65

366
Index
Transmit or Receive Clock 243
Transmit Sync character 105
transmit underrun error 102
Trans pa rent mo de 109, 132
Trap Interrupts 225
TRClk 97
TRClk3 - TRClk0 243
tri-state, Pin 96 output driver  199, 203, 204
Two or More Control Characters 81
Tx Bits/Char 142
Tx Buffer Empty 126, 159
Tx Chaining 67
Tx Chaining mode, selecting 90
Tx CRC Enable 143
Tx Data Buffer 66, 97, 144
Tx DMA 65
Tx Enable (SCC) 142
Tx Er Status bit 70
Tx Interrupt 67, 70, 73, 84, 87
Tx Interrupt Enable (SCC) 134
Tx IP 162
Tx Shift register 97
Tx Underrun 70, 143, 147
Tx Underrun/EOM 157
Tx Underrun/EOM bit 104
Tx Underrun/EOM External/Status Interrupt 127
Tx Underrun/EOM Interrupt Enable 154
TxClk 118, 119, 149
TxD Hi for SDLC/HDLC-NRZI 135
U
UARTs 15
underflow 18
underrun abo rt  87
Underrun, Tx 147
unlocked 58
Unscramble Zeros and Unscramble Ones 185
up-counter 192
V
V.54 or 2047 Select 189
V.54 Receive 186
V.54/2047 interrupts 188
V.54/2047 SCC Select 189
VADFG and VBDFG 229
VAGE 180
Valid Baud Rates 171
valid data in DMA Data FIFO 92
VASCC bit 180
VAVFG and VBVFG 229
VBGE 183
VBSCC 183
VDD, VSS 243
Von Neuman Architecture 27
VxCFG 191
VxDFG 187, 191
VxEC 192
VxGE 190
VxGP 190
VxRE 190
VxRP 190
VxSCC 189
VxSEL 189
VxT11 through VxT7 191
VxTCH 192
VxTCL 192
VxVFG 187, 190
VxWT2 through VxWT0 191
W
WAIT_Size8 29, 38, 44
Watchdog Timer 14
WE 243
Wrap 64, 65, 89
Write del ay 29
Write Enab le 243
X
X21 mode 142, 166
XInt2 238
XTALIN, XTALOUT 243
Z
Zero Count 159
Zero Count External/Status Interrupt 127
Zero Count Interrupt Enable 155
zero insert ion 101
zero stuffin g 101