T4312816A - Taiwan Memory Technology, Inc.

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Preliminary T4312816A

TM Technology Inc. reserves the right P. 1 Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

SDRAM

8M x 16 SDRAM

2M x 16bit x 4Banks Synchronous DRAM

FEATURES

• 3.3V power supply

• Four banks operation

• LVTTL compatible with multiplexed address

• All inputs are sampled at the positive going

edge of system clock

• Burst Read Single-bit Write operation

• DQM for masking

• Auto refresh and self refresh

• 64ms refresh period (4K cycle)

• MRS cycle with address key programs

- CAS Latency ( 2 & 3 )

- Burst Length ( 1 , 2 , 4 , 8 & full page)

- Burst Type (Sequential & Interleave)

• Available package type in 54 pin TSOP(II)

• Operating temperature : 0 ~ +70 °C

ORDERING INFORMATION

GRNERAL DESCRIPTION

The T4312816A is 134,217,728 bits

synchronous high data rate Dynamic RAM

organized as 4 x 2,097,152 words by 16 bits,

fabricated with high performance CMOS

technology .

Synchronous design allows precise cycle control

with the use of system clock I/O transactions are

possible on every clockcycle . Range of operating

frequencies , programmable burst length and

programmable latencies allow the same device to

be useful for a variety of high bandwidth , high

performance memory system applications.

PIN ARRANGEMENT (Top View)

DQ1

VDD

46

45

44

43

41

42

40

36

35

34

33

32

31

30

29

1

2

3

4

6

5

7

8

9

11

15

16

17

18

19

20

VDDQ

DQ11

DQ1

0

A8

A7

A9

10

21

22

47

48

49

50

VSSQ

DQ2

A0

A1

DQ15

DQ14

Vss

23

24

25

2827

26

DQ3

DQ0

VDDQ

DQ4

DQ5

VSSQ

DQ6

RAS

CS

BA1

A10/AP

A2

A3

VDD

VSSQ

DQ13

DQ12

DQ9

UDQM

N.C

CLK

CKE

Vss

A6

A5

A4

12

13

14

39

38

37

DQ7

VDD

LDQM

DQ8

Vss

N.C/RFU

W E

CAS

54PIN T SO P(II)

(400m il x 875m il)

(0.8 mm PIN PITCH)

51

52

53

54

VDDQ

BA0

VDDQ

VSSQ

A11

PART NO. MAX

FREQUENCY TEMPERATURE

T4312816A-6S 166 MHz 0 ~ +70°C

T4312816A-7S 143 MHz 0 ~ +70°C

T4312816A-7.5S 133 MHz 0 ~ +70°C

T4312816A-8S 125 MHz 0 ~ +70°C

T4312816A-10S 100 MHz 0 ~ +70°C

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Preliminary T4312816A

TM Technology Inc. reserves the right P. 2 Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

BLOCK DIAGRAM

D ata Input R egister

I/O Control Output Buffer

2M x 16

Sense AM P

C olum n D ecoder

La te n c y & Burs t L e n gt h

Program m ing Register

Bank Select

Row Buffeer

Refresh Counter

Row Decoder

A dd ress Register

Col. Buffer

Tim ing R egister

DQi

L(U)DQMRASCSCKECLK

LCBR

LRAS

ADD

CLK

CAS WE

2M x 16

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Preliminary T4312816A

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to change products or specifications without notice. Revision: 0.B

PIN DESCRIPTION

PIN NAME INPUT FUNCTION

CLK System Clock

Active on the positive going edge to sample all input.

CS Chip Select Disables or enables device operation by masking or enabling all input

except CLK,CKE and L(U)DQM

CKE Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A11 Address Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11,column address : CA0 ~ CA8

BA0 ~ BA1 Bank Select Address Selects bank to be activated during row address latch time.

Select bank for read/write during column address latch time.

RAS Row Address Strobe

Latches row addresses on the positive going edge of the CLK

with RAS low.

Enables row access & precharge.

CAS Column Address Strobe

Latches column addresses on the positive going edge of the CLK

with CAS low.

Enables column access .

WE Write Enable Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

L(U)DQM Data Input/Output

Mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQ0 ~ DQ15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.

VDD/VSS Power Supply/Ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data Output

Power/Ground

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

N.C/RFU

No

Connection/Reserved

for Future Use

This pin is recommended to be left No Connection on the device.

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Preliminary T4312816A

TM Technology Inc. reserves the right P. 4 Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on Any Pin Relative To Vss VIN,VOUT -1.0 to 4.6 V

Supply Voltage Relative To Vss VDD,VDDQ -1.0 to 4.6 V

Short circuit Output Current Iout 50 mA

Power Dissipation PD 1 W

Operating Temperature TOPR 0 to +70 °C

Storage Temperature Tstg -55 to +150 °C

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to +70°

°°

°C, Voltage referenced to VSS=0V)

Parameter Symbol Min. Typ Max. Unit Notes

Supply Voltage VDD,VDDQ 3.0 3.3 3.6 V

Input High Voltage VIH 2.0 3.0 VDD+0.3V V

Input Low Voltage VIL -0.3 0 0.8 V

Output logic high voltage VOH 2.4 - - V IOH=-4mA

Output logic low voltage VOL - - 0.4 V IOL=4mA

Input leakage current IIL -1 - 1 uA 1

Output leakage current IOL -1.5 - 1.5 uA 2

Note : 1. Any input 0V≤ VIN ≤ VDD+ 0.3V , all other pin are not under test = 0V.

2. Dout = disable, 0V≤ VOUT ≤ VDD .

CAPACITANCE

(TA =25°C,VDD=3.3V, f = 1MHz)

Pin Symbol Min Max Unit

CLOCK CCLK 2.5 4.0 pF

ADDRESS CADD 2.5 5.0 pF

DQ0 ~ DQ15 COUT 4.0 6.5 pF

RAS,CAS,WE,CS,CKE,LDQM,

UDQM

CIN 2.5 5.0 pF

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Preliminary T4312816A

TM Technology Inc. reserves the right P. 5 Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

DC CHARACTERISTICS

TA = 0 to 70°C , VIH(min)/VIL(max)=2.0V/0.8V

Speed version

Parameter Symbol

-6 -7 -7.5 -8 -10

Unit Test Condition Note

Operating Current

( One Bank Active) ICC1 140 120 115 110 100 mA

Burst Length = 1

tRC≥tRC(min) ,tCC≥tCC(min),IOL= 0 mA

1,3

ICC2P 2 CKE ≤ VIL(max),tCC=15ns

Precharge Standby

Current in power-

down mode ICC2PS 2

mA

CKE ≤ VIL(max),CLK ≤VIL(max), tCC =∞

3

ICC2N 20 CKE ≥ VIH(min), CS ≥ VIH(min),tCC=15ns

Input signals are changed one time during 30ns

Precharge Standby

Current in non

power-down mode

ICC2NS 8

mA

CKE≥VIH(min),CLK ≤VIL(min),tCC=∞

Input signals are stable

3

ICC3P 5 CKE ≤ VIL(max),tCC=15ns

Active Standby

Current in power-

down mode ICC3PS 4

mA

CKE ≤ VIL(max),CLK ≤VIL(max),tCC=∞

3

ICC3N 30 CKE≥VIH(min), CS ≥VIH(min),tCC=15ns

Input signals are changed one time during 30ns

Active Standby

Current in non

power-down mode

(One Bank Active) ICC3NS 20

mA

CKE≥VIH(min),CLK ≤VIL(min),tCC=∞

Input signals are stable

3

150 130 125 120 110 CAS Latency 3

Operating Current

(Burst Mode) ICC4

150 130 125 120 110

mA

CAS Latency 2

IOL=0 mA,Page Burst

All Band Activated

tCCD= tCCD(min)

1,3

Refresh Current ICC5 150 130 125 120 110 mA

tRC ≥tRC(min) 2,3

Self refresh

Current ICC6 2 mA

CKE ≤0.2V

Note: 1. Measured with output open. Addresses are changed only one time during tCC(min) .

2. Refresh period is 64ms. Addresses are changed only one time during tCC(min) .

3. tCC : Clock cycle time.

tRC : Row cycle time.

tCCD : Column address to column address delay time.

TE

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Preliminary T4312816A

TM Technology Inc. reserves the right P. 6 Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

AC OPERATING CONDITIONS

(VDD=3.3V ±0.3V ,TA= 0 to 70°C)

Parameter Value Unit

Input levels (VIH/VIL) 2.4 / 0.4 V

Input timing measurement reference level 1.4 V

Input rise and fall time tr / tf = 1 / 1 ns

Output timing measurement reference level 1.4 V

Output load condition See Fig.2

3.3V

1200 ohm

Output

870 ohm

30pf

VOH(DC)=2.4,IOH=-4mA

VOL(DC)=0.4,IOL=4mA

ZO=50 ohmOutput

50 ohm

Vtt=1.4v

30pf

(Fig.1) DC Output Load Circuit (Fig.2)AC Output Load Circuit

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Preliminary T4312816A

TM Technology Inc. reserves the right P. 7 Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

OPERATING AC PARAMETER

(AC opterating conditions unless otherwise noted) Speed Version

Parameter Symbol

-6 -7 -7.5 -8 -10

Unit Note

Row active to row active delay tRRD(min) 12 14 15 16 20 ns 1

RAS to CAS delay tRCD(min) 15 15 18 20 20 ns 1

Row precharge time tRP(min) 15 15 20 20 20 ns 1

tRAS(min) 42 42 45 48 50 ns 1

Row active time tRAS(max) 120K ns

Row cycle time tRC(min) 60 63 65 68 70 ns 1

Last data in to new col. Address delay tCDL(min) 1 CLK 2

Last data in to row precharge tRDL(min) 2 CLK 2

Last data in to burst stop tBDL(min) 1 CLK 2

Col. Address to col. Address delay tCCD(min) 1 CLK 3

CAS latency=3 1

Number of valid output data CAS latency=2 1 ea 4

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required

with clock cycle time and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

The earliest a precharge command can be issued after a Read command without the loss of data is

CL + BL-2 clocks.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.8

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to change products or specifications without notice. Revision: 0.B

AC CHARACTERISTICS

(AC opterating conditions unless otherwise noted)

-6 -7 -7.5 -8 -10

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Note

CAS Latency = 3 6 1K 7 1K 7.5 1K 8 1K 10 1K

CLK cycle time CAS Latency = 2 tCC 8 9 9 10 10 ns 1

CAS Latency = 3 - 5.5 - 6 6 - 6 - 7 ns

CLK to valid

Output delay CAS Latency = 2 tSAC - 6 - 6 6 - 7 - 9 ns 1

Output data hold time tOH 2 2.5 2.5 2.5 2.5 ns 2

CLK high pulse width tCH 2 2.5 2.5 3 3 ns 3

CLK low pulse width tCL 2 2.5 2.5 3 3 ns 3

Input setup time tSS 1.5 1.75 1.75 2 2.5 ns 3

Input hold time tSH 1 1 1 1 1 ns 3

CLK to output in Low-Z tSLZ 1 1 1 1 1 ns 2

CAS Latency = 3 - 5.5 - 6 6 - 6 - 7 ns

CLK to output in

Hi-Z CAS Latency = 2 tSHZ - 6 - 6 6 - 7 - 9 ns

Note: 1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns,transient time compensation should be considered,

i.e.,[(tr+tf)/2-1]ns should be added to the parameter.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.9

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to change products or specifications without notice. Revision: 0.B

FREQUENCY vs. AC PARAMETER RELATIONAHIP TABLE

T4312816A-6S (Unit : number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

Frequency CAS

Latency 60ns 42ns 15ns 12ns 15ns 6ns 6ns 12ns

166MHz(6.0ns) 3 10 7 3 2 3 1 1 2

143MHz(7.0ns) 3 9 6 3 2 3 1 1 2

125MHz

(

8.0ns

)

2 9 6 2 2 2 1 1 2

111MHz(9.0ns) 2 7 5 2 2 2 1 1 2

100MHz

(

10.0ns

)

2 7 5 2 2 2 1 1 2

T4312816A-7S (Unit : number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

Frequency CAS

Latency 63ns 42ns 15ns 14ns 15ns 7ns 7ns 14ns

143MHz(7.0ns) 3 9 6 3 2 3 1 1 2

125MHz(8.0ns) 3 9 6 2 2 2 1 1 2

111MHz

(

9.0ns

)

2 8 5 2 2 2 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz

(

12.0ns

)

2 6 4 2 2 2 1 1 2

T4312816A-7.5S (Unit : number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

Frequency CAS

Latency 65ns 45ns 20ns 15ns 18ns 7.5ns 7.5ns 15ns

133MHz(7.5ns) 3 9 6 3 2 3 1 1 2

125MHz(8.0ns) 3 9 6 3 2 3 1 1 2

111MHz

(

9.0ns

)

2 8 5 3 2 2 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz

(

12.0ns

)

2 6 4 2 2 2 1 1 2

T4312816A-8S (Unit : number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

Frequency CAS

Latency 68ns 48ns 20ns 16ns 20ns 8ns 8ns 16ns

125MHz(8.0ns) 3 9 6 3 2 3 1 1 2

111MHz(9.0ns) 3 9 6 3 2 3 1 1 2

100MHz

(

10.0ns

)

2 7 5 2 2 2 1 1 2

83MHz(12.0ns) 2 6 4 2 2 2 1 1 2

75MHz

(

13.0ns

)

2 6 4 2 2 2 1 1 2

T4312816A-10S (Unit : number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

Frequency CAS

Latency 70ns 50ns 20ns 20ns 20ns 10ns 10ns 20ns

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz(12.0ns) 2 7 5 2 2 2 1 1 2

75MHz

(

13.0ns

)

2 6 4 2 2 2 1 1 2

66MHz(15.0ns) 2 6 4 2 2 2 1 1 2

60MHz

(

16.7ns

)

2 5 3 2 2 2 1 1 Note 1

Note : 1. tRDL ≥ 16.7ns is recommended for T4312816A

2. Clock count formula : clock ≥periodclock

valuebase (round off whole number).

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Preliminary T4312816A

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MODE REGISTER

11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1

JEDEC Standa rd Test Set (refresh counter test)

11 10 9 8 7 6 5 4 3 2 1 0

x x 1 0 0 LTMODE WT BL Burst Read and Single Write (for Write Through Cache)

11 10 9 8 7 6 5 4 3 2 1 0

1 0 Use in future

11 10 9 8 7 6 5 4 3 2 1 0

x x x 1 1 v v v v v v v

Vender Specific

11 10 9 8 7 6 5 4 3 2 1 0 v = Valid

0 0 0 0 0 LTMODE WT BL Mode Register Set x = Don’t care

Bit2-0 WT=0 WT=1

000 1 1

001 2 2

010 4 4

011 8 8

100 R R

101 R R

110 R R

Burst length

111 Full page R

0 Sequential

Wrap type 1 Interleave

Bit6-4 CAS Latency

000 R

001 R

010 2

011 3

100 R

101 R

110 R

Latency mode

111 R

Remark R : Reserved

Mode Register Write Timing

CLOCK

CKE

CS

RAS

CAS

WE

A0-A11

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Preliminary T4312816A

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Burst Length and Sequence

(Burst of Two)

Starting Address

(column address A0 binary) Sequential Addressing

Sequence (decimal) Interleave Addressing

Sequence (Decimal)

0 0,1 0,1

1 1,0 1,0

(Burst of Four)

Starting Address

(column address A1-A0 binary) Sequential Addressing

Sequence (decimal) Interleave Addressing

Sequence (Decimal)

00 0,1,2,3 0,1,2,3

01 1,2,3,0 1,0,3,2

10 2,3,0,1 2,3,0,1

11 3,0,1,2 3,2,1,0

(Burst of Eight)

Starting Address

(column address A2-A0 binary) Sequential Addressing

Sequence (decimal) Interleave Addressing

Sequence (Decimal)

000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7

001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6

010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5

011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4

100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3

101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2

110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1

111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 512 for

8Mx16 divice.

POWER UP SEQUENCE

1. Apply power and start clock, attempt to maintain CKE = ‘H’ , L(U)DQM = ‘H’ and the other pin are NOP

condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue mode register set command to initalize the mode register.

Cf.) Sequence of 4 & 5 is regardless of the order.

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Preliminary T4312816A

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SIMPLIFIED TRUTH TABLE

COMMAND CKEn-1 CKEn

CS RAS CAS WE DQM BA

0,1 A10/AP A9~A0,

A11 Note

Register Mode Register Set H X L L L L X X 1,2

Auto Refresh H

Entry H L L L L H X X 3

L H H H

Refresh Self

Refresh Exit L H

H X X X X X 3

Bank Active & Row Address H X L L H H X V Row Address

Auto Precharge Disab le L

Read Column

Address Auto Precharge Enable H X L H L H X V

H

Column

Address

(A0~A8) 4,5

Auto Precharge Disab le L

Write & Column

Address Auto Precharge Enable H X L H L L X V H

Column

Address

(A0~A8) 4,5

Burst Stop H X L H H L X X 6

Bank Selection V L

Precharge Both Banks H X L L H L X

X H 4

H X X X Entry H L

L V V V X

Clock Suspend or

Active Power Down Exit L H X X X X X X

H X X X Entry H L

L H H H X

H X X X

Precharge Power Down

Mode Exit L H

L V V V X X

DQM H X V

X 7

H H X X X

No Operation Command H X L H H H X X

(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)

Notes :

1. OP Code : Operation Code. A0~A11 , BA0~BA1 : Program keys.(@MRS)

2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row

precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.

4. BA0~BA1 : Bank select address.

If both BA0 and BA1 are ’Low’ : at read , write , row active and precharge , bank A is selected.

If both BA0 is ‘Low’ and BA1 is ‘High’ : at read , write , row active and precharge , bank B is selected.

If both BA0 is ‘High’ and BA1 is ‘Low’ : at read , write , row active and precharge , bank C is selected.

If both BA0 and BA1 are ’High’ : at read , write , row active and precharge , bank D is selected

If A10/AP is ‘High’ : at row precharge , BA0 and BA1 ignored and all banks are selected.

5. During burst read or write with auto precharge , new read/write command cannotbeissued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

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Preliminary T4312816A

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Single Bit READ - Write Cycle (Same Page) @CAS Latency=3,Burst Length=1

CLOCK

CK E

CS

RA S

CA S

ADDR

BA

A10/AP

DQ

WE

DQ M

012345678910111213141516171819

tCH

tCC

tCL

HIGH

tRAS

tRC

*Note1 tSH

tSS tRP

tRCD

tSH

tSS tCCD

*Note2 *Note2.

3*Note2.

3*Note4 *Note2

tSH

tSS

tSH tSS

tSH

*Note3 *Note3 *Note3 *Note4

tRAC

tSRC

tSLZ tOH tSS

tSH

tSS

tSH

tSS

Row A ctive Read W rite Read Precharge Row Active

Ra Ca Cb Cc Rb

Bs Bs Bs Bs Bs Bs

RbRa

Qa Db Qc

:Do n 't care

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Preliminary T4312816A

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*note : 1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.

2. Bank active & read/write are controlled by BA0 – BA1.

BA0 BA1 Active & Read/Write

0 0 Bank A

1 0 Bnak B

0 1 Bank C

1 1 Bnak D

3. Enable and disable auto precharge function are controlled by A10/AP in read/wirte command.

A10 Auto-Precharge

0 Disable (End of burst)

1 Enable (End of burst)

BA0 BA1 Operation

0 0 Enable read/write command for bank A .

1 0 Enable read/write command for bank B .

0 1 Enable read/write command for bank C .

1 1 Enable read/write command for bank D .

4. A10/AP and BA control bank precharge when precharge command is asserted.

A10/AP BA0 BA1 precharge

0 0 0 Bank A

0 1 0 Bank B

0 0 1 Bank C

0 1 1 Bank D

1 X X All Bamks

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Preliminary T4312816A

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Power Up Sequence

CLOCK

C KE

C S

R AS

C AS

ADDR

B A

A10/AP

DQ

WE

DQM

012345678910111213141516171819

tCCD

H igh level is necessary

tRP tRC tRC

Key RAa

Key

Key RAa

H igh level is necessary

High-Z

SS

SS SS

SS

Precharge

A ll Ban k s Auto

Refresh A uto Refresh M ode R egister Set (A-Bank)

Row

Active

:D on't care

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Read & Write Cycle at Same Bank @Burst Length = 4

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

CL = 2

CL = 3

W E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

tRC

D Q M

D Q

:D on't care

*Note1

tRCD

*Note2

*Note4

*Note3

*Note3 *Note4

Ra Ca0 Rb Cb0

RbRa

Qa0 Qa1 Qa2 Qa3

Db0

Db1

Db2

Db3

tRAC

tSAC

tOH

tSAC

tSHZ

tRDL

Row

A c tive (A -

Bank)

R ead (A -

Bank) Precharg

e (A -

Bank)

Row Active

(A-Bnak) W rite ( A-

Bnak) Precharge

(a-Bnak)

*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is

available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock.

3. Access time from Row active command. tCC*(tRCD+CAS latency-1)+tSAC

4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)

Burst can’t end in Full Page Mode.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.17

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Page Read & Write Cycle at Same Bank @ Burst Length = 4

CLOCK

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L =2

C L =3

W E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

tCCD

D Q M

D Q

:D on't care

Row Active

(A-Bnak) R ead (A -

Bnak) R ead (A -

Bnak) W rite (A -

Bnak) Precharge

(A-Bnak)

*Note1

*Note3

*Note2

tRCD

tRDL

tCDL

Ra Ca0 Cb0 Cc0 Cd0

Qa0 Qa1

Qb0

Qb1 Qb2

Qb1

Dc0 Dc1

Dd0 Dd1

Dd0 Dd2

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to

avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge before

end of burst. Input data after Row precharge cycle will be masked internally.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.18

Publication Date: APR. 2003

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Page Read Cycle at Different Bank @ Burst Length = 4

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

CL = 2

CL = 3

W E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

D Q M

D Q

:D on't care

*Note1

*Note2

RAa CAa RBb CBb CAc CBd CAe

RAa RBb

QAa0 QAa1 QAa2 QAa3

QBb0

QBb1 QBb2 QBb3

QAc0 QAc1

QBd0

QBd1

QAe0

QAe1

Row Active

(A-Bank) Read (A -

Bank)

Row Active

(B-B ank)

R ead (B -

Bank) Read (A -

Bank) Read (B -

Bank) Read (A -

Bank) Precharge

(A-Bank)

*Note : 1. CS can be don’t cared when RAS,CAS and WE are high at the clock high going edge.

2. To interrupt a burst resd by row precharge, both the read and the precharge banks must be the same.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.19

Publication Date: APR. 2003

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Page Write cycle at Different Bank @ Burst Length = 4

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

DQ

W E

DQM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

:D on't care

Row Active

(A-Bank)

Write (A-

Bank)

Row Active

(B-Bank) Write (B-

Bank) Write (A-

Bank) Write (B-

Bank) Precharge

(A-Bank)

*Note1

*Note2

tCDL tRDL

RAa CAa RBb CBb CAc CBd

RAa RBb

DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1

*Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.20

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Read & Write Cycle at Different Bank @ Burst Length = 4

CLOCK

CK E

CS

RA S

CA S

ADDR

BA

A10/AP

CL =2

CL =3

W E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

D Q M

D Q

:D on't care

QAa0

RAa CAa RBb CBb RAc CAc

RAa RBb RAc

QAa1 QAa2 QAa3

QAa0 QAa1 QAa2 QAa3

DBb0 DBb1 DBb2 DBb3

QAc0

QAc1 QAc2

QAc1

*Note1

tCDL

Row Active

(A-Bank) Read (A -

Bank) Row Active

(B-B ank) Precharge

(A-Bank) W rite ( B-

Bank)

Row Active

(A-Bank)

R ead (A -

Bank)

*Note : 1. tCDL should be met to complete write.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.21

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Read & Write Cycle with Auto Precharge @ Burst Length = 4

CLOCK

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L =2

C L =3

W E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

D Q M

D Q

:D on't care

Row Active

(A-Bank) Row Active

(B-Bank)

R e ad w ith A u to

precharge (A-

Bank)

CL=2 Auto

Precharge S tart

P o in t ( A -B a n k )

CL=3 Auto

Precharge S tart

P o in t ( A -B a n k )

W rite w ith Au to

Precharge (B -

Bank)

Auto Precharge

S tart P o in t (A -

Bank)

Ra Rb Ca Cb

Ra Rb

Qa0 Qa1 Qa2 Qa3

Db0

Db1

Db2

Db3

*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.

(In the case of Burst Length = 1 & 2 and BRSW mode)

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Preliminary T4312816A

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Clock suspension & DQM Operation Cycle @ CAS Latency = 2 ,Burst Length = 4

CLOCK

CKE

C S

RAS

CAS

ADDR

B A

A10/AP

D Q

W E

DQM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

:Don't care

Row Active Read Clock

Suspension Read Read QDM Write

Write QDMClock

Suspension

Write QDM

*Note3

Ra Ca Cb Cc

Ra

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Dc0 Dc2

tSHZ

*Note 1. DQM is needed to prevent bus contention.

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Preliminary T4312816A

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Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length=Full Page

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

CL = 2

CL = 3

W E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

D Q M

D Q

:D on't care

RAa CAa CAb

RAa

QAa0 QAa1 QAa2 QAa3 QAa4

QAb0

QAb0 QAb1

QAb1 QAb2 QAb3

QAb2

QAb4

QAb3

QAb5

QAb4 QAb5

*Note2 1

2 2

1

Row Active

(A-Bank) Read (A -

Bank) Read (A -

Bank)

Burst Stop Precharge

(A-Bank)

*Note : 1. Burst can’t end in full page mode, so auto precharge can’t issue.

2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the lable 1,2 on them.

But at burst write, burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of ‘Full Page write burst stop cycle’.

3. Burst stop is valid at every burst length.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.24

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Write Interrupted by Prechareg Command & Write Burst Stop Cycle @ Burst Length=Full Page

CLOCK

CKE

C S

RAS

CAS

ADDR

B A

A10/AP

D Q

W E

DQM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

:Don't care

Row Active

(A-Bank) Write (A-

Bank) Burst Stop W rite (A-

Bank) Precharge

(A-Bank)

RAa CAa CAb

RAa

DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5

*Note3

tBDL tRDL

*Note : 1. Burst can’t end in full page mode, so auto precharge can’t issue.

2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell.

It is defined by AC parameter of tRDL.

DQM at write interrupted by precharge command is needed to prevent invalid write.

Input data after Row precharge cycle will be masked internally.

3. Burst stop is valid at every burst length.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.25

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Burst Read Single bit Write Cycle @ Burst Length = 2

CLOCK

CK E

CS

RA S

CA S

ADDR

BA

A10/AP

CL =2

CL =3

W E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HIGH

D Q M

D Q

:D on't care

*Note2

RAa CAa RBb CAb RAc CBc CAd

RAa RBb RAc

DAa0

DAb0

DAb1

DAb1 DBc0

DBc0 DAd0 DAd1

DAd0 DAd1

Row Active

(A-Bank)

W rite (A -

Bank)

Row Active

(A-Bank)

R ea d w ith Au to

Prech arge (A -

Bank)

Row Active

(A-Bank) W rite w ith Au to

Prech arge (A -

Bank)

R ead (A -

Bank) Precharge

(A-Bank)

*Note : 1. BRSW modes is enabled by setting A9 ‘High’ at MRS (Mode Register Set).

At the BRSW Mode, the burst length at write is fixed to ‘1’ regardless of programmed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not

be violated.

Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command,

the precharge command will be issued after two clock cycle.

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Preliminary T4312816A

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Active/ Precharge Power Down Mode @ CAS latency = 2, Butsr length = 4

CLOCK

C KE

C S

R AS

C AS

ADDR

B A

A10/AP

D Q

WE

DQM

0 1 2 3 4 5 6 7 8 9 10111213141516171819

:Do n't c ar e

Precharge

Power-

Down Entry

Precharge

Power-

Down Exit

Row Active

Active

Power-

Down Entry

Active

Power-

Down Exit

Read Precharge

Qa0 Qa1 Qa2

Ra Ca

Ra

tSHZ

SS

tsstsstss

*Note1

*Note3

*Note2

SS

*Note : 1. Both banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least 1CLK+tSS prior to Row active command.

3. Can not violate minimum refresh specification.(64ms)

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Preliminary T4312816A

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Self Refresh Entry & Exit Cycle

CLOCK

CKE

C S

RAS

CAS

ADDR

B A

A10/AP

D Q

W E

DQM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

:D on't care

SS

*Note2

*Note1

*Note3

*Note4

*Note6

*Note7

*Note5

tSS

tRCmin

Hi-z

S e lf R e fr es h E n try S e lf R e fr es h E x it A u to R e fresh

Hi-z

*Note : TO ENTER SELF REFRESH MODE

1. CS ,RAS & CAS with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs inculding the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays ‘Low’.

Cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5. CS starts from high.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the

system uses burst refresh.

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Preliminary T4312816A

TM Technology Inc. reserves the right P.28

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Mode Register Set Cycle Auto Refresh Cycle

CLOCK

CKE

CS

RAS

CAS

ADDR

DQ

W E

DQM

0123456 012345678910

:D on't care

SS

*Note2

*Note1

*Note3

tRPC

Auto Refresh New CommandMRS New Command

Hi-z

Key Key

Hi-z

HIGH

*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE

*Note : 1. CS ,RAS,CAS & WE activation at the same clock cycle with address key will set internal

mode register.

2. Minimum 2 clock cycles should be met before new RAS activation.

3. Please refer to Mode Register Set table.

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Preliminary T4312816A

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PACKAGE DIMENSIONS

54 LEAD TSOP -II (400 mil)

D

2854

127

E1 E

A

A2

B

A1

C

B1

θ

Dimension in mm Dimension in inch

Symbol Min Nom Max Min Nom Max

A - - 1.2 - - 0.047

A1 0.4 0.5 0.6 0.016 0.020 0.024

A2 - 0.15 - 0.006

B 0.24 0.32 0.40 0.009 0.012 0.016

B1 - 0.8 - 0.0315

C 0.05 0.10 0.15 0.002 0.004 0.006

D 22.12 22.22 22.62 0.871 0.875 0.905

E 11.56 11.76 11.96 0.455 0.463 0.471

E1 10.06 10.16 10.26 0.396 0.400 0.404

θ 0 - 8 0 - 8