Theseus Gold 48 Integrated Circuit for Smartcards
Theseustm Gold 48 Specification Rev 1
Page 1 Date 02/11/99 Document Number THEDATPUB v1.0
Environment
Single 3.0v to 5v supply ± 10%
-20 to +80 0C operating temp
Max supply current 10 mA
> 2 Kv ESD Protection
CPU
Software compatible CMOS 8051
industry standard
High speed non-standard architecture
Traps for illegal op codes
Standby and selectable powerdown
modes
Memory Control
Hardware Memory/ Security
Management
Application Secure OS partitioning
EEprom Erase write control and
verification logic
I/O
ISO 7816-3 compliant electrical
interface
ISO 7816-3 compliant reset and
response T=0 T=1 protocols
Security
Out of frequency, out of voltage
detection
Unique chip identification number
Notification of tampering
Hardware Random Number
Generator
Internal clock generation
Memory
32K OTPROM
1K ROM
16K EEPROM 10 year data
retention, >100k read write cycles
1024 bytes Ram
Chip
less than 16 mm2
180 microns max thickness
Industry Standard
8-bit 8051 core
ISO 7816-3 interface
Clocks
Security interface
Reset and Control
Memory Mapping
and
Control Interface
1K Bytes
RAM 1K Bytes
Masked ROM 16K Bytes
EEPROM
Char
g
e Pum
p
32 K Bytes
OTPROM
Random
Number
Generator
Theseus Gold 48 Integrated Circuit for Smartcards
Theseustm Gold 48 Specification Rev 1
Page 2 Date 02/11/99 Document Number THEDATPUB v1.0
Introduction.
The THESEUS Gold 48 is a member of the Theseus family of devices designed
specifically for smart card applications. It is software compatible with the industry
standard 8051 8-bit microprocessor, to guarantee the maximum availability of tested
software. The hardware implementation of the core is a modern design not relying on
microcode, with an increase of up to 4 times on a standard 8051's clocks per instruction.
As with all Theseus smart card Ics, it is fully compatible with the ISO-7816
specifications.
Security of the family of devices makes them particularly suitable in electronic commerce
and sensitive data areas. This is accomplished in hardware, with not only protection
against out of parameter operation of the device, but hardware memory management to
protect against software security attacks. The CPU clock is derived from its own internal
oscillator, which prevents attacks by clock manipulation, or extrapolating program
execution by monitoring current variations on clock edges.
The need to support the emerging multifunction cards, require that the device under
software control to be able to download an application and run it when the device is in the
field embedded in a smart card. The device has to be protected against the downloading
of attack software designed to corrupt or uncover the working or data contained in the
device. Traditionally this has been a software function, which relies on the total integrity
of the embedded software. The THESEUS Gold 48 implements the first level of
protection in hardware. This maximizes the security of the device, and allows the
reuseability of developed certified code, by isolating it from the actual hardware
implementation of the device. This protection mechanism allows for a Secure Operating
System to be embedded into the device at manufacture, which has access rights to
features of the device that are denied to applications that can be loaded into the device at
manufacture or in the field.
In systems where application isolation is not needed, the security mechanism acts as a
general protection unit trapping software errors.
SERIAL INTERFACE.
The THESEUS gold 48 has only one interface this is a serial interface that is compliant
with the ISO 7816-3 specification. Several modes are implemented that allow serial
connections at 9600 to 15200 bits per second. The THESEUS Gold 48 is designed to
be compatible with the ISO 7816 specifications defining the characteristics of Integrated
Circuit Cards commonly referred to as smart cards. The mapping of the pins used by the
THESEUS Gold 48 and the ISO specification is highlighted in the following table.
Pin Definitions
Theseus Gold 48 Integrated Circuit for Smartcards
Theseustm Gold 48 Specification Rev 1
Page 3 Date 02/11/99 Document Number THEDATPUB v1.0
Assignment Symbol ISO 7816-3 card THESEUS
Gold 48
Supply voltage Vcc C1 Vcc
Reset signal RST C2 RST
Clock signal CLK C3 CLK
Reserved C4 -
Ground GND C5 GND
Programming
Voltage VPP C6 -
Data input/output I/O C7 I/O
Reserved C8 -
Clocks
The THESEUS Gold 48 has its own internal oscillator. This allows the core of the
device to be independent of the external clock. The processor can also be clocked much
faster than the IO CLK signal. This ensures the elimination of fraudulent attacks
involving frequency jitter and unequal mark space ratios. The internal clock generator is
connected to the core via a divider that is under the control of the software. This allows
the Operating System writer to control the trade off between execution speed and power
drawn by the device. This can be set to extend battery life in hand-held applications
where slow interfaces are involved.
Random Number Generator
The on-chip random number generator is fully FIPS compliant, providing a rapid stream
of truly random numbers. This allows use of the random numbers generated beyond just
the provision of numbers for randomizing transmissions.
Anti-tampering.
The THESEUSTM Gold 48 has extensive anti-tampering provision including the
monitoring of the connection to the device to ensure that deviations beyond a prescribed
criteria result in the device being closed down before its operating conditions are violated.
On chip voltage regulators
Several on-chip regulators isolate the various elements of the device from variations and
fluctuations in the supply voltage. This allows elements to be characterized precisely, as
they operate at one fixed voltage, which in turn maximizes the endurance of the device,
and simplifies the protection from tampering.
Testability
The THESEUSTM Gold 48 has extensive built in self test, that allows rapid post
manufacture verification of the integrity of the device, minimizing the chances of field
failures due to the card manufacturing process.