AD650A - Analog Devices - Datasheet.Live

PIN CONFIGURATION

REV. C

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Voltage-to-Frequency and

Frequency-to-Voltage Converter

AD650

FEATURES

V/F Conversion to 1 MHz

Reliable Monolithic Construction

Very Low Nonlinearity

0.002% typ at 10 kHz

0.005% typ at 100 kHz

0.07% typ at 1 MHz

Input Offset Trimmable to Zero

CMOS or TTL Compatible

Unipolar, Bipolar, or Differential V/F

V/F or F/V Conversion

Available in Surface Mount

MIL-STD-883 Compliant Versions Available

PRODUCT DESCRIPTION

The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage

converter) provides a combination of high frequency operation

and low nonlinearity previously unavailable in monolithic form.

The inherent monotonicity of the V/F transfer function makes

the AD650 useful as a high-resolution analog-to-digital converter.

A flexible input configuration allows a wide variety of input volt-

age and current formats to be used, and an open-collector output

with separate digital ground allows simple interfacing to either

standard logic families or opto-couplers.

The linearity error of the AD650 is typically 20 ppm (0.002%

of full scale) and 50 ppm (0.005%) maximum at 10 kHz full

scale. This corresponds to approximately 14-bit linearity in an

analog-to-digital converter circuit. Higher full-scale frequencies

or longer count intervals can be used for higher resolution con-

versions. The AD650 has a useful dynamic range of six decades

allowing extremely high resolution measurements. Even at 1 MHz

full scale, linearity is guaranteed less than 1000 ppm (0.1%) on

the AD650KN, BD, and SD grades.

In addition to analog-to-digital conversion, the AD650 can be used

in isolated analog signal transmission applications, phased locked-

loop circuits, and precision stepper motor speed controllers. In

the F/V mode, the AD650 can be used in precision tachometer

and FM demodulator circuits.

The input signal range and full-scale output frequency are user-

programmable with two external capacitors and one resistor.

Input offset voltage can be trimmed to zero with an external

potentiometer.

The AD650JN and AD650KN are offered in a plastic 14-lead

DIP package. The AD650JP is available in a 20-lead plastic

leaded chip carrier (PLCC). Both plastic packaged versions of the

AD650 are specified for the commercial (0°C to +70°C) tempera-

ture range. For industrial temperature range (–25°C to +85°C)

applications, the AD650AD and AD650BD are offered in a

ceramic package. The AD650SD is specified for the full –55°C

to +125°C extended temperature range.

PRODUCT HIGHLIGHTS

1. In addition to very high linearity, the AD650 can operate at

full-scale output frequency up to 1 MHz. The combination of

these two features makes the AD650 an inexpensive solution

for applications requiring high resolution monotonic A/D

conversion.

2. The AD650 has a very versatile architecture that can be con-

figured to accommodate bipolar, unipolar, or differential

input voltages, or unipolar input currents.

3. TTL or CMOS compatibility is achieved using an open

collector frequency output. The pull-up resistor can be

connected to voltages up to +30 V, or +15 V or +5 V for

conventional CMOS or TTL logic levels.

4. The same components used for V/F conversion can also be

used for F/V conversion by adding a simple logic biasing net-

work and reconfiguring the AD650.

5. The AD650 provides separate analog and digital grounds.

This feature allows prevention of ground loops in real-world

applications.

6. The AD650 is available in versions compliant with MIL-

STD-883. Refer to the Analog Devices Military Products

Databook or current AD650/883B data sheet for detailed

specifications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD650J/AD650A AD650K/AD650B AD650S

Model Min Typ Max Min Typ Max Min Typ Max Units

DYNAMIC PERFORMANCE

Full-Scale Frequency Range 1 1 1 MHz

Nonlinearity

MAX

= 10 kHz 0.002 0.005 0.002 0.005 0.002 0.005 %

Nonlinearity

MAX

= 100 kHz 0.005 0.02 0.005 0.02 0.005 0.02 %

Nonlinearity

MAX

= 500 kHz 0.02 0.05 0.02 0.05 0.02 0.05 %

Nonlinearity

MAX

= 1 MHz 0.1 0.05 0.1 0.05 0.1 %

Full-Scale Calibration Error

, 100 kHz ±5±5±5%

Full-Scale Calibration Error

, 1 MHz ±10 ±10 ±10 %

vs. Supply

–0.015 +0.015 –0.015 +0.015 –0.015 +0.015 % of FSR/V

vs. Temperaturc

A, B, and S Grades

at 10 kHz ±75 ±75 ±75 ppm/°C

at 100 kHz ±150 ±150 ±150 ppm/°C

J and K Grades

at 10 kHz ±75 ±75 ppm/°C

at 100 kHz ±150 ±150 ppm/°C

BIPOLAR OFFSET CURRENT

Activated by 1.24 kΩ Between Pins 4 and 5 0.45 0.5 0.55 0.45 0.5 0.55 0.45 0.5 0.55 mA

DYNAMIC RESPONSE

Maximum Settling Time for Full Scale

Step Input 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs

Overload Recovery Time

Step Input 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs

ANALOLG INPUT AMPLIFIER (V/F Conversion)

Current Input Range (Figure 1) 0 +0.6 0 +0.6 0 +0.6 mA

Voltage Input Range (Figure 5) –10 0 –10 0 –10 0 V

Differential Impedance 2 MΩ储10 pF 2 MΩ储10 pF 2 MΩ储10 pF

Common-Mode Impedance 1000 MΩ储10 pF 1000 MΩ储10 pF 1000 MΩ储10 pF

Input Bias Current

Noninverting Input 40 100 40 100 40 100 nA

Inverting Input ±8ⴞ20 ±8ⴞ20 ±8ⴞ20 nA

Input Offset Voltage

(Trimmable to Zero) ⴞ4ⴞ4ⴞ4mV

vs. Temperature (T

MIN

to T

MAX

)±30 ±30 ±30 µV/°C

Safe Input Voltage ±V

±V

COMPARATOR (F/V Conversion)

Logic “0” Level –V

–1 –V

+1 V

Logic “1” Level 0 +V

0+V

Pulse Width Range

0.1 (0.3 × t

) 0.1 (0.3 × t

)µs

Input Impedance 250 250 250 kΩ

OPEN COLLECTOR OUTPUT (V/F Conversion)

Output Voltage in Logic “0”

SINK

≤ 8 mA, T

MIN

to T

MAX

0.4 0.4 0.4 V

Output Leakage Current in Logic “1” 100 100 100 nA

Voltage Range

0 +36 0 +36 0 +36 V

AMPLIFIER OUTPUT (F/V Conversion)

Voltage Range (1500 Ω min Load Resistance) 0 +10 0 +10 0 +10 V

Source Current (750 Ω max Load Resistance) 10 10 10 mA

Capacitive Load (Without Oscillation) 100 100 100 pF

POWER SUPPLY

Voltage, Rated Performance ±9ⴞ18 ±9ⴞ18 ±9ⴞ18 V

Quiescent Current 88 8mA

TEMPERATURE RANGE

Rated Performance – N Package 0 +70 0 +70 °C

Rated Performance – D Package –25 +85 –25 +85 –55 +125 °C

NOTES

Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale.

Full-scale calibration error adjustable to zero.

Measured at full-scale output frequency of 100 kHz.

Refer to F/V conversion section of the text.

Referred to digital ground.

Specifications subject to change without notice.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those test are used to calculate outgoing quality levels. All min and max

specifications are guaranteed, although only those shown in boldface are tested on all production units.

AD650–SPECIFICATIONS

(@ +25ⴗC, with V

= ⴞ15 V, unless otherwise noted)

REV. C

–2–

AD650

REV. C –3–

ABSOLUTE MAXIMUM RATINGS

Total Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V

Storage Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±10 V

Maximum Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . ±V

Open Collector Output Voltage Above Digital GND . . . . . 36 V

Open Collector Output Current . . . . . . . . . . . . . . . . . . 50 mA

Amplifier Short Circuit to Ground . . . . . . . . . . . . . . Indefinite

Comparator Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±V

PIN CONFIGURATION

NO. D-14 N-14 P-20A

OUT

2 +IN +IN V

OUT

3 –IN –IN +IN

4 BIPOLAR OFFSET BIPOLAR OFFSET –IN

CURRENT CURRENT

5–V

–V

6 ONE SHOT ONE SHOT BIPOLAR OFFSET

CAPACITOR CAPACITOR CURRENT

7NC NC NC

OUTPUT

–V

9 COMPARATOR COMPARATOR ONE SHOT

INPUT INPUT CAPACITOR

10 DIGITAL GND DIGITAL GND NC

11 ANALOG GND ANALOG GND NC

12 +V

OUTPUT

13 OFFSET NULL OFFSET NULL COMPARATOR

INPUT

14 OFFSET NULL OFFSET NULL DIGITAL GND

15 NC

16 ANALOG GND

17 NC

18 +V

19 OFFSET NULL

20 OFFSET NULL

ORDERING GUIDE

Gain

Tempco Specified

ppm/ ⴗC 1 MHz Temperature Package Package

Model 100 kHz Linearity Range ⴗC Description Option

AD650JN 150 typ 0.1% typ 0 to +70 Plastic DIP N-14

AD650KN 150 typ 0.1% max 0 to +70 Plastic DIP N-14

AD650JP 150 typ 0.1% typ 0 to +70 Plastic Leaded Chip Carrier (PLCC) P-20A

AD650AD 150 max 0.1% typ –25 to +85 Ceramic DIP D-14

AD650BD 150 max 0.1% max –25 to +85 Ceramic DIP D-14

AD650SD 150 max 0.1% max –55 to +125 Ceramic DIP D-14

AD650

REV. C

–4–

CIRCUIT OPERATION

UNIPOLAR CONFIGURATION

The AD650 is a charge balance voltage-to-frequency converter. In

the connection diagram shown in Figure 1, or the block diagram

of Figure 2a, the input signal is converted into an equivalent cur-

rent by the input resistance R

. This current is exactly balanced

by an internal feedback current delivered in short, timed bursts

from the switched 1 mA internal current source. These bursts of

current may be thought of as precisely defined packets of charge.

The required number of charge packets, each producing one

pulse of the output transistor, depends upon the amplitude of

the input signal. Since the number of charge packets delivered

per unit time is dependent on the input signal amplitude, a linear

voltage-to-frequency transformation will be accomplished. The

frequency output is furnished via an open collector transistor.

A more rigorous analysis demonstrates how the charge balance

voltage-to-frequency conversion takes place.

A block diagram of the device arranged as a V-to-F converter is

shown in Figure 2a. The unit is comprised of an input integra-

tor, a current source and steering switch, a comparator and a

one-shot. When the output of the one-shot is low, the current

steering switch S

diverts all the current to the output of the op

amp; this is called the Integration Period. When the one-shot

has been triggered and its output is high, the switch S

diverts

all the current to the summing junction of the op amp; this is

called the Reset Period. The two different states are shown in

Figure 2 along with the various branch currents. It should be

noted that the output current from the op amp is the same for

either state, thus minimizing transients.

Figure 1. Connection Diagram for V/F Conversion,

Positive Input Voltage

Figure 2a. Block Diagram

Figure 2b. Reset Mode Figure 2c. Integrate Mode

Figure 2d. Voltage Across C

INT

The positive input voltage develops a current (I

= V

)

which charges the integrator capacitor C

INT

. As charge builds up

on C

INT

, the output voltage of the integrator ramps downward

towards ground. When the integrator output voltage (Pin 1)

crosses the comparator threshold (–0.6 volt) the comparator

triggers the one shot, whose time period, t

is determined by

the one shot capacitor C

Specifically, the one shot time period is:

OS =C

OS ×6.8 ×103sec /F+3.0 ×10–7 sec

(1)

The Reset Period is initiated as soon as the integrator output

voltage crosses the comparator threshold, and the integrator

ramps upward by an amount:

∆V=tOS •dV

dt =tOS

CINT

1mA –IN

()

(2)

After the Reset Period has ended, the device starts another Inte-

gration Period, as shown in Figure 2, and starts ramping downward

again. The amount of time required to reach the comparator

threshold is given as:

TI=∆V

=tOS /CINT (1 mA –IIN )

IN/CINT

=tOS 1mA

IIN

–1







(3)

The output frequency is now given as:

fOUT =1

tOS +TI

=IIN

tOS ×1mA =0.15 F•Hz

VIN /RIN

COS +4.4 ×10–11F

(4)

Note that C

INT

, the integration capacitor has no effect on the

transfer relation, but merely determines the amplitude of the

sawtooth signal out of the integrator.

One Shot Timing

A key part of the preceding analysis is the one shot time period

that was given in equation (1). This time period can be broken

down into approximately 300 ns of propagation delay, and a sec-

ond time segment dependent linearly on timing capacitor C

When the one shot is triggered, a voltage switch that holds Pin 6

AD650

REV. C –5–

at analog ground is opened allowing that voltage to change. An

internal 0.5 mA current source connected to Pin 6 then draws

its current out of C

, causing the voltage at Pin 6 to decrease

linearly. At approximately –3.4 V, the one shot resets itself,

thereby ending the timed period and starting the V/F conversion

cycle over again. The total one shot time period can be written

mathematically as:

OS =∆VC

IDISCHARGE

+TGATE DELAY

(5)

substituting actual values quoted above,

OS =–3.4 V×C

–0.5 ×10–3 A+300 ×10–9 sec

(6)

This simplifies into the timed period equation given above.

COMPONENT SELECTION

Only four component values must be selected by the user. These

are input resistance R

, timing capacitor C

, logic resistor R2,

and integration capacitor C

INT

. The first two determine the

input voltage and full-scale frequency, while the last two are

determined by other circuit considerations.

Of the four components to be selected, R2 is the easiest to

define. As a pull-up resistor, it should be chosen to limit the

current through the output transistor to 8 mA if a TTL maxi-

mum V

of 0.4 V is desired. For example, if a 5 V logic supply

is used, R2 should be no smaller than 5 V/8 mA or 625 Ω. A

larger value can be used if desired.

and C

are the only two parameters available to set the

full- scale frequency to accommodate the given signal range.

The “swing” variable that is affected by the choice of R

and

is nonlinearity. The selection guide of Figure 3 shows this

quite graphically. In general, larger values of C

and lower

full-scale input currents (higher values of R

) provide better

linearity. In Figure 3, the implications of four different choices

of R

are shown. Although the selection guide is set up for a

unipolar configuration with a zero to 10 V input signal range,

the results can be extended to other configurations and input

signal ranges. For a full scale frequency of 100 kHz (corre-

sponding to 10 V input), you can see that among the available

choices, R

= 20 k and C

= 620 pF gives the lowest nonlin-

earity, 0.0038%. Also, if you wish to use the highest frequency

that will give the 20 ppm minimum nonlinearity, it is approxi-

mately 33 kHz (40.2 kΩ and 1000 pF).

For input signal spans other than 10 V, the input resistance

must be scaled proportionately. For example, if 100 kΩ is called

out for a 0 V–10 V span, 10k would be used with a 0 V–1 V

span, or 200 kΩ with a ±10 V bipolar connection.

The last component to be selected is the integration capacitor

INT

. In almost all cases, the best value for C

INT

can be calcu-

lated using the equation:

INT =10–4F/sec

fMAX

(1000 pF minimum)

(7)

When the proper value for C

INT

is used, the charge balance

architecture of the AD650 provides continuous integration of

the input signal, hence large amounts of noise and interference

Figure 3a. Full-Scale Frequency vs. C

Figure 3b. Typical Nonlinearity vs. C

can be rejected. If the output frequency is measured by counting

pulses during a constant gate period, the integration provides

infinite normal-mode rejection for frequencies corresponding to

the gate period and its harmonics. However, if the integrator

stage becomes saturated by an excessively large noise pulse, the

continuous integration of the signal will be interrupted, allowing

the noise to appear at the output. If the approximate amount of

noise that will appear on C

INT

is known (V

NOISE

), the value of

INT

can be checked using the following inequality:

INT

×1×10

–3

–3V–V

NOISE

(8)

For example, consider an application calling for a maximum

frequency of 75 kHz, a 0 volt–1 volt signal range, and supply

voltages of only ±9 volts. The component selection guide of Fig-

ure 3 is used to select 2.0 kΩ for R

and 1000 pF for C

. This

results in a one shot time period of approximately 7 µs. Sub-

stituting 75 kHz into equation 7 yields a value of 1300 pF for

INT

. When the input signal is near zero, 1 mA flows through the

integration capacitor to the switched current sink during the reset

phase, causing the voltage across C

INT

to increase by approximately

5.5 volts. Since the integrator output stage requires approximately

3 volts head room for proper operation, only 0.5 volt margin

remains for integrating extraneous noise on the signal line. A

negative noise pulse at this time might saturate the integrator,

causing an error in signal integration. Increasing C

INT

to 1500 pF

or 2000 pF will provide much more noise margin, thereby elimi-

nating this potential trouble spot.

AD650

REV. C

–6–

BIPOLAR V/F

Figure 4 shows how the internal bipolar current sink is used to

provide a half-scale offset for a ±5 V signal range, while provid-

ing a 100 kHz maximum output frequency. The nominally 0.5 mA

(±10%) offset current sink is enabled when a 1.24 kΩ resistor is

connected between Pins 4 and 5. Thus, with the grounded 10 kΩ

nominal resistance shown, a –5 V offset is developed at Pin 2.

Since Pin 3 must also be at –5 V, the current through R

10 V/40 kΩ = +0.25 mA at V

= +5 V, and 0 mA at

= –5 V.

Components are selected using the same guidelines outlined for

the unipolar configuration with one alteration. The voltage

across the total signal range must be equated to the maximum

Figure 4. Connections for

5 V Bipolar V/F with 0 to

100 kHz TTL Output

input voltage in the unipolar configuration. In other words, the

value of the input resistor R

is determined by the input voltage

span, not the maximum input voltage. A diode from Pin 1 to

ground is also recommended. This is further discussed in the

Other Circuit Conditions section.

As in the unipolar circuit, R

and C

must have low tempera-

ture coefficients to minimize the overall gain drift. The 1.24 kΩ

resistor used to activate the 0.5 mA offset current should also

have a low temperature coefficient. The bipolar offset current

has a temperature coefficient of approximately –200 ppm/°C.

UNIPOLAR V/F, NEGATIVE INPUT VOLTAGE

Figure 5 shows the connection diagram for V/F conversion of

negative input voltages. In this configuration full-scale output

frequency occurs at negative full-scale input, and zero output

frequency corresponds with zero input voltage.

A very high impedance signal source may be used since it only

drives the noninverting integrator input. Typical input imped-

ance at this terminal is 1 GΩ or higher. For V/F conversion of

positive input signals using the connection diagram of Figure 1,

the signal generator must be able to source the integration cur-

rent to drive the AD650. For the negative V/F conversion circuit

of Figure 5, the integration current is drawn from ground

through R1 and R3, and the active input is high impedance.

Circuit operation for negative input voltages is very similar to

positive input unipolar conversion described in a previous sec-

tion. For best operating results use component equations listed

in that section.

Figure 5. Connection Diagram for V/F Conversion,

Negative Input Voltage

F/V CONVERSION

The AD650 also makes a very linear frequency-to-voltage

converter. Figure 6 shows the connection diagram for F/V con-

version with TTL input logic levels. Each time the input signal

crosses the comparator threshold going negative, the one shot is

activated and switches 1 mA into the integrator input for a

measured time period (determined by C

). As the frequency

increases, the amount of charge injected into the integration

capacitor increase proportionately. The voltage across the inte-

gration capacitor is stabilized when the leakage current through

R1 and R3 equals the average current being switched into the

integrator. The net result of these two effects is an average output

voltage which is proportional to the input frequency. Optimum

performance can be obtained by selecting components using the

same guidelines and equations listed in the V/F Conversion section.

The reader is referred to Analog Devices' Application Note

AN-279 where a more complete description of this application

can be found.

Figure 6. Connection Diagram for F/V Conversion

HIGH FREQUENCY OPERATION

Proper RF techniques must be observed when operating the

AD650 at or near its maximum frequency of 1 MHz. Lead

lengths must be kept as short as possible, especially on the one

shot and integration capacitors, and at the integrator summing

junction. In addition, at maximum output frequencies above

500 kHz, a 3.6 kΩ pull-down resistor from Pin 1 to –V

is required

(see Figure 7). The additional current drawn through the pull-

down resistor reduces the op amp’s output impedance and

improves its transient response.

AD650

REV. C –7–

Figure 7. 1 MHz V/F Connection Diagram

DECOUPLING AND GROUNDING

It is good engineering practice to use bypass capacitors on the

supply-voltage pins and to insert small-valued resistors (10 Ω to

100 Ω) in the supply lines to provide a measure of decoupling

between the various circuits in a system. Ceramic capacitors of

0.1 µF to 1.0 µF should be applied between the supply-voltage

pins and analog signal ground for proper bypassing on the AD650.

In addition, a larger board level decoupling capacitor of 1 µF to

10 µF should be located relatively close to the AD650 on each

power supply line. Such precautions are imperative in high reso-

lution data acquisition applications where one expects to exploit

the full linearity and dynamic range of the AD650. Although

some types of circuits may operate satisfactorily with power sup-

ply decoupling at only one location on each circuit board, such

practice is strongly discouraged in high accuracy analog design.

Separate digital and analog grounds are provided on the AD650.

The emitter of the open collector frequency output transistor is

the only node returned to the digital ground. All other signals

are referred to analog ground. The purpose of the two separate

grounds is to allow isolation between the high precision analog

signals and the digital section of the circuitry. As much as sev-

eral hundred millivolts of noise can be tolerated on the digital

ground without affecting the accuracy of the VFC. Such ground

noise is inevitable when switching the large currents associated

with the frequency output signal.

At 1 MHz full scale, it is necessary to use a pull-up resistor of

about 500 Ω in order to get the rise time fast enough to provide

well defined output pulses. This means that from a 5 volt logic

supply, for example, the open collector output will draw 10 mA.

This much current being switched will surely cause ringing on

long ground runs due to the self inductance of the wires. For

instance, #20 gauge wire has an inductance of about 20 nH per

inch; a current of 10 mA being switched in 50 ns at the end of

12 inches of 20 gauge wire will produce a voltage spike of 50 mV.

The separate digital ground of the AD650 will easily handle

these types of switching transients.

A problem will remain from interference caused by radiation of

electro-magnetic energy from these fast transients. Typically, a

voltage spike is produced by inductive switching transients;

these spikes can capacitively couple into other sections of the

circuit. Another problem is ringing of ground lines and power

supply lines due to the distributed capacitance and inductance

of the wires. Such ringing can also couple interference into sen-

sitive analog circuits. The best solution to these problems is

proper bypassing of the logic supply at the AD650 package. A

1 µF to 10 µF tantalum capacitor should be connected directly

to the supply side of the pull-up resistor and to the digital

ground—Pin 10. The pull-up resistor should be connected

directly to the frequency output—Pin 8. The lead lengths on the

bypass capacitor and the pull up resistor should be as short as

possible. The capacitor will supply (or absorb) the current tran-

sients, and large ac signals will flow in a physically small loop

through the capacitor, pull up resistor, and frequency output

transistor. It is important that the loop be physically small for

two reasons: first, there is less self-inductance if the wires are

short, and second, the loop will not radiate RFI efficiently.

The digital ground (Pin 10) should be separately connected to

the power supply ground. Note that the leads to the digital

power supply are only carrying dc current and cannot radiate

RFI. There may also be a dc ground drop due to the difference

in currents returned on the analog and digital grounds. This will

not cause any problem. In fact, the AD650 will tolerate as much

as 0.25 volt dc potential difference between the analog and digital

grounds. These features greatly ease power distribution and

ground management in large systems. Proper technique for

grounding requires separate digital and analog ground returns to

the power supply. Also, the signal ground must be referred

directly to analog ground (Pin 11) at the package. All of the sig-

nal grounds should be tied directly to Pin 11, especially the

one-shot capacitor. More information on proper grounding and

reduction of interference can be found in Reference 1.

TEMPERATURE COEFFICIENTS

The drift specifications of the AD650 do not include temperature

effects of any of the supporting resistors or capacitors. The drift

of the input resistors R1 and R3 and the timing capacitor C

directly affect the overall temperature stability. In the application

of Figure 2, a 10 ppm/°C input resistor used with a 100 ppm/°C

capacitor may result in a maximum overall circuit gain drift of:

150 ppm/°C (AD650A) + 100 ppm/°C (C

) + 10 ppm/°C (R

) 260 ppm/°C

In bipolar configuration, the drift of the 1.24 kΩ resistor used to

activate the internal bipolar offset current source will directly

affect the value of this current. This resistor should be matched

to the resistor connected to the op amp noninverting input (Pin

2), see Figure 4. That is, the temperature coefficients of these

two resistors should be equal. If this is the case, then the effects

of the temperature coefficients of the resistors cancel each other,

and the drift of the offset voltage developed at the op amp non-

inverting input will be determined solely by the AD650. Under

these conditions the TC of the bipolar offset voltage is typically

–200 ppm/°C and is a maximum of –300 ppm/°C. The offset

voltage always decreases in magnitude as temperature is increased.

Other circuit components do not directly influence the accuracy

of the VFC over temperature changes as long as their actual val-

ues are not so different from the nominal value as to preclude

operation. This includes the integration capacitor, C

INT

. A

change in the capacitance value of C

INT

simply results in a dif-

ferent rate of voltage change across the capacitor. During the

Integration Phase (refer to Figure 2), the rate of voltage change

across C

INT

has the opposite effect that it does during the Reset

Phase. The result is that the conversion accuracy is unchanged

“Noise Reduction Techniques in Electronic Systems,” by H. W. OTT,

(John Wiley, 1976).

AD650

REV. C

–8–

by either drift or tolerance of C

INT

. The net effect of a change in

the integrator capacitor is simply to change the peak to peak ampli-

tude of the sawtooth waveform at the output of the integrator.

The gain temperature coefficient of the AD650 is not a constant

value. Rather the gain TC is a function of both the full-scale

frequency and the ambient temperature. At a low full-scale

frequency, the gain TC is determined primarily by the stability

of the internal reference—a buried Zener reference. This low

speed gain TC can be quite good; at 10 kHz full scale, the gain

TC near 25°C is typically 0 ± 50 ppm/°C. Although the gain TC

changes with ambient temperature (tending to be more positive

at higher temperatures), the drift remains within a ±75 ppm/°C

window over the entire military temperature range. At full-scale

frequencies higher than 10 kHz dynamic errors become much

more important than the static drift of the dc reference. At a

full-scale frequency of 100 kHz and above, these timing errors

dominate the gain TC. For example, at 100 kHz full-scale

frequency (R

= 40 k and C

= 330 pF) the gain TC near

room temperature is typically –80 ± 50 ppm/°C, but at an ambi-

ent temperature near +125°C, the gain TC tends to be more

positive and is typically +15 ± 50 ppm/°C. This information is

presented in a graphical form in Figure 8. The gain TC always

tends to become more positive at higher temperatures. There-

fore, it is possible to adjust the gain TC of the AD650 by using

a one-shot capacitor with an appropriate TC to cancel the drift

of the circuit. For example, consider the 100 kHz full-scale

frequency. An average drift of –100 ppm/°C means that as

temperature is increased, the circuit will produce a lower fre-

quency in response to a given input voltage. This means that the

one-shot capacitor must decrease in value as temperature increases

in order to compensate the gain TC of the AD650; that is, the

capacitor must have a TC of –100 ppm/°C. Now consider the

1 MHz full-scale frequency.

Figure 8. Gain TC vs. Temperature

It is not possible to achieve very much improvement in perfor-

mance unless the expected ambient temperature range is known.

For example, in a constant low temperature application such as

gathering data in an Arctic climate (approximately –20°C), a

with a drift of –310 ppm/°C is called for in order to compen-

sate the gain drift of the AD650. However, if that circuit should

see an ambient temperature of +75°C, the C

cap would

change the gain TC from approximately 0 ppm to +310 ppm/°C.

The temperature effects of the components described above are

the same when the AD650 is configured for negative or bipolar

input voltages, and for F/V conversion as well.

NONLINEARITY SPECIFICATION

The linearity error of the AD650 is specified by the endpoint

method. That is, the error is expressed in terms of the deviation

from the ideal voltage to frequency transfer relation after cali-

brating the converter at full scale and “zero”. The nonlinearity

will vary with the choice of one-shot capacitor and input resistor

(see Figure 3). Verification of the linearity specification requires

the availability of a switchable voltage source (or a DAC) having

a linearity error below 20 ppm, and the use of very long mea-

surement intervals to minimize count uncertainties. Every AD650

is automatically tested for linearity, and it will not usually be

necessary to perform this verification, which is both tedious and

time consuming. If it is required to perform a nonlinearity test

either as part of an incoming quality screening or as a final prod-

uct evaluation, an automated “bench-top” tester would prove

useful. Such a system based on the Analog Devices’ LTS-2010

is described in Reference 2.

The voltage-to-frequency transfer relation is shown in Figure 9

with the nonlinearity exaggerated for clarity. The first step in

determining nonlinearity is to connect the endpoints of the

Figure 9a. Exaggerated Nonlinearity at 100 kHz Full Scale

Figure 9b. Exaggerated Nonlinearity at 1 MHz Full Scale

operating range (typically at 10 mV and 10 V) with a straight

line. This straight line is then the ideal relationship which is

desired from the circuit. The second step is to find the difference

between this line and the actual response of the circuit at a few

points between the endpoints—typically ten intermediate points

will suffice. The difference between the actual and the ideal

response is a frequency error measured in hertz. Finally, these

frequency errors are normalized to the full-scale frequency and

expressed either as parts per million of full scale (ppm) or parts

per hundred of full scale (%). For example, on a 100 kHz full

“V–F Converters Demand Accurate Linearity Testing,” by L. DeVito,

(Electronic Design, March 4, 1982).

AD650

REV. C –9–

scale, if the maximum frequency error is 5 Hz, the nonlinearity

would be specified as 50 ppm or 0.005%. Typically on the

100 kHz scale, the nonlinearity is positive and the maximum

value occurs at about midscale (Figure 9a). At higher full-scale fre-

quencies, (500 kHz to 1 MHz), the nonlinearity becomes “S”

shaped and the maximum value may be either positive or nega-

tive. Typically, on the 1 MHz scale (R

= 16.9k, C

= 51 pF)

the nonlinearity is positive below about 2/3 scale and is negative

above this point. This is shown graphically in Figure 9b.

PSRR

The power supply rejection ratio is a specification of the change

in gain of the AD650 as the power supply voltage is changed.

The PSRR is expressed in units of parts-per-million change of

the gain per percent change of the power supply—ppm/%. For

example, consider a VFC with a 10 volt input applied and an

output frequency of exactly 100 kHz when the power supply

potential is ±15 volts. Changing the power supply to ±12.5 volts

is a 5 volt change out of 30 volts, or 16.7%. If the output frequency

changes to 99.9 kHz, the gain has changed 0.1% or 1000 ppm.

The PSRR is 1000 ppm divided by 16.7% which equals 60 ppm/%.

The PSRR of the AD650 is a function of the full-scale operating

frequency. At low full-scale frequencies the PSRR is determined

by the stability of the reference circuits in the device and can be

very good. At higher frequencies there are dynamic errors which

become more important than the static reference signals, and

consequently the PSRR is not quite as good. The values of PSRR

are typically 0 ± 20 ppm/% at 10 kHz full-scale frequency (R

= 40 k, C

= 3300 pF). At 100 kHz (R

= 40k, C

= 330 pF)

the PSRR is typically +80 ± 40 ppm/%, and at 1 MHz (R

16.9 kΩ, C

= 51 pF) the PSRR is +350 ± 50 ppm/%. This

information is summarized graphically in Figure 10.

Figure 10. PSRR vs. Full-Scale Frequency

OTHER CIRCUIT CONSIDERATIONS

The input amplifier connected to Pins 1, 2 and 3 is not a standard

operational amplifier. Rather, the design has been optimized for

simplicity and high speed. The single largest difference between

this amplifier and a normal op amp is the lack of an integrator

(or level shift) stage. Consequently the voltage on the output

(Pin 1) must always be more positive than 2 volts below the

inputs (Pins 2 and 3). For example, in the F-to-V conversion

mode, see Figure 6, the noninverting input of the op amp (Pin 2) is

grounded, which means that the output (Pin 1) will not be able

to go below –2 volts. Normal operation of the circuit as shown

in the figure will never call for a negative voltage at the output

but one may imagine an arrangement calling for a bipolar out-

put voltage (say ±10 volts) by connecting an extra resistor from

Pin 3 to a positive voltage. This will not work.

Care should be taken under conditions where a high positive

input voltage exists at or before power up. These situations can

cause a latch up at the integrator output (Pin 1). This is a non-

destructive latch and, as such, normal operation can be restored

by cycling the power supply. Latch up can be prevented by

connecting two diodes (e.g., 1N914 or 1N4148) as shown in

Figure 4, thereby, preventing Pin 1 from swinging below Pin 2.

A second major difference is that the output will only sink 1 mA

to the negative supply. There is no pulldown stage at the output

other than the 1 mA current source used for the V-to-F conver-

sion. The op amp will source a great deal of current from the

positive supply, and it is internally protected by current limiting.

The output of the op amp may be driven to within 3 volts of the

positive supply when it is not sourcing external current. When

sourcing 10 mA the output voltage may be driven to within

6 volts of the positive supply.

A third difference between this op amp and a normal device is

that the inverting input, Pin 3, is bias current compensated and

the noninverting input is not bias current compensated. The

bias current at the inverting input is nominally zero, but may be

as much as 20 nA in either direction. The noninverting input

typically has a bias current of 40 nA that always flows into the

node (an npn input transistor). Therefore, it is not possible to

match input voltage drops due to bias currents by matching

input resistors.

The op amp has provisions for trimming the input offset volt-

age. A potentiometer of 20 kΩ is connected to Pins 13 and 14

and the wiper is connected to the positive supply through a

250 kΩ resistor. A potential of about 0.6 volt is established

across the 250 kΩ resistor, and the 3 µA current is injected into

the null pins. It is also possible to null the op amp offset voltage

by using only one of the null pins and use a bipolar current

either into or out of the null pin. The amount of current required

will be very small—typically less than 3 µA. This technique is

shown in the applications section of this data sheet: the autozero

circuit uses this technique.

The bipolar offset current is activated by connecting a 1.24 kΩ

resistor between Pin 4 and the negative supply. The resultant

current delivered to the op amp noninverting input is nominally

0.5 mA and has a tolerance of ±10%. This current is then used

to provide an offset voltage when Pin 2 is tied to ground through a

resistor. The 0.5 mA which appears at Pin 2 is also flowing through

the 1.24 kΩ resistor and this current may be by observing the

voltage across the 1.24 kΩ resistor. An external resistor is used

to activate the bipolar offset current source to provide the lowest

tolerance and temperature drift of the resultant offset voltage. It

is possible to use other values of resistance between Pin 4 and –V

to obtain a bipolar offset current different than 0.5 mA. Fig-

ure 11 is a graph of the relationship between the bipolar offset

current and the value of the resistor used to activate the source.

AD650

REV. C

–10–

Figure 11. Bipolar Offset Current vs. External Resistor

APPLICATIONS

DIFFERENTIAL VOLTAGE-TO-FREQUENCY

CONVERSION

The circuit of Figure 12 accepts a true floating differential input

signal. The common-mode input, V

, may be in the range

+15 to –5 volts with respect to analog ground. The signal input,

, may be ±5 volts with respect to the common-mode input.

Both inputs are low impedance: the source which drives the

common-mode input must supply the 0.5 mA drawn by the

bipolar offset current source and the source which drives the

signal input must supply the integration current.

If less common-mode voltage range is required, a lower voltage

Zener may be used. For example, if a 5 volt Zener is used, the

input may be in the range +10 to –5 volt. If the Zener is

not used at all, the common-mode range will be ±5 volts with

respect to analog ground. If no Zener is used, the 10k pulldown

resistor is not needed and the integrator output (Pin 1) is con-

nected directly to the comparator input (Pin 9).

Figure 12. Differential Input

AUTOZERO CIRCUIT

In order to exploit the full dynamic range of the AD650 VFC,

very small input voltages will need to be converted. For example,

a six decade dynamic range based on a full scale of 10 volts will

require accurate measurement of signals down to 10 µV. In these

situations a well-controlled input offset voltage is imperative. A

constant offset voltage will not affect dynamic range but simply

shift all of the frequency readings by a few hertz. However, if the

offset should change, then it will not be possible to distinguish

between a small change in a small input voltage and a drift of

the offset voltage. Hence, the usable dynamic range is less. The

circuit shown in Figure 13 provides automatic adjustment of the

op amp offset voltage. The circuit uses an AD582 sample and

hold amplifier to control the offset and the input voltage to the

VFC is switched between ground and the signal to be measured

via an AD7512DI analog switch. The offset of the AD650 is

adjusted by injecting a current into or drawing a current out of

Pin 13. Note that only one of the offset null pins is used. During

the “VFC Norm” mode, the SHA is in the hold mode and the

hold capacitor is very large, 0.1 µF, to hold the AD650 offset

constant for a long period of time.

Figure 13. Autozero Circuit

When the circuit is in the “Autozero” mode the SHA is in

sample mode and behaves like an op amp. The circuit is a varia-

tion of the classical two amplifier servo loop, where the output

of the Device Under Test (DUT)—here the DUT is the AD650

op amp—is forced to ground by the feedback action of the con-

trol amplifier—the SHA. Since the input of the VFC circuit is

connected to ground during the autozero mode, the input cur-

rent which can flow is determined by the offset voltage of the

AD650 op amp. Since the output of the integrator stage is

forced to ground it is known that the voltage is not changing (it

is equal to ground potential). Hence if the output of the integra-

tor is constant, its input current must be zero, so the offset voltage

has been forced to be zero. Note that the output of the DUT

could have been forced to any convenient voltage other than

ground. All that is required is that the output voltage be known

to be constant. Note also that the effect of the bias current at

the inverting input of the AD650 op amp is also nulled in this

circuit. The 1000 pF capacitor shunting the 200 kΩ resistor

is compensation for the two amplifier servo loop. Two integra-

tors in a loop requires a single zero for compensation. Note that

the 3.6 kΩ resistor from Pin 1 of the AD650 to the negative sup-

ply is not part of the autozero circuit, but rather it is required for

VFC operation at 1 MHz.

PHASE LOCKED LOOP F/V CONVERSION

Although the F/V conversion technique shown in Figure 6 is quite

accurate and uses only a few extra components, it is very limited

in terms of signal frequency response and carrier feed-through.

If the carrier (or input) frequency changes instantaneously, the

AD650

REV. C –11–

output cannot change very rapidly due to the integrator time

constant formed by C

INT

and R

. While it is possible to decrease

the integrator time constant to provide faster settling of the

F-to-V output voltage, the carrier feedthrough will then be

larger. For signal frequency response in excess of 2 kHz, a phase

locked F/V conversion technique such as the one shown in Fig-

ure 14 is recommended.

Figure 14. Phase Locked Loop F/V Conversion

In a phase locked loop circuit, the oscillator is driven to a frequency

and phase equal to an input reference signal. In applications

such as a synthesizer, the oscillator output frequency is first pro-

cessed through a programmable “divide by N” before being

applied to the phase detector as feedback. Here the oscillator

frequency is forced to be equal to “N times” the reference fre-

quency and it is this frequency output which is the desired

output signal and not a voltage. In this case, the AD650 offers

compact size and wide dynamic range.

In signal recovery applications of a PLL, the desired output sig-

nal is the voltage applied to the oscillator. In these situations a

linear relationship between the input frequency and the output

voltage is desired; the AD650 makes a superb oscillator for FM

demodulation. The wide dynamic range and outstanding linearity

of the AD650 VFC allow simple embodiment of high perfor-

mance analog signal isolation or telemetry systems. The circuit

shown in Figure 14 uses a digital phase detector which also pro-

vides proper feedback in the event of unequal frequencies. Such

phase-frequency detectors (PFDs) are available in integrated

form. For a full discussion of phase lock loop circuits see

Reference 3.

An analysis of this circuit must begin at the 7474 dual D flip

flop. When the input carrier matches the output carrier in both

phase and frequency, the Q outputs of the flip flops will rise at

exactly the same time. With two zeros, then two ones on the

inputs of the exclusive or (XOR) gate, the output will remain

low keeping the DMOS FET switched off. Also, the NAND

gate will go low resetting the flip-flops to zero. Throughout the

entire cycle just described, the DMOS integrator gate remained

off, allowing the voltage at the integrator output to remain

unchanged from the previous cycle. However, if the input carrier

leads the output carrier by a few degrees, the XOR gate will be

turned on for the small time span that the two signals are mis-

matched. Since Q

will be low during the mismatch time, a

negative current will be fed into the integrator, causing its out-

put voltage to rise. This in turn will increase the frequency of

the AD650 slightly, driving the system towards synchronization.

In a similar manner, if the input carrier lags the output carrier,

the integrator will be forced down slightly to synchronize the

two signals.

Using a mathematical approach, the ±25 µA pulses from the

phase detector are incorporated into the phase detector gain, K

Using a mathematical approach, the ±25 µA pulses from the

phase detector are incorporated into the phase detector gain, K

=25 µA

2π=4×10

–6

amperes/radian

(9)

Also, the V/F converter is configured to produce 1 MHz in

response to a 10 volt input, so its gain K

, is:

o=2π×1×106Hz

10 V=6.3 ×105radians

volt • sec

(10)

The dynamics of the phase relationship between the input and

output signals can be characterized as a second order system

with natural frequency ω

(11)

and damping factor

ζ=RCK

(12)

For the values shown in Figure 14, these relations simplify to a

natural frequency of 35 kHz with a damping factor of 0.8.

For those desiring a simple approach to determining component

values for other PLL frequencies and VFC full-scale voltage, the

following cookbook steps can be used:

1. Determine K

(in units of radians per volt second) from the

maximum input carrier frequency F

MAX

(in hertz) and the

maximum output voltage V

MAX

Ko=2π×FMAX

VMAX

(13)

2. Calculate a value for C based upon the desired loop band-

width, f

. Note that this is the desired frequency range of the

output signal. The loop bandwidth (f

) is not the maximum

carrier frequency (f

MAX

): the signal may be very narrow even

though it is transmitted over a 1 MHz carrier.

C=Ko

•1×10–7 V•F

Rad • sec

C units FARADS

units HERTZ (14)

units RAD/VOLT•SEC

3. Calculate R to yield a damping factor of approximately 0.8

using this equation:

R=fn

•2.5×106Rad •Ω

R units OHMS

units HERTZ (15)

units RAD/VOLT•SEC

If in actual operation the PLL overshoots or hunts excessively

before reaching a final value, the damping factor may be raised

by increasing the value of R. Conversely, if the PLL is over-

damped, a smaller value of R should be used.

“Phase lock Techniques,” 2nd Edition, by F.M. Gardner, (John Wiley and

Sons, 1979)

AD650

REV. C

–12–

C00797–0–7/00 (rev. C)

PRINTED IN U.S.A.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead Ceramic DIP

(D-14)

0.098 (2.49) MAX

0.310 (7.87)

0.220 (5.59)

0.005 (0.13) MIN

PIN 1

0.100

(2.54)

BSC

SEATING

PLANE

0.023 (0.58)

0.014 (0.36)

0.060 (1.52)

0.015 (0.38)

0.200 (5.08)

MAX

0.200 (5.08)

0.125 (3.18)

0.070 (1.78)

0.030 (0.76)

0.150

(3.81)

MAX

0.785 (19.94) MAX

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

14-Lead Plastic DIP

(N-14)

PIN 1

0.795 (20.19)

0.725 (18.42)

0.280 (7.11)

0.240 (6.10)

0.100 (2.54)

BSC

SEATING

PLANE

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)

MAX

0.022 (0.558)

0.014 (0.356)

0.160 (4.06)

0.115 (2.93)

0.070 (1.77)

0.045 (1.15)

0.130

(3.30)

MIN

0.195 (4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.325 (8.25)

0.300 (7.62)

20-Lead PLCC

(P-20A)

PIN 1

IDENTIFIER

8914

TOP VIEW

(PINS DOWN)

0.395 (10.02)

0.385 (9.78) SQ

0.356 (9.04)

0.350 (8.89)SQ

0.048 (1.21)

0.042 (1.07)

0.048 (1.21)

0.042 (1.07)

0.020

(0.50)

0.050

(1.27)

BSC

0.021 (0.53)

0.013 (0.33) 0.330 (8.38)

0.290 (7.37)

0.032 (0.81)

0.026 (0.66)

0.180 (4.57)

0.165 (4.19)

0.040 (1.01)

0.025 (0.64)

0.056 (1.42)

0.042 (1.07) 0.025 (0.63)

0.015 (0.38)

0.110 (2.79)

0.085 (2.16)