GEC PLESSEY 2 ' ? SEMICONDUCTORS COMPONENTS The MV6QOI is a remote control receiver designed to > operate in Conjunction with the MV500 transmitter. A five dit Wistate binary output corresponding to the 32 codes available from the MVS5Q0 is provided together with data ready and output enable signals, allowing a simple interface to a microprocessor. A ceramic resonator and two rate inputs set the data rate to correspond to that produced by the MVS500. FEATURES High Noise Immunity 5V Operation Very Low Supply Current Momentary or Latched Operation Tri-State Outputs Ceramic Resonator and Data Rate Inputs to match MV500 .APPLICATIONS MI Remote Control Interface to Microprocessor Hf industrial and Consumer Remote Control xd MV601 REMOTE CONTROL RECEIVER 2182-10 QS PPM input ( 1 16 "| Voo POWER CLEAR q 2 16 (] OUTPUT E nate input al} 1a [] ouTPUT O Rate INPUT AU} a ayy 13[] OUTPUT C MOMENTAAY/LATCHED [| 5 601 12/] ouTPUTa OSCILLATOR INU 6 11 U0 output a oscittaTor out (7 10 [] DATA READY Vss U8 9 {] OUTPUT ENABLE DP16 PPMINPUTCII 1 16 CT Vo POWER CLEAR CL [T") OUTPUT E RATE INPUT 8 CO Er outeut o AATEINPUT ACI! MY [ry outputc MOMENTARY/LATCHEO Cr] 601 [Fr outputs OSCILLATOA IN CIC] [= guTPuT a OSCILLATOR OUTCI II] GATA READY VesCE4{3 9 FE) OUTPUT ENABLE MP16 Fig 1 Pin connections - top view 13 BIT SHIFT REGISTER 1 PPM INPUT O c~* DATA READY | A ( we 0 I l } u 4 T RATE INPUT A oT 0 BIT COUNTER WORD STORE WwORO oP 1 I pm U | R A E G TIMING PULSE CURRENT WORD |_| 1 }_] GENERATOR 4 REGISTER 2 L 1 ! E Af =~ y R aA 6 ~< OSC IN? > 7 OSCILLATOR | Osc OUT OF 16 BIT COUNTER WORD a NOISE A SUPPLY O Van COUNTER OETECTOR 8 QV > Vss5 U ait- 4 . | 5. MOMENTARY/ LATCHED 3-6 ee, o . - Fig.2. MV601 block diagram g ee HO OUTPUT ENASLE 15 }o OUTPUT E 14 o OUTPUT D 13 0 output c 12 Ho OUTPUT B 1 -S OUTPUT A ~2o BOWER CLEARELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated) Tamy = 0C to 70C, Von = *+45V to +5 5V MV601 Characteristic Pin Value Units Conditions Min Typ Max Power supply current, | Onillator frequency i 16 0.2 2.0 mA INPUTS 6,7 10 MHz . OSCIN, RATE A, RATE B. 6. 4, 3. MOM / LAT, OEN 5.9 Inout low voltage (Vir) Voo: 3 Input high voitage (Vip) x3, PPM, POWER CLEAR 1,2 input low voltage (Vi,) 1.0 Vv Voo = 5.0V Input high voltage (Vin) 2.0 v : Threshold voltage rising 1.85 Vv Threshold voltage falling 1.05 Vv POWER CLEAR, RATE A, RATE B] 2, 4,3 Input low current -33 -100 BA Nom. 150k pullup resistor A ofmer iapets except OSCIN 1.5.9 +25 | pA | Vy = Veg -0.3V to Vo +0.3V OSCIN . 6 . : Input current #10 | ua | Vm = Vsg-0.3V to Vpp +0.3V OUTPUTS , A-, DATA READY Output low current (sink) 13 mA Vor = 0.4V Output high current (source) -21 -45 mA Vou = 2.4V Output leakage current (A-E) +10 BA ao 3 So t0 Vop + 0.3V OSCOUT Cutput low voltage (sink) 1.0 mA Vig = 0.3V Output high current (source) -1.0 mA Vou = Voo 0.3V OPERATING NOTES The MV601 is designed to operate in conjunction with the MV500 transmitter. When the rate inputs of MVS00 and MV601 are pragrammed with the same binary input code and matched ceramic resonator frequencies are used (within 4%), the outputs of the MV6Q1 will be set to the value of the PPM code transmitted. Two identical valid words must be received before an output response. A data ready signal, set after the output data has settled may be used to strobe data into an external register or generate an interrupt to a microprocessor. When used in inffd red systems, the PPM input will usually be derived fram the output of an SL486 infra red amplifier, but direct connection ta the transmitter is also possible. The PPM input is insensitive to pulse width. The power clear input is generally connected ta an external capacitor which nolds the input momentarily low ensuring a reset of the outputs and internal logic at power on. The circuit can be reset at any time by taking the power clear input low. we. The rate inputs nave nominal 150kQ pull up resistors and may therefore be left open circuit when a high input is required. * When mere than 32 codes are required, the rate inputs on the MVS5CO transmitter can be switched and 2 or 3 MV601 circuits wired,in parallel to the PPM signal. Only the MV601 with rate inputs identical to the transmitter will respond. An alternative method giving 64 possible codes from only one MV601 is shown in Fig. 7. The fastest and slowest rate settings fram the transmitter should be used. in this circuit the three transistors produce a OC level dependent on the rate of the received PPM data. The DC level is used to provide the F output dit and to automatically switch the rate B input to the MV6Q1 to correspond with the transmitter. 5-7/601 IN FUNCTIONS i Oscillator Out Pies ortpul OF tee cose diator Cacul A Capacitor PPM Input connected to gruunel campletes the Perce The senal PPM data is connected here Pulse oscillator cucurl width ts not critical but must remain high kor low for at least one clock cycle. 8. Vss The negative sucoly gin Power Clear A logic low resets the output register and internal 9. Output Enable logic ensuring full noise immunity from switch on. A logic low enacies the A, 8B, C, D and E outputs. A capacitor to Vgg will normally be connected. A A logic high switches the output transistors off, 150k (nom) resistor to Voo is provided so that the providing a high impedance state. input may be leR open circu if required. 10. Data Ready Rate Input B . Set low when vahd data is present at the outputs. This input controls the received data rate according to table 1. Input state must match that 11. Output A on MV500. A 150k (nom) resistor pull up to Vag is Tri-state output set to the binary equivalent of the provided so that the input may be left open circuit PPM input date. if required. 12. Output B Rate Input A As pin 11. As pin 3. 13. Output C Momentary/Latched Input . AS pin 11. Controls the operational mode of the output register. When low, data will be retained at the 14. Output D output until updated by a newly validated code. As pin tt. When high, the data will only remain at the outputs whilst the valid code is present at the 15. Output E PPM input. As pin 11. }. Oscillator in 16. Voo The input to the oscillator circuit. A Pierce The positive sucply pin. oscillator is formed by a ceramic resonator connected to pin 7 and capacitor connected ta ground, ts q tg ts $a ~_-_ By NCL E bp c 8 A os BIT A Fig.3 Typical Received PPM Data Rate inputs Clock cycles B A ty to ts ABSOLUTE MAXIMUM RATINGS 0 0 NV NV NV Supply Voltage Voo +7V 0 1 4096 6144 12288 Input Voltage Voo *0.3V to Vsg-0.3V ' 0 2048 3072 6144 Operating Temperature 0C to +70C , 1024 1536 3072 Storage Temperature 55C to + 125C Output Sink and Source Current SOmA Table 1 Rate control inpuls Hurnidity 85% NV = Not Valid NOTE: Rate inputs snouid match those on MVS00 3-8he MV601 DATA WORD INITIAL SYNC BIT FINAL SYNC BIT A x | 1 2 3 4 n ned OUTPUT RESPONSE >| |e oetay-sync Time DATA READY I t~t- DELAY = 2 CLOCKS Timing diagram momentary mode FINAL SYNC BIT INITIAL SYNC BIT (CODE 1) INITIAL SYNC BIT (CODE 2) 2NO CODE LATCHED trie) fetal] Olle lie TO FIAST CO ~______-__- 1ST CODE LATCHEO>] + 2ND CODE | OUTPUT RESPONSE | OUTPUT RESPONSE | TO SECOND CODE LATCHED | reer SYNC TIME | DATA READY > DELAY =2 CLOCKS DELAY =2 cLocks>| |< Timing diagram latched mode Fig.4 Output timing vO PORT INTERRUPT MICROPROCESSOR X1=MURATA CS8S500E CERAMIC RESONATOR Fig.5 Interface to microprocessor and SL486 (latched mode) 5-9MV601 * ; ] * r $V acy || | RLY RLY ALY RLY 1 | 3 4 5 i 1 an :; A A 4 PPM input N\A 46 }- 4 Ly | L_f FROM SL486 tk +{]2 1s{}/-+{__} MV601 1 TTT IT] 4.7% O.1po= (| Al 100p | 100p a e * av 5X ZTX300 X1 = MURATA CS8500E CERAMIC RESONATOR Fig.6 General purpose 5-tunction industnal remote control application (momentary mode) 7 +5V NA 1M - 4 wat 50 BP ak tok} f1x| | o'4oF XY fH c ' 8 1Sh 4 2 15 -|}_{}: eA | Us ~ i s[k4 - F | 68 Cl a {}2 1s[}-+> E St 43 1a[--+ 0 [yd Se a fs zn P4Es xP TR2 4s wy aise cam 7 S {|7 10 fh >_ | 47x ) ny -{]s 801 12{}--> 8 a 9 TRI TR r qs 11 [7 A 150n 4.70 . oe = 47k * 4.7% ${]q 9 DATA READY == }22z ie ==100p ok to, 5 | i ov TA1,2,3 2N3904 OR SIMILAR, X1 = MURATA CS8500E CERAMIC RESONATOA Fig.7 64-code application using a single MVEQ! 5-10FROM UK. TECHNICAL . PACKAGE OUTLINE DIMENSIONS (continued) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTAGLUNG DIMENSION: INCH, [-B-| 3. OIM LTO CENTER OF LEAO WHEN FORMED PARALLEL a ae | | c __ y F 0.010 | 0.014 amet fk 3 PLANE G t i rlheJ sat E spt . w [S]0.13 0.005) @ [tT] B] a@| D set (1 0.13 (0.005) @ [tT] A@| B@] STYLE I: STYLE 3: . STYLE 5: STYLE 6: STYLE 8: PIN 1. ANOOE PIN 1. ANODE PIN 1. ANOOE PIN 1, ANOOE PIN 1. LED 1 ANOQE/LED 2 CATHODE 2. CATHOOE 2. CATHOOE 2. CATHOOE 2, CATHODE 2, LED 1 CATHODEILED 2 ANODE 3. NC 3. NC 3. NC 3 NC 3. NC 4, EMITTER 4. EMITTER 4, OUTPUT 4, MAIN TERMINAL 4. EMITTER 5. COLLECTOR . COLLECTOR 5. GROUND 5. SUBSTAATE . COLLECTOR 6. BASE &. NC & Voc 6. MAIN TERMINAL 6. BASE ' . CASE 730A-04 Ss , -A- 6 4 _ NOTES: { -B- | 1. DIMENSIONING ANO TOLERANCING PER ANSI Y14.5M, 1982. O1 3 L 2. CONTROLLING DIMENSION: INCH. F spl 4 | ro oS - 4 7 PLANE E 6pu D srt [4 0.13 (0.005) @ [T] B | a@} [B+ 0.13 (0.005) @ |T] A@| B| . STYLE 1: STYLE 3: STYLE 5: STYLE 6: STYLE &: PINS, ANCOE PINT. ANOOE PINT. ANCOE PINT. ANOQOE PIN 1. LED 1 ANOOE/LED 2 CATHOOE 2 CATHODE 2 CATHOOE 2, CATHOOE 2. CATHODE 2. LED 1 CATHCOE/LEO 2 ANODE 3, NC . 3. NC 4. NG 2 NC 3. NC 4, EMITTER me 4, EMITTER 4. OUTPUT 4. MAIN TERMINAL 4. EMITTER 5. COLLECTOR 5. COLLECTOR . GROUND . SUBSTRATE 5. COLLECTOR 8. BASE 8. NC & Voc 8. MAIN TERMINAL 8. BASE CASE 730C-04 Sv SUPRix.