MM0-672061FV-15 - Atmel Corporation

M672061F

Rev. D – June 5, 2000 1

Description

The M672061F implements a first-in first-out algorithm,

featuring asynchronous read/write operations. The FULL

and EMPTY flags prevent data overflow and underflow.

The Expansion logic allows unlimited expansion in word

size and depth with no timing penalties. Twin address

pointers automatically generate internal read and write

addresses, and no external address information are

required for the TEMIC FIFOs. Address pointers are

automatically incremented with the write pin and read

pin. The 9 bits wide data are used in data communications

applications where a parity bit for error checking is

necessary. The Retransmit pin reset the Read pointer to

zero without affecting the write pointer. This is very

useful for retransmitting data when an error is detected in

the system.

Using an array of eight transistors (8 T) memory cell, the

M672061F combine an extremely low standby supply

current (typ = 0.1 µA) with a fast access time at 15 ns

over the full temperature range. All versions offer battery

backup data retention capability with a typical power

consumption at less than 2 µW.

For military/space applications that demand superior

levels of performance and reliability the M672061F is

processed according to the methods of the latest revision

of the MIL STD 883 (class B or S) ,ESA SCC 9000 or

QML.

Features

DFirst-in first-out dual port memory

D16384 × 9 organisation

DFast Flag and access times: 15, 30 ns

DWide temperature range : – 55 °C to + 125 °C

DProgrammable Half Full Flag

DFully expandable by word width or depth

DAsynchronous read/write operations

DEmpty, full and half flags in single device mode

DRetransmit capability

DBi-directional applications

DBattery back-up operation : 2 V data retention

DTTL compatible

DSingle 5 V ± 10 % power supply

DHigh Performance SCMOS Technology

16 K  9 CMOS With Programmable Half Full Flag Parallel

FIFO Rad Tolerant

M672061F

Rev. D – June 5, 2000

Interface

Block Diagram

16384

16384 x 9

Pin Configuration

GND

VCC

FL/RT

XO/PHF

FP 28 pin 400 mils

DIL ceramic 28 pin 300 mils

(top view)

M672061F

Rev. D – June 5, 2000 3

Pin Names

NAMES DESCRIPTION

I0–8 Inputs

Q0–8 Outputs

WWrite Enable

RRead Enable

RS Reset

EF Empty Flag

NAMES DESCRIPTION

FF Full Flag

XO/PHF Expansion Out/Programmable Half-

Full Flag

XI Expansion IN

FL/RT First Load/Retransmit

VCC Power Supply

GND Ground

Signal Description

Data In (I0 - I8)

Data inputs for 9 - bit data

Reset (RS)

Reset occurs whenever the Reset (RS) input is taken to a

low state. Reset returns both internal read and write

pointers to the first location. A reset is required after

power-up before a write operation can be enabled. Both

the Read Enable (R) and W rite Enable (W) inputs must be

in the high state during the period shown in figure 1 (i.e.

tRSS before the rising edge of RS) and should not change

until tRSR after the rising edge of RS. Otherwise, pulse

write (or read) low during the reset operation has to effect

to load the Programmable Half Full Flag register grow the

data Inputs I0-I8 (or data outputs Q0-Q8) (shown in figure

2). In these two cases the Full Flag and the Programmable

Half Full Flag are reseted to high and the Empty Flag to

low.

M672061F

Rev. D – June 5, 20004

Figure 1. Reset (no write to Programmable Half Full Flag register)

tWR

(tRR)

Notes : 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC.

2. W and R = VIH around the rising edge of RS.

Figure 2. Reset (write (read) to Programmable Half Full Flag r egister)

DATA VALID

tWR

(tRR)

tWPW

(tRPW)

tWC

(tRC) tRSR

tDS tDH

(R)

I0–I8

(Q0–Q8)

Write Enable (W)

A write cycle is initiated on the falling edge of this input

if the Full Flag (FF) is not set. Data set-up and hold times

must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the

Ram array, regardless of any current read operation.

Once half the memory is filled, and during the falling

edge of the next write operation, the Programmable

Half-Full Flag (PHF) will be set to low and remain in this

state until the difference between the write and read

pointers is less than or equal to half of the total available

memory in the device. The Programmable Half-Full Flag

(PHF) is then reset by the rising edge of the read

operation.

To prevent data overflow, the Full Flag (FF) will go low,

inhibiting further write operations. On completion of a

valid read operation, the Full Flag (FF) will go high after

TRFF, allowing a valid write to begin. When the FIFO

stack is full, the internal write pointer is blocked from W,

so that external changes to W will have no effect on the

full FIFO stack.

Read Enable (R)

A read cycle is initiated on the falling edge of the Read

Enable (R) provided that the Empty Flag (EF) is not set.

The data is accessed on a first in/first out basis, not with

standing any current write operations. After Read Enable

(R) goes high, the Data Outputs (Q0 - Q8) will return to

a high impedance state until the next Read operation.

When all the data in the FIFO stack has been read, the

Empty Flag (EF) will go low, allowing the “final” read

cycle, but inhibiting further read operations whilst the

data outputs remain in a high impedance state. Once a

valid write operation has been completed, the Empty Flag

(EF) will go high after tWEF and a valid read may then

be initiated. When the FIFO stack is empty, the internal

read pointer is blocked from R, so that external changes

to R will have no effect on the empty FIFO stack.

First Load/Retransmit (FL/RT)

This is a dual-purpose input. In the Depth Expansion

Mode, this pin is connected to ground to indicate that it

M672061F

Rev. D – June 5, 2000 5

is the first loaded (see Operating Modes). In the Single

Device Mode, this pin acts as the retransmit input. The

Single Device Mode is initiated by connecting the

Expansion In (XI) to ground.

The M672061F can be made to retransmit data when the

Retransmit Enable Control (RT) input is pulsed low. A

retransmit operation will set the internal read point to the

first location and will not affect the write pointer. Read

Enable (R) and W rite Enable (W) must be in the high state

during retransmit. The retransmit feature is intended for

use when a number of writes equals to or less than the

depth of the FIFO has occured since the last RS cycle. The

retransmit feature is not compatible with the Depth

Expansion Mode and will affect the Programmable

Half-Full Flag (PHF), in accordance with the relative

locations of the read and write pointers.

Expansion In (XI)

This input is a dual-purpose pin. Expansion In (XI) is

connected to GND to indicate an operation in the single

device mode. Expansion In (XI) is connected to

Expansion Out (XO) of the previous device in the Depth

Expansion or Daisy Chain modes.

Full Flag (FF)

The Full Flag (FF) will go low, inhibiting further write

operations when the write pointer is one location less than

the read pointer, indicating that the device is full. If the

read pointer is not moved after Reset (RS), the Full Flag

(FF) will go low after 16384 writes.

Empty Flag (EF)

The Empty Flag (EF) will go low, inhibiting further read

operations when the read pointer is equal to the write

pointer, indicating that the device is empty.

Expansion Out/Half-Full Flag (XO/HF)

This is a dual-purpose output. In the single device mode,

when Expansion In (XI) is connected to ground, this

output acts as an indication of a half-full memory.

The M672061F offers a variable offset for the Half Full

condition. The offset is loaded into a register during a

reset cycle . When RS is low, the Programmable Half Full

Flag (PHF) can be loaded from the DATA inputs I0-I8 by

pulsing W low or from the DATA outputs Q0–Q8 by

pulsing R low. The offset options are listed in table 1. If

PHF is not loaded during the reset cycle, the default offset

will be the half of the total memory of the device.

The Programmable Half-Full Flag (PHF) will be set to

low and will remain set until the difference between the

write and read pointers is less than or equal to the

Programmable offset (if the Half Full Flag register has

been loaded during the reset cycle) or the half of the total

memory (if the Half Full register has not been loaded

during the reset cycle).

In the Depth Expansion Mode, Expansion In (XI) is

connected to Expansion Out (XO) of the previous device.

This output acts as a signal to the next device in the Daisy

Chain by providing a pulse to the next device when the

previous device reaches the last memory location.

Data Output (Q0 - Q8)

DATA output for 9-bit wide data. This data is in a high

impedance condition whenever Read (R) is in a high state.

M672061F

Rev. D – June 5, 20006

Functional Description

Operating Modes

Single Device Mode

A single M672061E may be used when the application

requirements are for 16384 words or less. The M672061E

is in a Single Device Configuration when the Expansion In

(XI) control input is grounded (see Figure 3). In this mode

the Programmable Half-Full Flag (PHF), which is an

active low output, is shared with Expansion Out (XO).

Figure 3. Block Diagram of Single 16384 × 9.

(HALF–FULL FLAG)

WRITE (W)(R) READ

DATAIN

(I) DATAOUT

(Q)

FULL FLAG

RESET

(FF)

(RS)

EMPTY FLAG

RETRANSMIT

(EF)

(RT)

EXPANSION IN (XI)

PHF

672061F

Width Expansion Mode

Word width may be increased simply by connecting the

corresponding input control signals of multiple devices.

Status flags (EF, FF and PHF) can be detected from any

device. Figure 4 demonstrates an 18-bit word width by

using two M672061E. Any word width can be attained by

adding additional M672061F.

Figure 4. Block Diagram of 16384 × 18 FIFO Memory Used in Width Expansion Mode.

672061F

(W)WRITE

(FF)

FULL FLAG

RESET

(R) READ

(EF) EMPTY FLAG

(RT) RETRANSMIT

PHF

(RS) 9

DATAIN (I)

9PHF

(Q) DATAOUT

Note : 3. Flag detection is accomplished by monitoring the FF, EF and the PHF signals on either (any) device used in the width

expansion configuration. Do not connect any output control signals together.

M672061F

Rev. D – June 5, 2000 7

Table 1 : Programmable Half Full Flag Offset

I8I7I6I5I4I3I2I1I0OFFSET

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 32

0 0 0 0 0 0 0 1 0 64

...

1 0 0 0 0 0 0 0 0 8192 (Half Full)

Default Offset

...

1 1 1 1 1 1 1 1 0 16384-64

1 1 1 1 1 1 1 1 1 16384-32

Table 2 : Reset and retransmit

Single Device Configuration/Width Expansion Mode

INPUTS INTERNAL STATUS OUTPUTS

MODE RS RT XI Read Pointer Write Pointer EF FF PHF

Reset 0 X 0 Location Zero Location Zero 0 1 1

Retransmit 1 0 0 Location Zero Unchanged X X X

Read/Write 1 1 0 Increment(4) Increment(4) X X X

Note : 4. Pointer will increment if flag is high.

Table 3 : Reset and First Load Truth Table

Depth Expansion/Compound Expansion Mode

INPUTS INTERNAL STATUS OUTPUTS

MODE RS FL XI Read Pointer Write Pointer EF FF

Reset First Device 0 0 (5) Location Zero Location Zero 0 1

Reset All Other Devices 0 1 (5) Location Zero Location Zero 0 1

Read/Write 1 X (5) X X X X

Note : 5. XI is connected to XO of previous device.

See fig. 5.

Depth Expansion (Daisy Chain) Mode

The M672061F can be easily adapted for applications

which require more than 16384 words. Figure 5

demonstrates Depth Expansion using three M672061F.

Any depth can be achieved by adding additional 672061F .

The M672061F operates in the Depth Expansion

configuration if the following conditions are met :

1. The first device must be designated by connecting the

First Load (FL) control input to ground.

2. All other devices must have FL in the high state.

3. The Expansion Out (XO) pin of each device must be

connected to the Expansion In (XI) pin of the next

device. See figure 5.

4. External logic is needed to generate a composite Full

Flag (FF) and Empty Flag (EF). This requires that all

EF’s and all FFs be ØRed (i.e. all must be set to

generate the correct composite FF or EF). See figure 5.

M672061F

Rev. D – June 5, 20008

5. The Retransmit (RT) function and Programmable

Half-Full Flag (PHF) are not available in the Depth

Expansion Mode.

Compound Expansion Module

It is quite simple to apply the two expansion techniques

described above together to create large FIFO arrays (see

figure 6).

Bidirectional Mode

Applications which require data buffering between two

systems (each system being capable of Read and Write

operations) can be created by coupling M672061E as

shown in figure 7. Care must be taken to ensure that the

appropriate flag is monitored by each system (i.e. FF is

monitored on the device on which W is in use ; EF is

monitored on the device on which R is in use). Both Depth

Expansion and Width Expansion may be used in this

mode.

Data Flow – Through Modes

Two types of flow-through modes are permitted : a read

flow-through and a write flow-through mode. In the read

flow-through mode (figure 18) the FIFO stack allows a

single word to be read after one word has been written to

an empty FIFO stack. The data is enabled on the bus at

(tWEF + tA) ns after the leading edge of W which is

known as the first write edge and remains on the bus until

the R line is raised from low to high, after which the bus

will go into a three-state mode after tRHZ ns. The EF line

will show a pulse indicating temporary reset and then will

be set. In the interval in which R is low, more words may

be written to the FIFO stack (the subsequent writes after

the first write edge will reset the Empty Flag) ; however,

the same word (written on the first write edge) presented

to the output bus as the read pointer will not be

incremented if R is low. On toggling R, the remaining

words written to the FIFO will appear on the output bus

in accordance with the read cycle timings.

In the write flow-through mode (figure 19), the FIFO

stack allows a single word of data to be written

immediately after a single word of data has been read

from a full FIFO stack. The R line causes the FF to be

reset, but the W line, being low, causes it to be set again

in anticipation of a new data word. The new word is

loaded into the FIFO stack on the leading edge of W. The

W line must be toggled when FF is not set in order to write

new data into the FIFO stack and to increment the write

pointer.

M672061F

Rev. D – June 5, 2000 9

Figure 5. Block Diagram of 49152 × 9 FIFO Memory (Depth expansion).

69FF

FULL

EMPTY

VCC

672061F

Figure 6. Compound FIFO Expansion.

M 672061F

DEPTH

EXPANSION

BLOCK

M 672061F

DEPTH

EXPANSION

BLOCK

M 672061F

DEPTH

EXPANSION

BLOCK

R . W . RS

Q0 – Q8

Q9 – Q17

Q(N–8) – QN

I(N–8) – IN

I9 – I17

I0 – I8

I9 – I17

I0 – I8

Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4.

7. For Flag detection see section on Width Expansion and Figure 3.

Figure 7. Bidirectional FIFO Mode.

672061F

SYSTEM A SYSTEM B

FFA

EFB

PHFB

IA 0–8QB 0–8

IB 0–8

QA 0–8

PHFA

EFA

FFB

M672061F

Rev. D – June 5, 200010

Electrical Characteristics

Absolute Maximum Ratings

Supply voltage (VCC – GND) – 0.3 V to 7.0 V. . . . . . . . . . . . . . . . . .

Input or Output voltage applied : (GND – 0.3 V) to (Vcc + 0.3 V). . . .

Storage temperature : – 65 °C to + 150 °C. . . . . . . . . . . . . . . . . . . . . .

OPERATING RANGE OPERATING SUPPLY VOLTAGE OPERATING TEMPERATURE

Military Vcc = 5 V ± 10 % – 55 °C to + 125 °C

DC Parameters

Parameter Description M 672061F-30 M 672061F-15 UNIT VALUE

ICCOP (8) Operating supply current 110 120 mA Max

ICCSB (9) Standby supply current 5 5 mA Max

ICCPD (10) Power down current 400 400 µA Max

Notes : 8. Icc measurements are made with outputs open.

9. R = W = RS = FL/RT = VIH.

10. All input = Vcc.

PARAMETER DESCRIPTION M672061F UNIT VALUE

ILI (11) Input leakage current ± 1 µA Max

ILO (12) Output leakage current ± 1 µA Max

VIL (13) Input low voltage 0.8 V Max

VIH (13) Input high voltage 2.2 V Min

VOL (14) Output low voltage 0.4 V Max

VOH (14) Output high voltage 2.4 V Min

C IN (15) Input capacitance 8 pF Max

C OUT (15) Output capacitance 8 pF Max

Notes : 11. 0.4 ≤ Vin ≤ Vcc.

12. R = VIH, 0.4 ≤ VOUT ≤ VCC.

13. VIH max = Vcc + 0.3 V. VIL min = –0.3 V or –1 V pulse width 50 ns. For XI input, VIH= 2.8V

14. Vcc min, IOL = 8 mA, IOH = –2 mA.

15. Guaranteed but not tested.

AC Test Conditions

Input pulse levels : Gnd to 3.0 V

Input rise/Fall times : 5 ns

Input timing reference levels : 1.5 V

Output reference levels : 1.5 V

Output load : See figure 8

Figure 8. Output Load.

OUTPUT

PIN 333 Ω30 pF*

500 Ω

5 V

* includes jig and scope capacitance

M672061F

Rev. D – June 5, 2000 11

SYMBOL (16) SYMBOL (17) PARAMETER (18) (22) M672061F

– 30 M672061F

– 15 UNITSYMBOL (16) SYMBOL (17) PARAMETER (18) (22) MIN. MAX. MIN. MAX. UNIT

READ CYCLE READ CYCLE

TRLRL tRC Read cycle time 40 –25 –ns

TRLQV tA Access time –30 –15 ns

TRHRL tRR Read recovery time 10 –10 –ns

TRLRH tRPW Read pulse width (19) 30 –15 –ns

TRLQX tRLZ Read low to data low Z (20) 3–0–ns

TWHQX tWLZ Write low to data low Z (20, 21) 3–3–ns

TRHQX tDV Data valid from read high 5–5–ns

TRHQZ tRHZ Read high to data high Z (20) –20 –15 ns

WRITE CYCLE WRITE CYCLE

TWLWL tWC Write cycle time 40 –25 –ns

TWLWH tWPW Write pulse width (19) 30 –15 –ns

TWHWL tWR Write recovery time 10 –10 –ns

TDVWH tDS Data set-up time 18 –9–ns

TWHDX tDH Data hold time 0–0–ns

RESET CYCLE RESET CYCLE

TRSLWL tRSC Reset cycle time 40 –25 –ns

TRSLRSH tRS Reset pulse width (19) 30 –15 –ns

TWHRSH tRSS Reset set-up time 40 –25 –ns

TRSHWL tRSR Reset recovery time 10 –10 –ns

RETRANSMIT CYCLE RETRANSMIT

CYCLE

TRTLWL tRTC Retransmit cycle time 40 –25 –ns

TRTLRTH tRT Retransmit pulse width (19) 30 –15 –ns

TWHRTH tRTS Retransmit set-up time (20) 30 –15 –ns

TRTHWL tRTR Retransmit recovery time 10 –10 –ns

FLAGS FLAGS

TRSLEFL tEFL Reset to EF low –30 –25 ns

TRSLFFH tHFH, tFFH Reset to HF/FF high –30 –25 ns

TRLEFL tREF Read low to EF low –30 –15 ns

TRHFFH tRFF Read high to FF high –30 –25 ns

TEFHRH tRPE Read width after EF high 30 –15 –ns

TWHEFH tWEF Write high to EF high –30 –15 ns

TWLFFL tWFF Write low to FF low –30 –17 ns

TWLHFL tWHF Write low to HF low –30 –30 ns

TRHHFH tRHF Read high to HF high –30 –30 ns

TFFHWH tWPF Write width after FF high 30 –15 –ns

M672061F

Rev. D – June 5, 200012

SYMBOL (16) SYMBOL (17) PARAMETER (18) (22) M672061F

– 30 M672061F

– 15 UNITSYMBOL (16) SYMBOL (17) PARAMETER (18) (22) MIN. MAX. MIN. MAX. UNIT

EXPANSION

TWLXOL tXOL Read/Write to XO low –30 –15 ns

TWHXOH tXOH Read/Write to XO high –30 –15 ns

TXILXIH tXI XI pulse width 30 –15 –ns

TXIHXIL tXIR XI recovery time 10 –10 –ns

TXILRL tXIS XI set–up time 10 –10 –ns

Notes : 16. STD symbol.

17. ALT symbol.

18. Timings referenced as in ac test conditions.

19. Pulse widths less than minimum value are not allowed.

20. Values guaranteed by design, not currently tested.

21. Only applies to read data flow-through mode.

22. All parameters tested only.

Figure 9. Asynchr onous Write and Read Operation.

M672061F

Rev. D – June 5, 2000 13

Figure 10. Full Flag from Last Write to First Read.

Figure 11. Empty Flag from Last Read to First Write.

Figure 12. Retransmit.

Note : 23. EF, FF and PHF may change status during Retransmit, but flags will be valid at tRTC.

M672061F

Rev. D – June 5, 200014

Figure 13. Empty Flag Timing

Figure 14. Full Flag Timing

Figure 15. Programmable Half-Full Flag Timing.

PROGRAMMABLE

HALF FULL OFFSET OR LESS

PROGRAMMABLE

HALF FULL OFFSET OR LESS

MORE THAN HALF FULL

M672061F

Rev. D – June 5, 2000 15

Figure 16. Expansion Out.

Figure 17. Expansion In.

Figure 18. Read Data Flow – Through Mode.

M672061F

Rev. D – June 5, 200016

Figure 19. Write Data Flow – Through Mode.

M672061F

Rev. D – June 5, 2000 17

Ordering Information

M = Military –55°to +125°C

S = Space –55°to +125°C

* For ordering in QML quality level, use the QML PIN according to SMD number no 5962–93177.

MDP

CP = 28 pins 300 mils side brazed

DP = Flat pack 28 pins 400 mils

0 = Die form

67206FV

672061 = 16384 × 9 FIFO

FV = Very low power and rad tolerant

15 ns

30 ns

/883

blank = MHS standards

/883 = MIL-STD 883 CLASS B or S

TEMPERATURE RANGE PACKAGE DEVICE SPEED FLOW*

The information contained herein is subject to change without notice. No r esponsibility is assumed by TEMIC for using this publication and/or circuits

described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.