Zero-Drift, Single-Supply, Rail-to-Rail
Input/Output Operational Amplifiers
AD8571/AD8572/AD8574
Rev. E
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FEATURES
Low offset voltage: 1 μV
Input offset drift: 0.005 μV/°C
Rail-to-rail input and output swing
5 V/2.7 V single-supply operation
High gain: 145 dB typical
CMRR: 140 dB typical
PSRR: 130 dB typical
Ultralow input bias current: 10 pA typical
Low supply current: 750 μA per op amp
Overload recovery time: 50 μs
No external capacitors required
APPLICATIONS
Temperature sensors
Pressure sensors
Precision current sensing
Strain gage amplifiers
Medical instrumentation
Thermocouple amplifiers
GENERAL DESCRIPTION
This family of amplifiers has ultralow offset, drift, and bias
current. The AD8571, AD8572, and AD8574 are single, dual,
and quad amplifiers, respectively, featuring rail-to-rail input
and output swings. All are guaranteed to operate from 2.7 V to
5 V single supply.
The AD857x family provides benefits previously found only in
expensive auto-zeroing or chopper-stabilized amplifiers. Using
Analog Devices, Inc., topology, these zero-drift amplifiers
combine low cost with high accuracy. (No external capacitors
are required.) Using a patented spread-spectrum, auto-zero
technique, the AD857x family eliminates the intermodulation
effects from interaction of the chopping function with the
signal frequency in ac applications.
With an offset voltage of only 1 µV and drift of 0.005 µV/°C, the
AD857x family is perfectly suited for applications where error
sources cannot be tolerated. Position and pressure sensors,
medical equipment, and strain gage amplifiers benefit greatly
from nearly zero drift over their operating temperature range.
Many more systems require the rail-to-rail input and output
swings provided by the AD857x family.
PIN CONFIGURATIONS
V+
OUT A
NC
NC
NC = NO CONNECT
–IN A
+IN A
V–
NC 8
7
6
5
1
2
3
4
AD8571
TOP VIEW
(Not to Scale)
0
1104-001
Figure 1. 8-Lead MSOP (RM Suffix)
NC = NO CONNECT
AD8571
TOP VIEW
(Not to Scale)
NC
1
IN A
2
+IN A
3
V–
4
NC
V+
OUT A
NC
8
7
6
5
01104-004
Figure 2. 8-Lead SOIC (R Suffix)
–IN A
+IN A
V–
OUT B
–IN B
+IN B
OUT A V+
1
2
3
4
8
7
6
5
AD8572
TOP VIEW
(Not to Scale)
01104-002
Figure 3. 8-Lead TSSOP (RU Suffix)
–IN A
+IN A
V–
OUT B
–IN B
+IN B
OUT A V+
1
2
3
4
8
7
6
5
AD8572
TOP VIEW
(Not to Scale)
01104-005
Figure 4. 8-Lead SOIC (R Suffix)
OUT A
1
–IN A
2
+IN A
3
V+
4
+IN B
5
OUT D
–IN D
+IN D
V–
+IN C
14
13
12
11
10
–IN B
6
OUT B
7
–IN C
OUT C
9
8
AD8574
TOP VIEW
(Not to Scale)
01104-003
Figure 5. 14-Lead TSSOP (RU Suffix)
OUT A
1
–IN A
2
+IN A
3
V+
4
+IN B
5
OUT D
–IN D
+IN D
V–
+IN C
14
13
12
11
10
–IN B
6
O
UT B
7
–IN C
OUT C
9
8
AD8574
TOP VIEW
(Not to Scale)
0
1104-006
Figure 6. 14-Lead SOIC (R Suffix)
The AD857x family is specified for the extended industrial/
automotive temperature range (−40°C to +125°C). The AD8571
single amplifier is available in 8-lead MSOP and narrow SOIC
packages. The AD8572 dual amplifier is available in 8-lead narrow
SOIC and surface-mount TSSOP packages. The AD8574 quad
amplifier is available in 14-lead narrow SOIC and TSSOP packages.
AD8571/AD8572/AD8574
Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Electrical Characteristics...................................................... 3
2.7 V Electrical Characteristics................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Functional Description.................................................................. 14
Amplifier Architecture .............................................................. 14
Basic Auto-Zero Amplifier Theory..........................................14
Auto-Zero Phase......................................................................... 15
Amplification Phase................................................................... 15
High Gain, CMRR, and PSRR .................................................. 16
Maximizing Performance Through Proper Layout............... 16
1/f Noise Characteristics ........................................................... 17
Random Auto-Zero Correction Eliminates Intermodulation
Distortion .................................................................................... 17
Broadband and External Resistor Noise Considerations.......... 18
Output Overdrive Recovery...................................................... 18
Input Overvoltage Protection................................................... 18
Output Phase Reversal............................................................... 18
Capacitive Load Drive ............................................................... 19
Power-Up Behavior.................................................................... 19
Applications Information.............................................................. 20
5 V Precision Strain Gage Circuit ............................................ 20
3 V Instrumentation Amplifier ................................................ 20
High Accuracy Thermocouple Amplifier............................... 21
Precision Current Meter............................................................ 21
Precision Voltage Comparator.................................................. 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
2/11—Rev. D to Rev. E
Changes to Figure 66...................................................................... 21
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 23
6/08—Rev. C to Rev. D
Changes to Figure 19 and Figure 20............................................... 8
Changes to Figure 44...................................................................... 12
Changes to Figure 38...................................................................... 13
Moved Figure 50 and Figure 51.................................................... 14
Changes to Figure 66, Precision Current Meter Section, Layout,
Figure 67, Equation 24, and Figure 68......................................... 21
5/07—Rev. B to Rev. C
Changes to Features.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Basic Auto-Zero Amplifier Theory Section ........... 14
Changes to Figure 50...................................................................... 15
Changes to Figure 55...................................................................... 16
Changes to Figure 66...................................................................... 21
Updated Outline Dimensions....................................................... 22
9/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Figure 50...................................................................... 14
Changes to Figure 51...................................................................... 15
Changes to Figure 66...................................................................... 21
Deleted Figure 69 and SPICE Macro-Model Section ................ 17
Deleted SPICE Macro-Model for the AD857x Section............. 18
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide.......................................................... 23
7/03—Rev. 0 to Rev. A
Renumbered Figures..........................................................Universal
Changes to Ordering Guide.............................................................4
Change to Figure 15. ...................................................................... 16
Updated Outline Dimensions....................................................... 19
10/99—Revision 0: Initial Version
AD8571/AD8572/AD8574
Rev. E | Page 3 of 24
SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 1 5 V
−40°C TA ≤ +125°C 10 V
Input Bias Current IB 10 50 pA
AD8571/AD8574 −40°C TA ≤ +125°C 1.0 1.5 nA
AD8572 −40°C TA ≤ +85°C 160 300 pA
−40°C TA ≤ +125°C 2.5 4 nA
Input Offset Current IOS 20 70 pA
AD8571/AD8574 −40°C TA ≤ +125°C 150 200 pA
AD8572 −40°C TA ≤ +85°C 30 150 pA
−40°C TA ≤ +125°C 150 400 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 120 140 dB
−40°C TA ≤ +125°C 115 130 dB
Large Signal Voltage Gain1 A
VO R
L = 10 kΩ, VO = 0.3 V to 4.7 V 125 145 dB
−40°C TA ≤ +125°C 120 135 dB
Offset Voltage Drift VOS/T −40°C TA ≤ +125°C 0.005 0.04 V/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
L = 100 kΩ to GND 4.99 4.998 V
R
L = 100 kΩ to GND @ −40°C to +125°C 4.99 4.997 V
R
L = 10 kΩ to GND 4.95 4.98 V
R
L = 10 kΩ to GND @ −40°C to +125°C 4.95 4.975 V
Output Voltage Low VOL R
L = 100 kΩ to V+ 1 10 mV
RL = 100 kΩ to V+ @ −40°C to +125°C 2 10 mV
R
L = 10 kΩ to V+ 10 30 mV
R
L = 10 kΩ to V+ @ −40°C to +125°C 15 30 mV
Short-Circuit Limit ISC ±25 ±50 mA
−40°C to +125°C ±40 mA
Output Current IO ±30 mA
−40°C to +125°C ±15 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V 120 130 dB
−40°C TA ≤ +125°C 115 130 dB
Supply Current per Amplifier ISY V
O = 0 V 850 975 A
−40°C TA ≤ +125°C 1000 1075 A
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 0.4 V/s
Overload Recovery Time 0.05 0.3 ms
Gain Bandwidth Product GBP 1.5 MHz
NOISE PERFORMANCE
Voltage Noise en p-p 0 Hz to 10 Hz 1.3 V p-p
0 Hz to 1 Hz 0.41 V p-p
Voltage Noise Density en f = 1 kHz 51 nV/√Hz
Current Noise Density in f = 10 Hz 2 fA/√Hz
1 Gain testing is dependent upon test bandwidth.
AD8571/AD8572/AD8574
Rev. E | Page 4 of 24
2.7 V ELECTRICAL CHARACTERISTICS
VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 1 5 V
−40°C TA ≤ +125°C 10 V
Input Bias Current IB 10 50 pA
AD8571/AD8574 −40°C TA ≤ +125°C 1.0 1.5 nA
AD8572 −40°C TA ≤ +85°C 160 300 pA
−40°C TA ≤ +125°C 2.5 4 nA
Input Offset Current IOS 10 50 pA
AD8571/AD8574 −40°C TA ≤ +125°C 150 200 pA
AD8572 −40°C TA ≤ +85°C 30 150 pA
−40°C TA ≤ +125°C 150 400 pA
Input Voltage Range 0 2.7 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 115 130 dB
−40°C TA ≤ +125°C 110 130 dB
Large Signal Voltage Gain1 A
VO R
L = 10 kΩ, VO = 0.3 V to 2.4 V 110 140 dB
−40°C TA ≤ +125°C 105 130 dB
Offset Voltage Drift VOS/T −40°C TA ≤ +125°C 0.005 0.04 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
L = 100 kΩ to GND 2.685 2.697 V
R
L = 100 kΩ to GND @ −40°C to +125°C 2.685 2.696 V
R
L = 10 kΩ to GND 2.67 2.68 V
R
L = 10 kΩ to GND @ −40°C to +125°C 2.67 2.675 V
Output Voltage Low VOL R
L = 100 kΩ to V+ 1 10 mV
R
L = 100 kΩ to V+ @ −40°C to +125°C 2 10 mV
R
L = 10 kΩ to V+ 10 20 mV
R
L = 10 kΩ to V+ @ −40°C to +125°C 15 20 mV
Short-Circuit Limit ISC ±10 ±15 mA
−40°C to +125°C ±10 mA
Output Current IO ±10 mA
−40°C to +125°C ±5 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V 120 130 dB
−40°C TA ≤ +125°C 115 130 dB
Supply Current per Amplifier ISY V
O = 0 V 750 900 A
−40°C TA ≤ +125°C 950 1000 A
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 0.5 V/s
Overload Recovery Time 0.05 ms
Gain Bandwidth Product GBP 1 MHz
NOISE PERFORMANCE
Voltage Noise en p-p 0 Hz to 10 Hz 2.0 V p-p
Voltage Noise Density en f = 1 kHz 94 nV/√Hz
Current Noise Density in f = 10 Hz 2 fA/√Hz
1 Gain testing is dependent upon test bandwidth.
AD8571/AD8572/AD8574
Rev. E | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 6 V
Input Voltage GND to VS + 0.3 V
Differential Input Voltage1 ±5.0 V
ESD (Human Body Model) 2000 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1 Differential input voltage is limited to ±5.0 V or the supply voltage,
whichever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in a circuit board for SOIC and
TSSOP packages.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
8-Lead SOIC (R) 158 43 °C/W
8-Lead MSOP (RM) 190 44 °C/W
8-Lead TSSOP (RU) 240 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 36 °C/W
ESD CAUTION
AD8571/AD8572/AD8574
Rev. E | Page 6 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
180
0
120
100
60
20
40
80
140
160
–1.5–2.5 –0.5 0.5 1.5 2.5
NUMBER OF AMPLIFIERS
OFFSET VOLTAGE (µV)
V
S
= 2.7V
V
CM
= 1.35V
T
A
= 25°C
01104-007
Figure 7. Input Offset Voltage Distribution
–40°C
+25°C
+85°C
50
40
30
20
10
0
–20
–10
–30 012 435
INPUT BIAS CURRENT (pA)
INPUT COMMON-MODE VOLTAGE (V)
V
S
= 5V
T
A
= –40°C, +25°C, +85°C
01104-008
Figure 8. Input Bias Current vs. Input Common-Mode Voltage
1500
–2000
1000
500
0
–1000
–1500
–500
012345
INPUT BIAS CURRENT (pA)
COMMON-MODE VOLTAGE (V)
V
S
= 5V
T
A
= 125°C
01104-009
Figure 9. Input Bias Current vs. Common-Mode Voltage
180
0
120
100
60
20
40
80
140
160
–1.5–2.5 –0.5 0.5 1.5 2.5
NUMBER OF AMPLIFIERS
OFFSET VOLTAGE (µV)
V
S
= 5V
V
CM
= 2.5V
T
A
= 25°C
0
1104-010
Figure 10. Input Offset Voltage Distribution
12
10
8
6
4
2
001234 65
NUMBER OF AMPLIFIERS
INPUT OFFSET DRIFT (nV/°C)
VS = 5V
VCM = 2.5V
TA = –40°C TO +125°C
0
1104-011
Figure 11. Input Offset Voltage Drift Distribution
SOURCE
SINK
10k
1k
100
10
1
0.1
0.0001 0.001 0.01 0.1 100101
OUTPUT VOLTAGE (mV)
LOAD CURRENT (mA)
V
S
= 5V
T
A
= 25°C
01104-012
Figure 12. Output Voltage to Supply Rail vs. Load Current
AD8571/AD8572/AD8574
Rev. E | Page 7 of 24
SOURCE SINK
10k
1k
100
10
1
0.1
0.0001 0.001 0.01 0.1 1 10 100
OUTPUT VOLTAGE (mV)
LOAD CURRENT (mA)
V
S
= 2.7V
T
A
= 25°C
01104-013
Figure 13. Output Voltage to Supply Rail vs. Load Current
1000
750
500
250
0
–75 –50 –25 0 25 50 75 100 125 150
INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
V
CM
= 2.5V
V
S
= 5V
01104-014
Figure 14. Input Bias Current vs. Temperature
5V
2.7V
1.0
0.8
0.6
0.4
0.2
0
–75 –25–50 25 750 50 100 150125
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
01104-015
Figure 15. Supply Current vs. Temperature
800
200
100
300
400
500
600
700
001 2 34 5 6
SUPPLY CURRENT PER AMPLIFIER (µA)
SUPPLY VOLTAGE (V)
T
A
= 25°C
01104-016
Figure 16. Supply Current per Amplifier vs. Supply Voltage
45
90
135
180
225
270
0
60
40
50
10
20
30
–10
0
–40
–30
–20
10k 100k 1M 10M 100M
OPEN-LOOP GAIN (dB)
PHASE SHIFT (Degrees)
FREQUENCY (Hz)
VS= 2.7V
CL = 0pF
RL =
01104-017
Figure 17. Open-Loop Gain and Phase Shift vs. Frequency
45
90
135
180
225
270
0
60
40
50
10
20
30
–10
0
–40
–30
–20
10k 100k 1M 10M 100M
OPEN-LOOP GAIN (dB)
PHASE SHIFT (Degrees)
FREQUENCY (Hz)
VS= 5V
CL = 0pF
RL =
01104-018
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency
AD8571/AD8572/AD8574
Rev. E | Page 8 of 24
60
40
50
10
20
30
–10
0
–40
–30
–20
100 10k1k 1M100k 10M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
S
= 2.7V
C
L
= 20pF
R
L
= 2k
A
V
= 100
A
V
= 10
A
V
= 1
01104-019
Figure 19. Closed-Loop Gain vs. Frequency
60
40
50
10
20
30
–10
0
–40
–30
–20
100 10k1k 1M100k 10M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
S
= 5V
C
L
= 20pF
R
L
= 2k
A
V
= 100
A
V
= 10
A
V
= 1
01104-020
Figure 20. Closed-Loop Gain vs. Frequency
300
240
270
150
180
210
90
120
0
30
60
100 10k1k 10M
OUTPUT IMPEDANCE ()
FREQUENCY (Hz)
A
V
= 1
A
V
= 100
A
V
= 10
V
S
= 2.7V
0
1104-021
1M100k
Figure 21. Output Impedance vs. Frequency
300
240
270
150
180
210
90
120
0
30
60
100 10k1k 10M
OUTPUT IMPEDANCE ()
FREQUENCY (Hz)
AV = 1
AV = 100
AV = 10
VS= 5V
01104-022
1M100k
Figure 22. Output Impedance vs. Frequency
V
S
= 2.7V
C
L
= 300pF
R
L
= 2k
A
V
= 1
2µs 500mV
0
1104-023
Figure 23. Large Signal Transient Response
VS = 5V
CL = 300pF
RL = 2k
AV = 1
01104-024
5µs 1V
Figure 24. Large Signal Transient Response
AD8571/AD8572/AD8574
Rev. E | Page 9 of 24
V
S
= ±1.35V
C
L
= 50pF
R
L
=
A
V
= 1
01104-025
5µs 50mV
Figure 25. Small Signal Transient Response
V
S
= ±2.5V
C
L
= 50pF
R
L
=
A
V
= 1
5µs 50mV
0
1104-026
Figure 26. Small Signal Transient Response
010 100 1k 10k
CAPACITANCE (pF)
01104-027
SMALL SIGNAL OVERSHOOT (%)
50
45
0
40
35
30
25
20
15
10
5
–OS
+OS
V
S
= ±1.35V
R
L
= 2k
T
A
= 25°C
Figure 27. Small Signal Overshoot vs. Load Capacitance
45
0
5
10
15
20
25
30
35
40
10 100 1k 10k
SMALL SIGNAL OVERSHOOT (%)
CAPACITANCE (pF)
V
S
= ±2.5V
R
L
= 2k
T
A
= 25°C
–OS
+OS
01104-028
Figure 28. Small Signal Overshoot vs. Load Capacitance
0V
V
IN
V
OUT
0V
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
V
S
= ±2.5V
V
IN
= –200mV p-p
(RET TO GND)
C
L
= 0pF
R
L
= 10k
A
V
= –100
20µs 1V
0
1104-029
Figure 29. Positive Overvoltage Recovery
0V
V
IN
V
OUT
0V
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
20µs 1V
V
S
= ±2.5V
V
IN
= 200mV p-p
(RET TO GND)
C
L
= 0pF
R
L
= 10k
A
V
= –100
01104-030
Figure 30. Negative Overvoltage Recovery
AD8571/AD8572/AD8574
Rev. E | Page 10 of 24
200µs 1V
V
S
= ±2.5V
R
L
= 2k
A
V
= –100
V
IN
= 60mV p-p
01104-031
Figure 31. No Phase Reversal
100 10k1k 1M100k 10M
CMRR (dB)
FREQUENCY (Hz)
V
S
= 2.7V
140
80
100
120
60
0
20
40
01104-032
Figure 32. CMRR vs. Frequency
100 10k1k 10M
CMRR (dB)
FREQUENCY (Hz)
V
S
= 5V
140
80
100
120
60
0
20
40
01104-033
1M100k
Figure 33. CMRR vs. Frequency
100 10k1k 1M100k 10M
PSRR (dB)
FREQUENCY (Hz)
V
S
= ±1.35V
140
80
100
120
60
0
20
40 –PSRR +PSRR
01104-034
Figure 34. PSRR vs. Frequency
100 10k1k 10M
PSRR (dB)
FREQUENCY (Hz)
V
S
= ±2.5V
140
80
100
120
60
0
20
40 –PSRR
+PSRR
01104-035
1M100k
Figure 35. PSRR vs. Frequency
100 10k1k 100k 1M
OUTPUT SWING (V p-p)
FREQUENCY (Hz)
3.0
1.5
2.0
2.5
1.0
0
0.5
V
S
= ±1.35V
R
L
= 2k
A
V
= 1
THD + N < 1%
T
A
= 25°C
01104-036
Figure 36. Maximum Output Swing vs. Frequency
AD8571/AD8572/AD8574
Rev. E | Page 11 of 24
100 10k1k 100k 1M
OUTPUT SWING (V p-p)
FREQUENCY (Hz)
5.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
S
= ±2.5V
R
L
= 2k
A
V
= 1
THD + N < 1%
T
A
= 25°C
01104-037
Figure 37. Maximum Output Swing vs. Frequency
0
V
V
S
= ±1.35V
A
V
= 120,000
1sec 50mV
0
1104-038
Figure 38. 0.1 Hz to 10 Hz Noise
1sec 50mV
V
S
= ±2.5V
A
V
= 120,000
01104-039
Figure 39. 0.1 Hz to 10 Hz Noise
V
S
= 2.7V
R
S
= 0
312
364
208
260
104
156
52
0 0.5 1.0 1.5 2.0 2.5
e
n (nV/ Hz)
FREQUENCY (kHz)
0
1104-040
Figure 40. Voltage Noise Density from 0 Hz to 2.5 kHz
V
S
= 2.7V
R
S
= 0
96
112
64
80
32
48
16
0 5 10 15 20 25
e
n (nV/ Hz)
FREQUENCY (kHz)
01104-041
Figure 41. Voltage Noise Density from 0 Hz to 25 kHz
V
S
= 5V
R
S
= 0
156
182
104
130
52
78
26
0 0.5 1.0 1.5 2.0 2.5
e
n (nV/ Hz)
FREQUENCY (kHz)
01104-042
Figure 42. Voltage Noise Density from 0 Hz to 2.5 kHz
AD8571/AD8572/AD8574
Rev. E | Page 12 of 24
V
S
= 5V
R
S
= 0
96
112
64
80
32
48
16
0 5 10 15 20 25
e
n (nV/ Hz)
FREQUENCY (kHz)
01104-043
Figure 43. Voltage Noise Density from 0 Hz to 25 kHz
V
S
= 5V
R
S
= 0
180
210
120
150
60
90
30
05
e
n (nV/ Hz)
FREQUENCY (Hz)
10
01104-044
Figure 44. Voltage Noise Density from 0 Hz to 10 Hz
V
S
= 2.7V TO 5.5V
150
145
140
130
135
125
–75 –50 –25 0 25 50 75 100 125 150
POWER SUPPLY REJECTION (dB)
TEMPERATURE (°C)
01104-045
Figure 45. Power Supply Rejection vs. Temperature
50
30
40
10
–30
–10
20
0
–40
–20
–50
–75 –50 –25 0 25 50 75 100 125 150
OUTPUT SHORT-CIRCUIT CURRENT (mA)
TEMPERATUREC)
V
S
= 2.7V
I
SC–
I
SC+
01104-046
Figure 46. Output Short-Circuit Current vs. Temperature
AD8571/AD8572/AD8574
Rev. E | Page 13 of 24
100
60
80
20
–60
–20
40
0
–80
–40
–100
–75 –50 –25 0 25 50 75 100 125 150
OUTPUT SHORT-CIRCUIT CURRENT (mA)
TEMPERATURE (°C)
V
S
= 5V
I
SC–
I
SC+
01104-047
Figure 47. Output Short-Circuit Current vs. Temperature
–75 –50 –25 0 25 50 75 100 125 150
OUTPUT VOLTAGE (mV)
TEMPERATURE (°C)
V
S
= 2.7V
R
L
= 1k
R
L
= 10kR
L
= 100k
100
250
200
0
150
25
50
75
125
175
225
01104-048
Figure 48. Output Voltage to Supply Rail vs. Temperature
–75 –50 –25 0 25 50 75 100 125 150
OUTPUT VOLTAGE (mV)
TEMPERATURE (°C)
V
S
= 5V
100
250
200
0
150
25
50
75
125
175
225
01104-049
R
L
= 1k
R
L
= 10k
R
L
= 100k
Figure 49. Output Voltage to Supply Rail vs. Temperature
AD8571/AD8572/AD8574
Rev. E | Page 14 of 24
B
FUNCTIONAL DESCRIPTION
The AD8571/AD8572/AD8574 are CMOS amplifiers that
achieve their high degree of precision through random frequency
auto-zero stabilization. The autocorrection topology allows the
AD857x to maintain its low offset voltage over a wide temperature
range, and the randomized auto-zero clock eliminates any inter-
modulation distortion (IMD) errors at the amplifier output.
The AD857x can run from a single-supply voltage as low as 2.7 V.
The extremely low offset voltage of 1 µV and no IMD products
allow the amplifier to be easily configured for high gains without
risk of excessive output voltage errors, which makes the AD857x
an ideal amplifier for applications requiring both dc precision
and low distortion for ac signals. The extremely small temperature
drift of 5 nV/°C ensures a minimum of offset voltage error over
its −40°C to +125°C temperature range. These combined features
make the AD857x an excellent choice for a variety of sensitive
measurement and automotive applications.
AMPLIFIER ARCHITECTURE
Each AD857x op amp consists of two amplifiers: a main amplifier
and a secondary amplifier that is used to correct the offset voltage
of the main amplifier. Both consist of a rail-to-rail input stage,
allowing the input common-mode voltage range to reach both
supply rails. The input stage consists of an NMOS differential
pair operating concurrently with a parallel PMOS differential
pair. The outputs from the differential input stages are combined in
another gain stage whose output is used to drive a rail-to-rail
output stage.
The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The output
voltage range is limited by the drain-to-source resistance of
these transistors. As the amplifier is required to source or sink
more output current, the voltage drop across these transistors
increases due to their on resistance (RDS). Simply put, the output
voltage does not swing as close to the rail under heavy output
current conditions as it does with light output current. This is a
characteristic of all rail-to-rail output amplifiers. Figure 12 and
Figure 13 show how close the output voltage can get to the rails
with a given output current. The output of the AD857x is short-
circuit protected to approximately 50 mA of current.
The AD857x amplifiers have exceptional gain, yielding greater
than 120 dB of open-loop gain with a load of 2 k. Because
the output transistors are configured in a common-source
configuration, the gain of the output stage, and thus the open-
loop gain of the amplifier, is dependent on the load resistance.
Open-loop gain decreases with smaller load resistances, which
is another characteristic of rail-to-rail output amplifiers.
BASIC AUTO-ZERO AMPLIFIER THEORY
Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for more than 15 years,
and some improvements have been made over time. The
AD857x design offers a number of significant performance
improvements over older versions while attaining a very
substantial reduction in device cost. This section offers a
simplified explanation of how the AD857x is able to offer
extremely low offset voltages and high open-loop gains.
As noted in the Amplifier Architecture section, each AD857x
op amp contains two internal amplifiers. One is used as the
primary amplifier, and the other as an autocorrection, or nulling,
amplifier. Each amplifier has an associated input offset voltage
that can be modeled as a dc voltage source in series with the
noninverting input. In Figure 50 and Figure 51, these are labeled
as VOSA and VOSB, where A denotes the nulling amplifier and
denotes the primary amplifier. The open-loop gain for the +IN
and −IN inputs of each amplifier is given as AX. Both amplifiers
also have a third voltage input with an associated open-loop
gain of BX.
VIN+
VIN–
VOUT
AB
AA
ΦA1
ΦB
VOSA
+
V
OSB
+
BB
CM2
CM1
ΦA2
VNB
VNA
–BA
VOA ΦB
0
1104-050
Figure 50. Auto-Zero Phase of the Amplifier
V
IN+
V
IN–
V
OUT
A
B
A
A
ΦA
ΦB
V
OSA
+
V
OSB
+
B
B
C
M2
C
M1
ΦA
V
NB
V
NA
–B
A
V
OA
ΦB
01104-051
Figure 51. Output Phase of the Amplifier
There are two modes of operation determined by the action of
two sets of switches in the amplifier: an auto-zero phase and an
amplification phase.
AD8571/AD8572/AD8574
Rev. E | Page 15 of 24
AUTO-ZERO PHASE
In this phase, all ΦAX switches are closed, and all ΦB switches
are open. Here, the nulling amplifier is taken out of the gain
loop by shorting its two inputs together. Of course, there is a
degree of offset voltage, shown as VOSA, inherent in the nulling
amplifier, that maintains a potential difference between the +IN
and −IN inputs. The nulling amplifier feedback loop is closed
through ΦA2, and VOSA appears at the output of the nulling
amplifier and on CM1, an internal capacitor in the AD857x.
Mathematically, this can be expressed in the time domain as
VOA[t] = AAVOSA[t] − BAVOA[t] (1)
This can also be expressed as
[] []
A
OSAA
OA B
tVA
tV +
=1 (2)
The previous equations show that the offset voltage of the nulling
amplifier times a gain factor appears at the output of the nulling
amplifier and thus on the CM1 capacitor.
AMPLIFICATION PHASE
When the ΦB switches close and the ΦAX switches open for
the amplification phase, the offset voltage remains on CM1 and
essentially corrects any error from the nulling amplifier. The
voltage across CM1 is designated as VNA. The potential difference
between the two inputs to the primary amplifier is designated as
VIN, or VIN = (VIN+ − VIN−). The output of the nulling amplifier
can then be expressed as
VOA[t] = AA(VIN[t] − VOSA[t]) − BAVNA[t] (3)
Because ΦAX is now open and there is no place for CM1 to
discharge, the voltage (VNA) at the present time (t) is equal to
the voltage at the output of the nulling amp (VOA) at the time when
ΦAX is closed. If the period of the autocorrection switching
frequency is designated as TS, the amplifier switches between
phases every 0.5 × TS. Therefore, in the amplification phase
[]
= SNANA TtVtV 2
1 (4)
and substituting Equation 4 and Equation 2 into Equation 3 yields
[] [] []
A
SOSAAA
OSAA
IN
AOA B
TtVBA
tVAtVAtV +
+= 1
2
1
(5)
For the sake of simplification, it can be assumed that the auto-
correction frequency is much faster than any potential change
in VOSA or VOSB. This is a good assumption because changes in
offset voltage are a function of temperature variation or long-
term wear time, both of which are much slower than the
auto-zero clock frequency of the AD857x, which effectively
makes the VOS time invariant, and Equation 5 can be rewritten as
[] []
(
)
A
OSAAAOSAAA
IN
AOA B
VBAVBA
tVAtV +
+
+= 1
1 (6)
or
[] []
+
+=
A
OSA
IN
AOA B
V
tVAtV 1 (7)
Here, the auto-zeroing becomes apparent. Note that the VOS
term is reduced by a factor of 1 + BA, which shows how the
nulling amplifier has greatly reduced its own offset voltage error
even before correcting the primary amplifier. Therefore, the
primary amplifier output voltage is the voltage at the output of the
AD857x amplifier. It is equal to
VOUT[t] = AB(VIN[t] + VOSB) + BBVNB (8)
In the amplification phase, VOA = VNB, so this can be rewritten as
[
]
[] []
+
+++
A
OSA
IN
A
B
OSB
BINB
OUT
B
V
tVABVAtVA
tV
1
(9)
Combining terms yield
[
]
[]
()
OSB
B
A
OSA
B
A
B
A
BIN
OUT
VA
B
VBA
BAAtV
tV
+
+
++
1
(10)
The AD857x architecture is optimized in such a way that
AA = AB, BA = BB, and BA >> 1. In addition, the gain product to
AABB is much greater than AB. Therefore, Equation 10 can be
simplified to
VOUT[t] = VIN[t]AABA + AA(VOSA+ VOSB) (11)
Most obvious is the gain product of both the primary and nulling
amplifiers. This AABA term is what gives the AD857x its extremely
high open-loop gain. To understand how VOSA and VOSB relate to
the overall effective input offset voltage of the complete amplifier,
set up the generic amplifier equation of
VOUT = k × (VIN + VOS, EFF) (12)
where:
k is the open-loop gain of an amplifier.
VOS, EFF is its effective offset voltage.
Putting Equation 12 into the form of Equation 11 gives
VOUT[t] = VIN[t]AABA + VOS, EFFAABA (13)