STK11C68-M STK11C68-M CMOS nvSRAM High Performance 8K x 8 Nonvolatile Static RAM MIL-STD-883/SMD # 5962-92324 FEATURES DESCRIPTION * * * * * * * * * * * * The Simtek STK11C68-M is a fast static RAM (35, 45 and 55ns), with a nonvolatile electrically-erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (STORE), or from the EEPROM to the SRAM (RECALL) are initiated through software sequences. It combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. 35, 45 and 55ns Access Times 17, 20 and 25ns Output Enable Access Unlimited Read and Write to SRAM Software STORE Initiation Automatic STORE Timing 100,000 STORE cycles to EEPROM 10 year data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation Unlimited RECALL cycles from EEPROM Single 5V 10% Operation Available in multiple standard packages The STK11C68-M is pin compatible with industry standard SRAMs and is available in a 28-pin 300 mil ceramic DIP or 28-pad LCC package. Commercial and industrial devices are also available. 3 A3 STORE A0 A 12 NC A8 24 A9 A3 7 23 A11 STORE/ RECALL CONTROL A12 DQ 4 DQ 5 A1 A2 A10 27 3 26 VCC W NC A6 4 25 A8 A5 A4 5 24 6 23 A9 A 11 22 G 22 G A3 9 21 A 10 A2 8 21 A0 20 E 9 20 DQ 0 DQ 1 11 19 DQ 7 DQ 6 A1 A0 8 TOP VIEW 12 18 10 19 A 10 E DQ 7 DQ 0 11 18 DQ 6 DQ 1 DQ 2 12 17 13 16 DQ 5 DQ 4 VSS 14 15 DQ 3 28 - LCC 28 - 300 C-DIP PIN NAMES A0 - A12 COLUMN DECODER A0 28 2 10 COLUMN I/O INPUT BUFFERS DQ 3 1 A1 DQ 0 DQ 1 NC A 12 A7 7 13 14 15 16 17 A9 DQ 2 W 25 6 DQ5 A8 ARRAY 256 x 256 5 DQ4 A7 4 DQ3 A6 28 27 26 A4 A2 RECALL STATIC RAM 1 A6 A5 DQ2 Vss A5 ROW DECODER A4 2 NC EEPROM ARRAY 256 x 256 Vcc PIN CONFIGURATIONS A7 A 12 LOGIC BLOCK DIAGRAM A 11 G DQ 6 DQ 7 E W 4-31 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable VCC Power (+5V) VSS Ground STK11C68-M ABSOLUTE MAXIMUM RATINGSa Voltage on typical input relative to VSS. . . . . . . . . . . . . -0.6V to 7.0V Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .-0.5V to (VCC+0.5V) Temperature under bias . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (One output at a time, one second duration) (VCC = 5.0V 10%) DC CHARACTERISTICS SYMBOL PARAMETER ICC b Average VCC Current 1 ICC d 2 MIN MAX UNITS 90 mA tAVAV = 35ns 85 mA tAVAV = 45ns 80 mA tAVAV = 55ns 50 mA E (VCC - 0.2V) Average VCC Current 27 mA tAVAV = 35ns (Standby, Cycling TTL Input Levels) 23 mA tAVAV = 45ns 20 mA tAVAV = 55ns 2 mA E (VCC - 0.2V) VCC = max Average VCC Current all others VIN 0.2V or (VCC - 0.2V) during STORE cycle ISB c 1 NOTES E VIH; all others cycling ISB c 2 Average VCC Current all others VIN 0.2V or (VCC - 0.2V) (Standby, Stable CMOS Input Levels) IILK Input Leakage Current (Any Input) 1 A IOLK Off State Output Leakage Current 5 A VIN = VSS to VCC VCC = max VIN = VSS to VCC VIH Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs VIL Input Logic "0" Voltage VSS-.5 0.8 V All Inputs VOH Output Logic "1" Voltage VOL Output Logic "0" Voltage TA Operating Temperature 2.4 -55 V IOUT = -4mA 0.4 V IOUT = 8mA 125 C Note b: ICC 1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note d: ICC2 is the average current required for the duration of the store cycle (tSTORE) after the sequence (tWC) that initiates the cycle. AC TEST CONDITIONS Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 5.0V 480 Ohms Output CAPACITANCEe (TA=25C, f=1.0MHz) SYMBOL MAX UNITS CONDITIONS CIN Input Capacitance PARAMETER 5 pF V = 0 to 3V COUT Output Capacitance 7 pF V = 0 to 3V 255 Ohms 30pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading Note e: These parameters are guaranteed but not tested. 4-32 STK11C68-M (VCC = 5.0V 10%) READ CYCLES #1 & #2 SYMBOLS NO. 1 STK11C68-35M #1, #2 Alt. tELQV PARAMETER MIN tACS Chip Enable Access Time 2 tAVAV g tRC Read Cycle Time 3 tAVQVh tAA Address Access Time 4 tGLQV tOE Output Enable to Data Valid 5 tAXQX tOH Output Hold After Address Change 5 6 tELQX tLZ Chip Enable to Output Active 5 7 tEHQZi tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZi tOHZ Output Disable to Output Inactive e MAX STK11C68-45M MIN 35 35 MAX 45 MAX ns 25 5 0 ns 25 0 ns ns 20 25 0 ns 10 tELICCH tPA Chip Enable to Power Active 11 tEHICCLc,e tPS Chip Disable to Power Standby 35 45 55 ns tWHQV tWR Write Recovery Time 45 55 65 ns 11A 0 ns ns 20 17 55 5 5 17 ns ns 25 5 UNITS 55 55 45 20 0 MIN 45 35 0 STK11C68-55M ns Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note e: Parameter guaranteed but not tested. Note g: For READ CYCLE #1 and #2, W must be high for entire cycle. Note h: Device is continuously selected with E low and G low. Note i: Measured 200mV from steady state output voltage. READ CYCLE #1 g,h 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (Data Out) DATA VALID W 11A tWHQV READ CYCLE #2 g 2 tAVAV ADDRESS 1 tELQV 6 E 9 tGHQZ 8 tGLQX DQ (Data Out) DATA VALID 10 tELICCH W 7 tEHQZ 4 tGLQV G ICC 11 tEHICCL tELQX ACTIVE STANDBY 11A tWHQV 4-33 STK11C68-M (VCC = 5.0V 10%) WRITE CYCLES #1 & #2; G high SYMBOLS NO. #1 #2 STK11C68-35M PARAMETER Alt. MIN MAX STK11C68-45M MIN MAX STK11C68-55M MIN MAX UNITS 12 tAVAV tAVAV tWC Write Cycle Time 35 45 55 ns 13 tWLWH tWLEH tWP Write Pulse Width 30 35 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 30 35 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 18 20 30 ns 16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 30 35 45 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns WRITE CYCLES #1 & #2; G low (VCC = 5.0V 10%) SYMBOLS NO. #1 #2 STK11C68-35M PARAMETER Alt. MIN MAX STK11C68-45M MIN MAX STK11C68-55M MIN MAX UNITS 12 tAVAV tAVAV tWC Write Cycle Time 45 45 55 ns 13 tWLWH tWLEH tWP Write Pulse Width 35 35 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 35 35 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 30 30 30 ns 16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 35 35 45 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns tWZ Write Enable to Output Disable tOW Output Active After End of Write i,m 20 tWLQZ 21 tWHQX Note i: 35 5 Measured + 200mV from steady state output voltage. Note k: E or W must be VIH during address transitions. Note m: If W is low when E goes low, the outputs remain in the high impedance state. 4-34 35 5 35 5 ns ns STK11C68-M WRITE CYCLE #1: W CONTROLLEDk 12 tAVAV ADDRESS 14 tELWH 19 tWHAX E 17 tAVWH 18 13 tWLWH tAVWL W 15 tDVWH DATA IN 16 tWHDX DATA VALID 20 21 tWHQX tWLQZ DATA OUT HIGH IMPEDANCE PREVIOUS DATA WRITE CYCLE #2: E CONTROLLEDk 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT 16 tEHDX DATA VALID HIGH IMPEDANCE 4-35 STK11C68-M NONVOLATILE MEMORY OPERATION MODE SELECTION E W A12 - A0(hex) MODE I/O POWER H X X Not Selected Output High Z Standby L H X Read SRAM Output Data Active L L X Write SRAM Input Data Active L H 0000 Read SRAM Output Data Active 1555 Read SRAM Output Data n,o 0AAA Read SRAM Output Data n,o 1FFF Read SRAM Output Data n,o 10F0 Read SRAM Output Data 0F0F Nonvolatile STORE Output High Z ICC2 n 0000 Read SRAM Output Data Active n,o L H NOTES o n,o n,o 1555 Read SRAM Output Data n,o 0AAA Read SRAM Output Data n,o 1FFF Read SRAM Output Data n,o 10F0 Read SRAM Output Data n,o 0F0E Nonvolatile RECALL Output High Z n Note n: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA,1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. Note o: I/O state assumes that G VIL. Initiation and operation of nonvolatile cycles does not depend on the state of G. STORE CYCLE INHIBIT and AUTOMATIC POWER-UP RECALL VCC 5.0V 4.0 t STORE inhibit Automatic RECALL 4-36 STK11C68-M STORE/RECALL CYCLE (VCC = 5.0V 10%) SYMBOLS NO. #1 STK11C68-35M PARAMETER Alt. MIN STORE/RECALL Initiation Cycle Time tRC MAX 35 STK11C68-45M MIN MAX 45 STK11C68-55M MIN MAX 22 tAVAV 23 tELQZp Chip Enable to Output Inactive 75 75 85 ns 24 tELQXS tSTOREq STORE Cycle Time 10 10 10 ms 25 tELQXR tRECALLr RECALL Cycle Time 20 s 26 tAVELNs tAE Address Set-up to Chip Enable 0 0 0 27 tELEHNs,t tEP Chip Enable Pulse Width 25 35 45 ns 28 tEHAXNs tEA Chip Disable to Address Change 0 0 0 ns 20 55 UNITS 20 ns ns Note p: Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note q: Note that STORE cycles (but not RECALLs) are aborted by VCC < 4.0V (STORE inhibit). Note r: A RECALL cycle is initiated automatically at power up when VCC exceeds 4.0V. tRECALL is measured from the point at which VCC exceeds 4.5V. Note s: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence. Note t: If the Chip Enable Pulse Width is less than tELQV (see READ CYCLE #2) but greater than or equal to tELEHN, then the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. Note u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK11C68-M performs a STORE or RECALL. Note v: E must be used to clock in the address sequence for the Software STORE and RECALL cycles. STORE/RECALL CYCLE u,v 22 tAVAV ADDRESS 22 tAVAV ADDRESS #6 ADDRESS #1 26 tAVELN 27 tELEHN 28 tEHAXN E 24 tSTORE 25 tRECALL 23 tELQZ DATA OUT DATA VALID DATA VALID 4-37 HIGH IMPEDANCE STK11C68-M DEVICE OPERATION The STK11C68-M has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. SRAM READ The STK11C68-M performs a READ cycle whenever E and G are LOW while W is HIGH. The address specified on pins A0-12 determines which of the 8192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ CYCLE #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ CYCLE #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. The STK11C68-M is a high speed memory and therefore must have a high frequency bypass capacitor of approximately 0.1F connected between DUT VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM WRITE A write cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W go HIGH at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept HIGH during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tWLQZ after W goes LOW. To initiate the STORE cycle the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. HARDWARE PROTECT The STK11C68-M offers hardware protection against inadvertent STORE cycles through VCC Sense. A STORE cycle will not be initiated, and one in progress will discontinue, if VCC goes below 4.0V. 4.0V is a typical, characterized value. The datasheet specifications are guaranteed only for VCC = 5.0 +10%. NONVOLATILE RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: NONVOLATILE STORE The STK11C68-M STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the STK11C68-M implements nonvolatile operation while remaining pin-for-pin compatible with standard 8Kx8 SRAMs. During the STORE cycle, an erase of the 4-38 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle STK11C68-M Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. On power-up, once VCC exceeds the VCC sense voltage of 4.0V, a RECALL cycle is automatically initiated. The voltage on the VCC pin must not drop below 4.0V once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until tRECALL after VCC exceeds 4.0V. 4.0V is a typical, characterized value. If the STK11C68-M is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected between W and system VCC. 4-39 STK11C68-M ORDERING INFORMATION STK11C68 - 5 C 35 M Temperature Range M = Military (-55 to 125 degrees C) Access Time 35 = 35ns 45 = 45ns 55 = 55ns Package C = Ceramic 28 pin 300-mil DIP with gold lead finish K = Ceramic 28 pin 300-mil DIP with solder DIP finish L = Ceramic 28 pin LCC Retention / Endurance 10 years / 100,000 cycles 5962-92324 04 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = lead finish "A" or "C" is acceptable Package MX = Ceramic 28 pin 300-mil DIP MY = Ceramic 28 pin LCC Access Time 04 = 55ns 05 = 45ns 06 = 35ns 4-40