REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Changes in accordance with NOR 5962-R027-94. 93-11-05
Michael A. Frye
B
Boilerplate update, part of 5 year review. ksr 07-03-05
Joseph Rodenbeck
REV
SHEET
REV B B
SHEET 15 16
REV STATUS REV B B B B B B B B B B B B B B
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Gary L. Gross
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Jeffery D. Bowling
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
APPROVED BY
Michael A. Frye
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
93-04-09
MICROCIRCUIT, MEMORY,
DIGITAL, CMOS, POWER
SWITCHED, 32K x 8-BIT PROM,
MONOLITHIC SILICON
AMSC N/A
REVISION LEVEL
B SIZE
A CAGE CODE
67268 5962-93166
SHEET
1 OF
16
DSCC FORM 2233
APR 97 5962-E210-07
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1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962 - 93166 01 Q Y C
│ │ │ │ │ │
│ │ │ │ │ │
│ │ │ │ │ │
Federal RHA Device Device Case Lead
stock class designator type class outline finish
designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5)
\ / (see 1.2.3)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number 1/ Circuit function Access time
01 32K x 8 PROM 55 ns
02 32K x 8 PROM 45 ns
03 32K x 8 PROM 35 ns
04 32K x 8 PROM 55 ns
05 32K x 8 PROM 45 ns
06 32K x 8 PROM 35 ns
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level
as follows:
Device class Device requirements documentation
M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN
class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
X GDIP4-T28 or CDIP3-T28 28 Dual-in-line
Y GDFP2-F28 28 Flat pack
Z CQCC1-N32 32 Rectangular leadless chip carrier
U GDIP1-T28 or CDIP2-T28 28 Dual-in-line
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and
will also be listed in QML-38535 and MIL-HDBK-103 (see 6.6 herein).
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1.3 Absolute maximum ratings. 2/
Supply voltage range -------------------------------------------- -0.5 V dc to +7.0 V dc
DC voltage applied to outputs in high Z state ------------- -0.5 V dc to +7.0 V dc
DC input voltage -------------------------------------------------- -3.0 V dc to +7.0 V dc
DC program voltage---------------------------------------------- 13.0 V dc
Maximum power dissipation (PD) ---------------------------- 1.0 W 3/
Lead temperature (soldering, 10 seconds maximum)--- +260°C
Thermal resistance, junction-to-case (θJC) ----------------- See MIL-STD-1835
Junction temperature (TJ)--------------------------------------- +175°C
Storage temperature range------------------------------------- -65°C to +150°C
Temperature under bias----------------------------------------- -55°C to +125°C
Data Retention----------------------------------------------------- 10 years (minimum)
1.4 Recommended operating conditions.
Supply voltage (VCC) -------------------------------------------- 4.5 V dc to 5.5 V dc
Ground voltage (GND)------------------------------------------- 0.0 V DC
Input high voltage (VIH) ----------------------------------------- 2.0 V dc minimum
Input Low voltage (VIL) ------------------------------------------ 0.8 V dc maximum
Case operating temperature range (TC) -------------------- -55°C to +125°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the
Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation.
AMERICAN SOCIETY FOR TEST ING AND MATERIALS (ASTM)
ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena from
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr
Harbor Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)
2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
3/ Must withstand the added PD due to short circuit test e.g.; IOS.
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ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD78 - IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201; http://www.jedec.org.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless
a specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing
shall be as specified on figure 2 herein. When required in screening (see 4.2 herein) or qualification conformance inspection
groups A, B, C, or D (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50
percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item
drawing.
3.2.3.2 Programmed devices. The truth tables for programmed devices shall be as specified by an attached altered item
drawing.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
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TABLE I. Electrical performance characteristics.
Limit
Test
Symbol Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
subgroups
Device
type Min Max
Unit
Output high voltage
VOH
VCC = 4.5 V, IOH = -2.0 mA,
VIN = VIH, VIL
1,2,3
All
2.4
V
Output low voltage
VOL
VCC = 4.5 V, IOL = 6.0 mA,
VIN = VIH, VIL
0.4
Input high voltage 1/
VIH
2.0
Input low voltage 1/
VIL
0.8
Input leakage current
IIX
GND < VIN < VCC
VCC = 5.5 V
-10
+10
µA
Output leakage current
IOZ
GND < VOUT < VCC
VCC = 5.5 V
-40
+40
Output short circuit current
2/ 3/
IOS
VCC = 5.5 V, VOUT = 0.0 V
-20
-90
mA
Power supply current
ICC
VCC = 5.5 V, IOUT = 0 mA,
VIN = 0 to 3.0 V,
f = fMAX 4/ 5/
130
Standby supply current
ISB
VCC = 5.5 V, CS 1 > VIH,
IOUT = 0 mA, VIN = 2.0 V
40
Input capacitance 3/
CIN
VCC = 5.0 V,
T = 25°C, f = 1 MHz,
(see 4.4.1c)
4
10
pF
Output capacitance 3/
COUT
VCC = 5.0 V,
T = 25°C, f = 1 MHz
(see 4.4.1c)
4
10
Functional testing See 4.4.1d 7,8A,8B
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Limit
Unit
Symbol Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
subgroups
Device
type Min Max
Address to output valid
tAA
See figures 3 and 4,
and note 6/
9,10,11
01,04
55
ns
02,05 45
03,06 35
Chip select inactive to high Z
(CS1 and CS2 only) 3/ 7/
tHZCS
9,10,11
01,02
30
ns
03 25
Output enable inactive to high Z
3/ 7/
tHZOE
04
30
05,06 25
Chip select active to output
valid (CS 1 and CS2 only)
tACS
01,02
30
03 25
Output enable active to output
valid
tOE 04 30
05,06 25
Chip enable inactive to high Z
(CE only) 3/ 7/
tHZCE 01,04 60
02,05 50
03,06 40
Chip enable active to output
valid (CE only)
tACE 01,04 60
02,05 50
03,06 40
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Limit
Unit
Test
Symbol Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
subgroups
Device
type Min Max
Chip enable active to power
up 3/ tPU
ALL 0
Chip enable inactive to
power down 3/ tPD
01,04 60
02,05 50
03,06 40
Output hold from address
change 3/ tOH
ALL 0
1/ These are absolute values with respect to device ground and all overshoots and undershoots due to system or tester
noise are included.
2/ For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed
thirty seconds.
3/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to
the limits specified in table I.
4/ At f = fMAX, the inputs are switching at 1/tAA.
5/ Devices 01-03 CE = 0.0 V, CS 1 = 3.0 V, CS2 = 0.0 V; devices 04-06 CE = 0.0 V, OE = 3.0 V.
6/ AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0
to 3.0 V, and the output load on figure 3, circuit A.
7/ Transition is measured at steady-state high level -500 mV or steady-state low level +500 mV on the output from the 1.5 V
level on the input with the output load on figure 3, circuit B.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 42 (see MIL-PRF-38535, appendix A).
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Device
Types
01 - 03
04 - 06
Case
Outlines
X,Y
Z
U
Z
Terminal
Number
Terminal Symbol
Terminal Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
O3
O4
O5
O6
O7
NC
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC
O0
O1
O2
GND
NC
O3
O4
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
O3
O4
O5
O6
O7
NC
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
NC
O0
O1
O2
GND
NC
O3
O4
20
21
22
23
24
25
26
27
28
29
30
31
32
CE
CS2
CS 1
A14
A13
A12
A11
A10
VCC
---
---
---
---
O5
O6
O7
CE
CS2
CS 1
NC
A14
A13
A12
A11
A10
VCC
CE
A10
OE
A11
A9
A8
A13
A14
VCC
---
---
---
---
O5
O6
O7
CE
A10
OE
NC
A11
A9
A8
A13
A14
VCC
FIGURE 1. Terminal connections.
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Devices 01 - 03
State
Mode
CS2
CS1
CE
A14 - A0
Power
Outputs
Programmed Read VIH V
IL V
IL X ICC Data out
Standby X X VIH X ISB High Z
Output disable X VIH X X ICC High Z
Output disable VIL X X X ICC High Z
Unprogrammed Blank check ones VIHP V
PP V
ILP X ICC Zeros
Blank check
zeros VILP V
PP V
ILP X ICC Ones
Devices 04 - 06
State
Mode
CE
OE
VPP
A14 - A0
Power
Outputs
Programmed Read VIL V
IL X X ICC Data out
Standby VIH X X X ISB High Z
Output disable X VIH X X ICC High Z
Unprogrammed Blank check ones VIHP V
ILP V
PP X ICC Zeros
Blank check
zeros VILP V
ILP V
PP X ICC Ones
NOTES:
1. X = Don't care
2. High Z = High-impedance state
FIGURE 2. Truth table
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Circuit A Circuit B
Output load Output load for tHZCS, tHZOE, and tHZCE
NOTE: Including scope and jig (minimum values).
Load Circuit A Circuit B
R1 658 Ω 658 Ω
R2 403 Ω 403 Ω
CL 30 pF 5 pF
AC test conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
GND to 3.0 V
< 5 ns
1.5 V
1.5 V
FIGURE 3. Output load circuits and test conditions.
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NOTES:
1. CS 1 and CS2 are valid for device types 01-03 only. OE is valid for device types 04-06 only.
2. tHZOE and tOE are valid for device types 04-06 only.
FIGURE 4. Switching waveforms.
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3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in
a wide variety of configurations, two processing options are provided for selection in the contract using an altered item drawing.
3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1
and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program
configuration.
3.11.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions
herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery.
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical
parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).
c. Interim and final electrical test parameters shall be as specified in table IIA herein.
d. A data retention stress test shall be included as part of the screening procedure and shall consist of the following:
(Steps 1 through 4 are performed at the wafer level.)
(1) Program 100 percent of the total number of cells, excluding the security bit.
(2) Bake, unbiased, for 72 hours at +140°C or for 48 hours at +150°C or for 8 hours at +200°C, or 2 hours at +300°C for
unassembled devices only.
(3) Perform margin test using Vm = +5.7 V at +25°C using loose timing (i.e., tAA ≥ 1 µs).
(4) Erase.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
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4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified. Quality conformance inspection for device
class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for
device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted.
c. Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the designated
terminal and GND at a frequency equal or less than 1 MHz. Sample size is 15 devices with no failures, and all input
and output terminals tested.
d. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
e. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon
request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be used for reference.
f. Devices shall be tested for programmability and ac performance compliance to the requirements of group A, subgroups
9, 10, and 11. Either of two techniques is acceptable:
(1) Testing the entire lot using additional built-in test circuitry which allows the manufacturer to verify programmability
and ac performance without programming the user array. If this is done, the resulting test patterns shall be verified
on all devices during subgroups 9, 10, and 11, group A testing in accordance with the sampling plan specified in
MIL-STD-883, method 5005.
(2) If such compliance cannot be tested on an unprogrammed device, a sample shall be selected to satisfy
programmability requirements prior to performing subgroups 9, 10, and 11. Twelve devices shall be submitted to
programming (see 3.2.3.2). If more than two devices fail to program, the lot shall be rejected. At the manufacturer's
option, the sample may be increased to 24 total devices with no more than 4 total device failures allowable. Ten
devices from the programmability sample shall be submitted to the requirements of group A, subgroups 9, 10, and
11. If more than two devices fail, the lot shall be rejected. At the manufacturer's option, the sample may be
increased to 20 total devices with no more than 4 total device failures allowable.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005.
b. TA = +125°C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-93166
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET
14
DSCC FORM 2234
APR 97
TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/ 8/
Line
no.
Test requirements Subgroups
(in accordance with
MIL-STD-883,
TM 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M
Device
class Q
Device
class V
1
Interim electrical parameters
(see 4.2)
1, 7, 9
or
2, 8A, 10
2
Static burn-in
(method 1015)
Not
required
Not
required
Required
3
Same as line 1 1*, 7* ∆
4
Dynamic burn-in
(method 1015)
Required Required Required
5
Same as line 1 1*, 7* ∆
6
Final electrical parameters
(programmed) (see 4.2)
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
6A
Final electrical parameters
(unprogrammed) (see 4.2)
1*, 2, 3, 7*,
8A, 8B
1*, 2, 3, 7*,
8A, 8B
1*, 2, 3, 7*,
8A, 8B
7
Group A test requirements (see
4.4)
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
8
Group C end-point electrical
parameters (see 4.4)
2, 3, 7,
8A, 8B
2, 3, 7,
8A, 8B
1, 2, 3, 7, 8A,
8B, 9, 10, 11 ∆
9
Group D end-point electrical
parameters (see 4.4)
2, 3, 8A, 8B 2, 3, 8A, 8B 2, 3, 8A, 8B
10
Group E end-point electrical
parameters (see 4.4)
1, 7, 9 1, 7, 9 1, 7, 9
1/ Blank spaces indicate tests are not applicable.
2/ Any or all subgroups may be combined when using high-speed testers.
3/ Subgroups 7 and 8 functional tests shall verify the truth table.
4/ * indicates PDA applies to subgroup 1 and 7.
5/ ** see 4.4.1c.
6/ ∆ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with
reference to the previous interim electrical parameters (see line 1).
7/ See 4.6
8/ See 4.4.1e. Table IIB. Delta limits at +25°C.
Device types
Test 1/
All
IIX +10% of specified value in table I
IOZ +10% of specified value in table I
1/ The above parameter shall be recorded before and
after the required burn-in and life tests to determine the delta.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-93166
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET
15
DSCC FORM 2234
APR 97
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-
883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table IIA herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at
T
A = +25°C ± 5°C, after exposure, to the subgroups specified in table IIA herein.
4.5 Programming procedure. The programming procedures shall be as specified by the device manufacturer and shall be
made available upon request.
4.6 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7,
and 9.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-93166
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET
16
DSCC FORM 2234
APR 97
6.5 Symbols, definitions, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535, MIL-STD-1331, and as follows:
C
IN----------------------------------------Input terminal capacitance.
C
OUT -------------------------------------Output terminal capacitance.
I
CC ----------------------------------------Supply current.
I
IX -----------------------------------------Input current.
I
OZ ----------------------------------------Output current.
T
C-----------------------------------------Case temperature.
V
CC ---------------------------------------Positive supply voltage (5.0 V).
GND -------------------------------------Ground zero voltage potential.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 07-03-05
Approved sources of supply for SMD 5962-93166 are listed below for immediate acquisition only and shall be added
to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to
include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of
compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit
drawing PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9316601MXA 3/
0C7V7 CY7C271-55DMB
QP7C271-55DMB
5962-9316601MYA 3/
0C7V7 CY7C271-55KMB
QP7C271-55KMB
5962-9316601MZA 3/
0C7V7 CY7C271-55LMB
QP7C271-55LMB
5962-9316602MXA 3/
0C7V7 CY7C271-45DMB
QP7C271-45DMB
5962-9316602MYA 3/
0C7V7 CY7C271-45KMB
QP7C271-45KMB
5962-9316602MZA 3/
0C7V7 CY7C271-45LMB
QP7C271-45LMB
5962-9316603MXA 3/
0C7V7 CY7C271-35DMB
QP7C271-35DMB
5962-9316603MYA 3/
0C7V7 CY7C271-35KMB
QP7C271-35KMB
5962-9316603MZA 3/
0C7V7 CY7C271-35LMB
QP7C271-35LMB
5962-9316604MUA 3/ CY7C274-55DMB
5962-9316604MZA 3/ CY7C274-55LMB
5962-9316605MUA 3/ CY7C274-45DMB
5962-9316605MZA 3/ CY7C274-45LMB
5962-9316606MUA 3/ CY7C274-35DMB
5962-9316606MZA 3/ CY7C274-35LMB
1/ The lead finish shown for each PIN representing a hermetic package is the
most readily available from the manufacturer listed for that part. If the desired
lead finish is not listed, contact the Vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired to this
number may not satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the Government
assumes no liability whatsoever for any inaccuracies in this information bulletin.
