Standard Pr oducts
June 1997
1 Megabit (128K x8) CMOS Mask-Programmable ROM
1
Features
•Fast Read Access Time - 70ns
•Low Power CMOS Operation
– 20
µ
A max. Standby
– 15mA max. Active at 5MHz
•Wide Selection of JEDEC Standard Packages
– 40-Lead 600-mil PDIP
– 44-Pad PLCC
– 40-Lead TSOP
– 48-Lead TSOP
•2.7V–3.6V Supply
•High Reliability CMOS Technology
– 2000V ESD Protection
– 200mA Latchup Immunity
•Two-line Control
•CMOS and TTL Compatible Inputs and Outputs
•Full Commercial and Industrial Temperature Ranges
•Designed for Battery Supply Operation
Description
The S63B1001 is a low-power, high performance
1,048,576 bit Mask Programmable Read Only Memory
(ROM) organized 128K x 8 bits. It requires only one
power supply in normal operation. Any word can be
accessed in less than 70ns, eliminating the need for
speed reducing WAIT states on high-performance
microprocessor systems.
The S63B1001 typically consumes 9mA. Standby mode
supply current is typically less than 10
µ
A.
The S63B1001 comes in a choice of industry standard
JEDEC-approved packages including: plastic PDIP,
PLCC, and TSOP. The device features two-line control
(CE, OE) to give designers the flexibility to prevent bus
contention.
With high density 128K byte storage capability, the
S63B1001 allows firmware to be stored reliably and to be
accessed by the system without the delays of mass
storage media. AMI’s S63B1001 has additional features
to ensure high quality and efficient production use.
Block Diagram
Absolute Maximum Ratings
1
NOTE:1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent danger
to the device. This is a stress rating only and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses less than 20ns.
Maximum pin voltage is V
CC
+0.6V DC which may overshoot to +6.0V for pulses of less than 20 ns.
Pin Configurations
Pin Capacitance
(f = 1 MHz T = 25
°
C)
NOTE: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Temperature Under Bias -55
°
C to +125
°
C
Storage Temperature -65
°
C to +150
°
C
Voltage on Any Pin with Respect
to Ground -2.0V to +6V
2
PIN NAME FUNCTION
A0-A16 Addresses
O0-O7 Outputs
CE Chip Enable
OE Output Enable
NC No Connect
TYPICAL MAXIMUM UNITS CONDITIONS
C
IN
4 8 pF V
IN
= 0V
C
OUT
812pFV
OUT
= 0V
VCC
GND
OE
CE
A0-A16
ADDRESS
INPUTS
OE, CE
Y DECODER
OUTPUT
BUFFERS
DATA OUTPUTS
O0 - O7
X DECODER
Y-GATING
CELL MATRIX
S63B1001
BA TTERY VOL T AGE