Standard Pr oducts
June 1997
1 Megabit (128K x8) CMOS Mask-Programmable ROM
1
Features
•Fast Read Access Time - 70ns
•Low Power CMOS Operation
– 20
µ
A max. Standby
– 15mA max. Active at 5MHz
•Wide Selection of JEDEC Standard Packages
– 40-Lead 600-mil PDIP
– 44-Pad PLCC
– 40-Lead TSOP
– 48-Lead TSOP
•2.7V–3.6V Supply
•High Reliability CMOS Technology
– 2000V ESD Protection
– 200mA Latchup Immunity
•Two-line Control
•CMOS and TTL Compatible Inputs and Outputs
•Full Commercial and Industrial Temperature Ranges
•Designed for Battery Supply Operation
Description
The S63B1001 is a low-power, high performance
1,048,576 bit Mask Programmable Read Only Memory
(ROM) organized 128K x 8 bits. It requires only one
power supply in normal operation. Any word can be
accessed in less than 70ns, eliminating the need for
speed reducing WAIT states on high-performance
microprocessor systems.
The S63B1001 typically consumes 9mA. Standby mode
supply current is typically less than 10
µ
A.
The S63B1001 comes in a choice of industry standard
JEDEC-approved packages including: plastic PDIP,
PLCC, and TSOP. The device features two-line control
(CE, OE) to give designers the flexibility to prevent bus
contention.
With high density 128K byte storage capability, the
S63B1001 allows firmware to be stored reliably and to be
accessed by the system without the delays of mass
storage media. AMI’s S63B1001 has additional features
to ensure high quality and efficient production use.
Block Diagram
Absolute Maximum Ratings
1
NOTE:1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent danger
to the device. This is a stress rating only and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses less than 20ns.
Maximum pin voltage is V
CC
+0.6V DC which may overshoot to +6.0V for pulses of less than 20 ns.
Pin Configurations
Pin Capacitance
(f = 1 MHz T = 25
°
C)
NOTE: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Temperature Under Bias -55
°
C to +125
°
C
Storage Temperature -65
°
C to +150
°
C
Voltage on Any Pin with Respect
to Ground -2.0V to +6V
2
PIN NAME FUNCTION
A0-A16 Addresses
O0-O7 Outputs
CE Chip Enable
OE Output Enable
NC No Connect
TYPICAL MAXIMUM UNITS CONDITIONS
C
IN
4 8 pF V
IN
= 0V
C
OUT
812pFV
OUT
= 0V
VCC
GND
OE
CE
A0-A16
ADDRESS
INPUTS
OE, CE
Y DECODER
OUTPUT
BUFFERS
DATA OUTPUTS
O0 - O7
X DECODER
Y-GATING
CELL MATRIX
S63B1001
BA TTERY VOL T AGE
Standard Pr oducts
1 Megabit (128K x8) CMOS Mask-Programmable ROM
June 1997
2
Operating Modes
DC and AC Operating Conditions
DC and Operating Characteristics
2.7V to 3.6V
MODE/PIN CE OE Ai V
CC
OUTPUTS
Read V
IL
V
IL
Ai V
CC
D
OUT
Output Disable X V
IH
XV
CC
High Z
Standby V
IH
XXV
CC
High Z
S63B1001
-70 -90 -120
Operating Temperature Commercial 0
°
C - 70
°
C0
°
C - 70
°
C0
°
C - 70
°
C
Industrial -40
°
C - 85
°
C -40
°
C - 85
°
C -40
°
C - 85
°
C
V
dd
Power Supply 2.7V – 3.6V 2.7V – 3.6V 2.7V – 3.6V
SYMBOL PARAMETER CONDITION APP. MIN MAX UNITS
I
LI
Input Load Current V
IN
= 0V to V
CC
Com., Ind.
±
1
µ
A
I
LO
Output Leakage Current V
OUT
= 0V to V
CC
Com., Ind.
±
5
µ
A
I
SB
V
CC
Standby Current CE = V
CC
±
0.3V 20
µ
A
I
CC
V
CC
Active Current f = 5MHz, I
OUT
= 0mA,
CE = V
IL
,V
CC
= 3.6V Com. 15 mA
Ind. 20 mA
V
IL
Input Low Voltage V
CC
= 3.0V to 3.6V 0.8 V
V
CC
= 2.7V to 3.6V 0.2 x V
CC
V
V
IH
Input High Voltage V
CC
= 3.0V to 3.6V 2.2 V
V
CC
= 2.7V to 3.6V 0.7 x V
CC
V
V
OL
Output Low Voltage 2mA 0.4 V
100
µ
A 0.2 V
20
µ
A 0.1 V
V
OH
Output High Voltage -1mA 2.2 V
-100
µ
AV
CC
– 0.2 V
-20
µ
AV
CC
– 0.1 V
S63B1001
Standard Pr oducts
June 1997
1 Megabit (128K x8) CMOS Mask-Programmable ROM
3
AC Characteristics for Read Operations
2.7V - 3.6V
AC Waveforms
1
Notes:1. Timing measurement references are 1.5V. Input AC driving levels are 0V and 2.7V.
2. OE may be delayed up to t
CE
-t
OE
after the falling edge of CE without impact on t
CE
.
3. OE may be delayed up to t
ACC
-t
OE
after the address is valid without impact on t
ACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
Input Test Waveforms and Measurement Levels
Output Test Load
S63B1001
SYMBOL PARAMETER CONDITION -70 -90 -120
Min. Max. Min. Max. Min. Max.
t
ACC
3
Address to Output Delay CE=OE=V
IL
70ns 90ns 120ns
t
CE
2
CE to Output Delay OE=V
IL
70ns 90ns 120ns
t
OE
2,3
OE to Output Delay CE=V
IL
30ns 35ns 35ns
t
DF
4,5
OE or CE High to Output Float 25ns 25ns 30ns
t
OH
Output Hold from Addresses, CE or OE whichever
occurred first 0ns 0ns 0ns
ADDRESS VALID
OUTPUT
VALID
ADDRESS
CE
tCE
OE
OUTPUT HIGH Z
tOE
tDF
tOH
tACC
2.7V
0.0V
1.5V
tR, tF < 5 ns (10% to 90%)
AC
MEASUREMENT
LEVEL
AC
DRIVING
LEVELS
TEST COMPARATOR
OUT VL = 1.92V
CL = 30pF
RL = 476Ω
S63B1001
Standard Pr oducts
June 1997
1 Megabit (128K x8) CMOS Mask-Programmable ROM
4
32-Pin PDIP Specifications
Description
The Plastic Dual-In-Line Package (PDIP) meets widely
accepted industry standard for MOS/VLSI applications.
The package consists of a plastic body, transfer-molded
around the leadframe and die. The leadframe is copper
alloy, with external pins solder plated.
Internally, there is 125
µ
inch silver spot plating on the die
attach pad and on each bonding finger tip. These fingers
are electrically connected to the die by thermosonic gold
ball bonding techniques.
Pin Configuration
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
NC
NC
A14
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Package Description and Outline Dimensions
PDIP Specifications
NOTE:1. All measurements in inches.
2. Data is subject to change. Contact the factory for most current specifications.
SYMBOL
AA1BB1C D EE1eeAeBLB2S
MAX 0.180 - 0.020 0.055 0.012 1.655 0.625 0.550 0.100
TYP - 0.686 0.135 - -
MIN - 0.015 0.016 0.045 0.008 1.645 0.600 0.530 0.580 - 0.125 - -
LOW STRESS
MOLDING
COMPOUND
SOLDER PLATING
COPPER ALLOY
LEAD FRAME
CONDUCTIVE
DIE ATTACH
MATERIAL
SPOT SILVER
PLATING
GOLD
BONDING
WIRE
DIE
E1 E
1eA C
LEAD COUNT DIRECTION
LEAD 1
L
B1 e
A
DA1 eB
B
S63B1001
Standard Pr oducts
1 Megabit (128K x8) CMOS Mask-Programmable ROM June 1997
5
S63B1001
32-Pin PLCC Specifications
Description
The PLCC is transfer molded and thermosonic wire
bonded. Die is mounted on a copper alloy leadframe and
external leads are solder plated to provide improved
solderability.
Pin Configuration
A7
A6
A5
A4
A3
A2
A1
A0
O0
A14
A13
A8
A9
A11
OE
A10
CE
O7
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20
O1O2GNDO3O4 O5O6
29
28
27
26
25
24
23
22
21
A12 A15 A16 NC VCC NC NC
4321323130
Package Description
Package Outline Dimensions
PDIP Specifications
NOTE:1. All measurements in millimeters.
2. Data is subject to change. Contact the factory for most current specifications.
SYMBOL
A A1D1D2D3E1E2E3 e D E
MAX 3.56 2.41 11.51 10.92 7.62
BSC 14.05 13.46 10.16
BSC 1.27
BSC 12.57 15.11
MIN 2.45 1.52 11.35 9.91 13.89 12.45 12.32 14.86
SOLDER
PLATING
LOW STRESS
MOLDING COMPOUND
DIE
COPPER ALLOY
LEADFRAME
GOLD
WIRE
BOND
SILVER
PLATING
D1
1.22/1.07
2 PLCS
PIN 1
IDENTIFIER & ZONE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.51 MIN.
SEATING PLANE
.10
R 1.14/.64
D3
E3
D
E 1
E
A
e
D2/E2
.53/.33
.81/.66
A1
Standard Pr oducts
June 1997 1 Megabit (128K x8) CMOS Mask-Programmable ROM
6
S63B1001
32-Pin TSOP Specifications
Description
The Type I Thin Small Outline Package (TSOP) is a thin,
ends only package. This package is constructed using
the latest low stress molding compounds and bonding
technology to provide a pac kage with total body thickness
of less than 1.90mm.
This package is popular for ROM applications in memory
cards and other thin card applications.
Pin Configuration
A11
A9
A8
A13
A14
NC
NC
VCC
NC
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Package Description and Outline Dimensions
TSOP Specifications
NOTE:1. All measurements in millimeters.
2. Data is subject to change. Contact the factory for most current specifications.
Copyright®1997, American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, e xpress, statutory implied or b y description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI
reserv es the right to discontinue production and change specifications and prices at any time and without notice . AMI's products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental
requirements, or high reliability applications, such as militar y, medical life-support or life-sustaining equipment, are specifically not
recommended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796
SYMBOL
AA1A2B D E H e c Lα°
MAX 1.20 0.15 1.05 0.25 8.20 18.50 20.20 0.50
BSC 0.20 0.60 5
MIN - 0.0 0.95 0.15 7.80 18.30 19.80 0.10 0.40 0
DIE
LOW STRESS
MOLDING
COMPOUND GOLD WIRE BOND
A2 cL
TOP VIEW
0.90 (.035)
1
3
2
(SPHERICAL)
B
e
32
E
0.90 (.035)
PIN #1 I.D.
1.00 (.039) DIA
HPLANE
SEATING
A1
A
D
α°
