LE2416RDXATDG - ON SEMICONDUCTOR

1 Publication Order Number :

LE2416RDXA/D

www.onsemi.com

August 2016 - Rev. 1

ORDERING INFORMATION

See detailed ordering and shipping information on page 17 of this data sheet.

LE2416RDXA

16 kb I2C CMOS Serial EEPROM

Overview

The LE2416RDXA is two-wire serial interface EEPROM (Electrically

Erasable and Programmable ROM). This device realizes high speed and a

high level reliability by high performance CMOS EEPROM technology.

This device is compatible with I2C memory protocol, therefore it is best

suited for application that requires re-writable nonvolatile parameter

memory.

Function

 Capacity : 16k bits (2k  8 bits)

 Single supply voltage : 1.7 V to 3.6 V

 Operating temperature : 40 ºC to +85 ºC

 Interface : Two wire serial interface (I2C Bus*)

 Operating clock frequency : 400 kHz (Fast), 1000 kHz (Fast-Plus)

 Low Power consumption

: Standby : 2 µA (max.)

: Active (Read, 400 kHz) : 0.5 mA (max.)

Active (Read, 1000 kHz) : 2.0 mA (max.)

 Automatic page write mode : 16 Bytes

 Read mode : Sequential Read and random read

 Erase/Write cycles : 106 cycles (Page Write)

 Data Retention : 20 years

 Pull-up resistance: 5 kΩ (typ.) on WP pin with a built-in pull-up resister

 High reliability : Adopts proprietary symmetric memory array configuration (USP6947325)

Hardware write protect feature

Noise filters connected to SCL and SDA pins

Incorporates a feature to prohibit write operations under low voltage conditions.

 Package : LE2416RDXA WLP6(0.801.20) 0.33 mm height

Specifications

Absolute Maximum Ratings at Ta = 25C

Parameter Symbol Conditions Ratings Unit

Supply voltage 0.5 to +4.6 V

DC input voltage 0.5 to VDD+0.5 V

Over-shoot voltage 1.0 to VDD+1.0 V

Storage temperature Tstg 65 to +150 C

WLCSP6, 0.80x1.20

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,

damage may occur and reliability may be affected.

* This product is licensed from Silicon Storage Technology, Inc. (USA).

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Recommended Operating Conditions

Parameter Symbol Conditions Ratings Unit

min typ max

Operating supply voltage 1.7 3.6 V

Operating temperature 40 +85 C

DC Electrical Characteristics

Parameter Symbol Conditions Spec. Unit

min typ max

Supply current at reading ICC1 f = 400 kHz, VDD = VDD Max 0.5

f = 1000 kHz, VDD = VDD Max 2.0

Supply current at writing ICC2 f = 1000 kHz / 400 kHz,

tWC = 5 ms, VDD = VDD Max 3.0 mA

Standby current ISB WP = VDD2 = VDD

VIN = VDD or VSS 2 µA

Input leakage current ILI VIN = VSS to VDD, VDD = VDD Max 2.0 +2.0 µA

Output leakage current ILO VIN = VSS to VDD, VDD = VDD Max 2.0 +2.0 µA

Input Low voltage VIL V

DD  0.3 V

Input High voltage VIH V

DD  0.7 V

Output Low voltage

VOL2 IOL = 1. 0 m A , VDD = 1.7 V 0.2 V

IOL = 1.2 mA , V DD = 2.0 V

VOL1 IOL = 2. 1 m A , VDD = 2.0 V

0.4 V

IOL = 3.0 mA , V DD = 2.5 V

Capacitance at Ta = 25C, f = 1 MHz

Parameter Symbol Conditions max Unit

In/Output pin ca pacitanc e CI/O V

I/O = 0 V (SDA) 10 pF

Input pin capacitance CI V

IN = 0 V 10 pF

Note : These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices.

Pull-up resistance (WP) at Ta = 40 to 85C

Parameter Symbol Conditions min typ max Unit

Pull up resistance R Resistance between WP to VDD2 3500 5000 6500 

Note : These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices.

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended

Operating Ranges limits may affect device reliability.

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under different conditions.

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Fast-Plus (1000 kHz)

Parameter Symbol

Spec. Unit

min typ max

Slave mode SCL clock frequency fSCLS 0 1000 kHz

SCL clock low time tLOW 500 ns

SCL clock high time tHIGH 300 ns

SDA output delay time tAA 50 450 ns

SDA data output hold time tDH 50 ns

Start condition setup time tSU.STA 250 ns

Start condition hold time tHD.STA 250 ns

Data in setup time tSU.DAT 50 ns

Data in hold time tHD.DAT 0 ns

Stop condition setup time tSU.STO 250 ns

SCL SDA rise time tR 120 ns

SCL SDA fall time tF 120 ns

Bus rel e ase time tBUF 500 ns

Noise suppression time tSP 50 ns

Write time tWC 5 ms

Fast (400 kHz)

Parameter Symbol

Spec. Unit

min typ max

Slave mode SCL clock frequency fSCLS 0 400 kHz

SCL clock low time tLOW 1200 ns

SCL clock high time tHIGH 600 ns

SDA output delay time tAA 100 900 ns

SDA data output hold time tDH 100 ns

Start condition setup time tSU.STA 600 ns

Start condition hold time tHD.STA 600 ns

Data in setup time tSU.DAT 100 ns

Data in hold time tHD.DAT 0 ns

Stop condition setup time tSU.STO 600 ns

SCL SDA rise time tR 300 ns

SCL SDA fall time tF 300 ns

Bus rel e ase time tBUF 1200 ns

Noise suppression time tSP 50 ns

Write time tWC 5 ms

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Standard (100 kHz)

Parameter Symbol

Spec. Unit

min typ max

Slave mode SCL clock frequency fSCLS 0 100 kHz

SCL clock low time tLOW 4700 ns

SCL clock high time tHIGH 4000 ns

SDA output delay time tAA 100 3500 ns

SDA data output hold time tDH 100 ns

Start condition setup time tSU.STA 4700 ns

Start condition hold time tHD.STA 4000 ns

Data in setup time tSU.DAT 250 ns

Data in hold time tHD.DAT 0 ns

Stop condition setup time tSU.STO 4000 ns

SCL SDA rise time tR 1000 ns

SCL SDA fall time tF 300 ns

Bus rel e ase time tBUF 4700 ns

Noise suppression time tSP 50 ns

Write time tWC 5 ms

AC measurement condition

Input pulse level 0.2  VDD to 0.8  VDD

Input pulse rise / fall time 20 ns

Output timing reference level 0.5  VDD

Output load 100 pF

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Package Dimensions

unit : mm

WLCSP6, 0.80x1.20

CASE 567HM

ISSUE O

SEATING

PLANE

0.05 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO SPHERICAL

CROWNS OF SOLDER BALLS.

DIM

AMIN MAX

MILLIMETERS

D0.80 BSC

b0.15 0.25

e0.40 BSC

0.33

A B

PIN A1

REFERENCE

A0.05 BC

0.03 C

0.08 C

6X b

0.05 C

0.03 0.13

1.20 BSC

PITCH

0.20

DIMENSIONS: MILLIMETERS

*For a d d i t i o n a l i n f o r m a t i o n o n o u r P b-Fr e e s t r a t e g y a n d s o l d e r i n g

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.40

0.05 C

2X T OP VIEW

SIDE VIEW

BOTTOM VIE W

NOTE 3

RECOMMENDED

A1 PACKAGE

OUTLINE

PITCH

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Pin Assignment

Pin Descriptions

PIN.A1 VDD Power supply

PIN.A2 VDD2 Power supply for WP pin Pull-up

PIN.B1 WP Write protect

PIN.B2 VSS Ground

PIN.C1 SCL Serial clock input

PIN.C2 SDA Serial data input/output

Block Diagram

Ball side View

C B

VDD2 VSS SDA

VDD SCL WP

VDD2

EEPROM Array

X decoder

h volta

enerator

Serial-Parallel converter

Y decod er & Sense

Serial controller

SCL

SDA

Write controller

B C

2 VDD2 VSS SD

VDD SCL

Top View

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Bus timing

Write timing

Pin Function

SCL (Serial clock)

The SCL signal is used to control se rial input data timing. The SCL is used to latch input data synchronously

at the rising edge and read output data synchronously at the falling edge.

SDA (Serial input / output data)

The SDA pin is bidirectional for serial dat a transfer . It is an open-drain structure that needs to be pulled up by

resistor.

WP (Write protect)

When the WP input is high, write protection is enabled. When WP input is either low or floating, write

protection is disabled. The read operation is always activated irre spective of the WP pin status.

VDD2 (Po wer supply for WP pin pull-up)

VDD2 pin is for the pull-up power supply to WP pin. Voltage impression of 0.5 V to VDD +0.5 V is permitted

like other pins about the pin voltage.

Write Data Acknowledge Stop

condition Start

condition

tWC

SCL

SDA D0

tSU.DAT

tBUF

tSU.STO

SCL

SDA/IN

SDA/OUT

tSU.STA tHD.DAT

tHIGH t

LOW

tDH

tAA

tHD.STA

tSP

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Functional Description

The device supports the I2C protocol. Any device that send s data on to the bus is defined to be a transmitter ,

and any device that reads the data to a receiver. The device that controls the data transfer is known as the

bus master, and the other as the slave device.

1) Start Condition

A Start condition needs to start the EEPROM operati on, it is to set falling edge of the SDA while the SCL

is stable in the high status.

2) Stop Condition

A Start condition is identified by rising edge of the SDA signal while the SCL is stable in the high status.

The device becomes the standby mode from a Read operation by a Stop condition. In a write sequence,

a stop condition is trigger to terminate the write data input s and it is trigger to start the internal write cycle.

After the internally write cycle time which is specified as tWC, the device enters a standby mode.

3) Data Input

During data input, the device latches the SDA on the rising edge of the SCL. For correct the operation,

The SDA must be stable during the rising edge of the SCL.

Stop

condition

Start

condition

SCL

SDA

tSU.STA tHD.STA tSU.STO

SCL

SDA

tSU.DAT tHD.DAT

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4) Ackno wledge Bit (ACK)

The Acknowledge Bit is used to indicate a successful byte data transfer. The receiver sends a zero to

acknowledge that it has received each word (Device Code, Slave Address etc) from the transmitter.

5) Device addressing

To transmit between the bus master and slave device (EEPROM), the master must send a Start condition

to the EEPROM. The device address word of the EE PROM consis ts of 4-bit Device Code, 3-bit Memory

address and 1-bit read/write code. By sending these, it becomes possible to communicate between the

bus master and the EEPROM.

The upper 4-bit of the device address word are called the Device Code, the Device Code of the EEPROM

uses 1010b fixed code. This device does not have the Slave address.

When the Device Code and Memory address (A10, A9, A8) are received on the SDA, the device only

responds. The 8th bit is the read/write bit. The bit is set to 1 for Read operation and 0 for W rite operation.

If a match occurs on the Device Code, the corresponding device gives an acknowledgement on SDA

during the 9th bit time. If device does not match the Device Code, it deselects itself from the bus, and goes

into the Standby mode.

1 0 1 0 A10 A9 A8 R/W

Device Code Memory

Address

MSB LSB

Device address word

Acknowledge

Bit output

Start

condition

SCL

(

From T ransmitter

)

SDA

(From T ran smitter)

SDA

(EEPROM output)

8 9

tAA tDH

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6) EEPROM Write Operation

6)-1. Byte Write

The write operation requires a 7-bit device address (Device code + A10 + A9 + A8) with the 8th bit = 0

(write). Then the EEPROM sends acknowledgement 0 at the 9th clock cycle. After these, the EEPROM

receives word address (A7 to A0), and the EEPROM outputs acknowledgement 0. Then the EEPROM

receives 8-bit write data, the EEPROM outputs acknowledgement 0 after receipt of write data. If the

EEPROM receives a stop condition, the EEPROM enters an internally timed (tWC) write cycle and

terminates receipt of inputs until completion of the write cycle.

6)-2. Page Write

The Page write allows up to 16 bytes to be written in a single write cycle. The page write is the same

sequence as the byte write except for inputting the more write data. The page write is initiated by a start

condition, device code, memory address and write data(n) with every 9th bit acknowledgement. The

device enters the page write operation if this device receives more write data (n+1) instead of receiving a

stop condition. The page address (A0 to A3) bits are automatically incremented on receiving write

data(n+1). The device can contin ue to receive write data up to 16 by tes. If the page address bits reache s

the last address of the page, the page address bits wi ll roll over to the first address of the same page and

previous write data will be overwritten. After these, if the device receives a stop condition, the device

enters an internally timed (tWC×(n+x)) write cycle and terminates receipt of inputs until completion of the

write cycle.

Word Address

0 1 0 1

Start

K A

Sto

D7 D6 D5 D4 D3 D2 D1 D0

Data

R/W

10 A7 A6 A5 A4 A3 A2 A1 A0

Access from master device

0 1 0 1 W

Start

K A

Data(n)

R/W

Word Address(n)

10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Sto

D7 D6 ~ D1 D0

K A

·····

Data(n+x)

Data(n+1)

ACK

D7 D6 ~ D1 D0 D7 D6 ~ D1 D0 D7 D6 ~ D1 D0

Access from master device

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6)-3. Acknowledge Polling

The Acknowledge Polling operation is used to show if the EEPROM is in an internally timed write cycle or

not. This operation is initiated by the stop condition after inputting write data. This requires the 8-bit

device address word with the 8th bit = 0 (write) following the start condition duri ng an internally timed write

cycle. If the EEPROM is busy with the internal write cycle, no acknowledge will be returned. If the

EEPROM has terminated the internal write cycle, it responds with an acknowledge. The terminated write

cycle of the EEPROM can be known by this operation.

Access from master device

During Write

Start

NO ACK

SDA ······

Start

NO ACK

During Write

Start

No Write

R/W R/W R/W

0 1 0 A9

1 W

10 A8 0 1 0 A9

1 W

10 A8 0 1 0 A9

1 W

10 A8

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7) EEPROM Read Operation

7)-1. Current Address Read

The device has an internal address counter. It maintains that last address during the last read or write

operation, with incremented by one. The current address read accesses the address kept by the internal

address counter. After receiving a start condi tion and the device address word with the 8th bit = 1 (Read),

the EEPROM outputs the 8-bit current address data from following acknowledgement 0. If the EEPROM

receives acknowledgem ent 1 and a following sto p con dition, the EEPROM stops the read op eration and

is returned to a standby mode. In case the EEPROM has accessed the last address of the last page at

previous read operation, the current address will roll over and returns to zero address. In case EEPROM

has accessed the last address of the last page at previous write operation, the current address roll over

within page addressing a nd returns to the first address in the sam e page.

The current address is vali d while power is on. After power on, the current address will be reset (all 0).

Note: After the page write operation, the current address is the specified memory address in the last page

write, if the write data is more than 16-bytes.

7)-2. Random Read

The random read requires a dummy write to set read address. The EEPROM receives a start condition

and the device address (Device code + A10 + A9 + A8) with the 8th bit = 0 (write), the memory address.

The EEPROM outputs acknowledgement 0 after receiving memory address then enters a current

address read with receiving a start condition. The EEPROM outputs the read data of the address which

was defined in the dummy write operation. After receiving no acknowledgement and a following stop

condition, the EEPROM stops the random read operation and returns to a standby mode.

Access from master device

Device Address

K NO ACK

Sto

Data (n+1)

R/W

0 1 0 A9

1 R

Start

10 A8 D7 D6 D5 D4 D3 D2 D1 D0

Access from master device

Dummy Write

Device Address

R/W

Word Address(n)

ACK

Data(n)

Device Address

K NO ACK

Stop

Current Read

R/W

Start

SDA 0 1 0 1 W

10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 A9

1 R

Start

10 A8 D7 D6 ~ D1 D0

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7)-3. Sequential Read

The sequential read operation is initiated by either a current address read or random read. If the

EEPROM receives acknowledgement 0 after 8-bit read data, the read address is incremented and the

next 8-bit read data outputs. The current address will roll over and returns address zero if it reaches the

last address of the last page. The s equential read can be continued after roll ov er . The seq uential read is

terminated if the EEPROM receives no acknowledgement and a following stop condition.

Access from master device

NO ACK

Sto

Data(n+x)

D7 D6 ~ D1 D0

ACK

D7 D6 ~ D1 D0

Data(n)

Device Address

0 1 0 1

Start

Data(n+1) Data(n+2)

R/W

D7 D6 ~ D1 D0

K A

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Application Notes

1) Software reset function

Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is

executed in order to avoid erroneous operation after power-on and to reset while the command input

sequence. During the dummy clock inpu t period, the SDA bus must be opened (set to high by a pull-up

resistor). Since it is possible for the ACK output and read data to be output from the EEPROM during

the dummy clock period, forcibly entering H will result in an overcurrent flow.

Note that this software reset function does not work during the internal write cycle.

2) Pull-up resistor of SDA pin

Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor

(with a resistance from several k to several tens of k) without fail. The appropriate value must be

selected for this resistance (RPU) on the basis of the VIL and IIL of the microcontroller and other devices

controlling this product as well as the VOL – IOL characteristics of the product. Generally, when the

resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the

operating current consumption will increase.

RPU maximum value

The maximum resistance must be set in such a

way that the bus potential, which is determined

by the sum total (IL) of the input leaks of the

devices connected to the SDA bus and by RPU,

can completely satisfy the input high level (VIH

min) of the microcontroller and EEPROM.

However, a resistance value that satisfies SDA

rise time tR and fall time tF must be set.

RPU maximum value = (VDD  VIH) / IL

Example: When VDD = 3.0 V and I L = 2 A

RPU maximum value = (3.0 V  3.0 V  0.8) / 2 A = 300 k

RPU minimum value

A resistance corresponding to the low-level output voltage (VOL max) of EEPROM must be set.

RPU minimum value = (VDD  VOL) / IOL

Example: When VDD = 3.0 V, VOL = 0.4 V and IOL = 1 mA

RPU minimum value = (3.0 V  0.4) / 1 mA = 2.6 k

Recommended RPU setting

RPU is set to strike a good balance between the operating frequency requirements and power

consumption. If it is assumed that the SDA load capacitance is 50 pF and the SDA output data strobe

time is 500 ns, RPU will be about RPU = 500 ns/50 pF = 10 k.

Start

Condition

Start

Condition

SCL

SDA

1 2 8 9

Dummy clock x 9

Master

Device

EEPROM

SDA

CBUS

RPU

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3) Precautions when turning on the power

This product contains a power-on reset circuit for preventing the inadvertent writing of data when the

power is turned on. The following conditions must be met in order to ensure stable operation of this

circuit. No data guarantees are given in the event of an instantaneous power failure during the internal

write operation.

symbol Parameter Spec. Unit

Min. Typ. Max.

tRISE Power rise time – – 100 ms

tOFF Power off time 10 – – ms

Vbot Power bottom voltage – – 0.2 V

Notes:

1) The S DA pin must be set to high and the SCL pin to low or high.

2) Steps must be taken to ensure that the SDA and SCL pins are n ot placed in a high-impedance state.

A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during

power rise

After the power has stabilized, the SCL and SDA pin s must be controlled as shown below , with both pins

set to high.

B. If it is not possible to satisfy the instruction 2 in Note above

After the power has stabilized, software reset must be executed.

C. If it is not possible to satisfy the instructions both 1 and 2 in Note above

After the power has stabilized, the steps in A must be executed, then software reset must be executed.

4) Noise filter for the SCL and SDA pins

This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100 ns or

less are not recognized because of this function.

5) Function to inhibit writing when supply voltage is low

This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the

guaranteed operating supply voltage ra nge. The data is prote cted by ensuring that write operations are

not started at voltages (typ.) of 1.3 V and below.

VDD

tOFF

tRISE

Vbot

VDD

SCL

SDA

tLOW

tDH tSU.DAT

VDD

SCL

SDA tSU.DAT

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6) Notes on write protect operation

This product prohibits all memory array writing when the WP pin is high. To ensure full write protection,

the WP i s set high for all period s from the start condition to the sto p condition, an d the conditions belo w

must be satisfied.

symbol Parameter Spec. Unit

Min. Typ. Max.

tSU.WP WP Setup time 600 – – ns

tHD.WP WP Hold time 600 – – ns

Stop Condition

Start Condition

SCL

SDA

.WP tHD.WP

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MARKING INFORMATION

LE2416RDXA WLP6(0.80x1.20)

ORDERING INFORMATION

Device Package Shipping (Qty / Packing)

LE2416RDXATDG WLCSP6, 0.80x1.20

(Pb-Free / Halogen Free) 5000 / Tape & Reel

† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel

Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF

Part ID : 16S

Lot Number : 3digits

16S

Lot

* I2C Bus is a trademark of Philips Corporation.