ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 1/47
8 Mbit (1M x 8/512K x 16)
3V Only CMOS Flash Memory
1. FEATURES
z Single supply voltage 2.7V-3.6V
z Fast access time: 70/90 ns
z 1,048,576x8 / 524,288x16 switchable by BYTE pin
z Compatible with JEDEC standard
- Pin-out, packages and software commands
compatible with single-power supply Flash
z Low power consumption
- 7mA typical active current
- 25uA typical standby current
z 100,000 program/erase cycles typically
z 20 years data retention
z Command register architecture
- Byte programming (9us typical)
- Sector Erase(sector structure: one 16 KB, two 8 KB,
one 32 KB, and fifteen 64 KB)
z Auto Erase (chip & sector) and Auto Program
- Any combination of sectors can be erased
concurrently; Chip erase also provided.
- Automatically program and verify data at specified
address
z Erase Suspend/Erase Resume
- Suspend or Resume erasing sectors to allow the
read/program in another sector
z Ready/Busy (RY/ BY )
- RY/B
Y
output pin for detection of program or erase
operation completion
z End of program or erase detection
- Data polling
- Toggle bits
z Hardware reset
- Hardware pin( ESETR ) resets the internal state machine
to the read mode
z Sector Protection /Unprotection
- Hardware Protect/Unprotect any combination of sectors
from a program or erase operation.
z Low VCC Write inhibit is equal to or less than 2.0V
z Boot Sector Architecture
- U = Upper Boot Block
- B = Bottom Boot Block
z Packages available:
- 48-pin TSOPI
- All Pb-free products are RoHS-Compliant
2. ORDERING INFORMATION
Part No Boot Speed Package Comments Part No Boot Speed Package Comments
F49L800UA-70TIG Upper 70 ns TSOPI Pb-free F49L800UA-90TIG Upper 90 ns TSOPI Pb-free
F49L800BA-70TIG Bottom 70 ns TSOPI Pb-free F49L800BA-90TIG Bottom 90 ns TSOPI Pb-free
3. GENERAL DESCRIPTION
The F49L800UA/F49L800BA is a 8 Megabit, 3V only
CMOS Flash memory device organized as 1M bytes of 8
bits or 512K words of 16bits. This device is packaged in
standard 48-pin TSOP. It is designed to be programmed
and erased both in system and can in standard EPROM
programmers.
With access times of 70 ns and 90 ns, the
F49L800UA/F49L800BA allows the operation of
high-speed microprocessors. The device has separate
chip enableCE, write enable WE , and output enable OE
controls. ESMT's memory devices reliably store memory
data even after 100,000 program and erase cycles.
The F49L800UA/F49L800BA is entirely pin and
command set compatible with the JEDEC standard for 8
Megabit Flash memory devices. Commands are written to
the command register using standard microprocessor
write timings.
The F49L800UA/F49L800BA features a sector erase
architecture. The device memory array is divided into one
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and fifteen 64
Kbytes. Sectors can be erased individually or in groups
without affecting the data in other sectors. Multiple-sector
erase and whole chip erase capabilities provide the
flexibility to revise the data in the device.
The sector protect/unprotect feature disables both
program and erase operations in any combination of the
sectors of the memory. This can be achieved in-system or
via programming equipment.
A low VCC detector inhibits write operations on loss of
power. End of program or erase is detected by the
Ready/Busy status pin, Data Polling of DQ7, or by the
Toggle Bit I feature on DQ6. Once the program or erase
cycle has been successfully completed, the device
internally resets to the Read mode.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 2/47
4. PIN CONFIGURATIONS
4.1 48-pin TSOP
4.2 Pin Description
Symbol Pin Name Functions
A0~A18 Address Input To provide memory addresses.
DQ0~DQ14 Data Input/Output To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
DQ15/A-1 Q15 (Word mode) /
LSB addr (Byte Mode)
To bi-direction date I/O when BYTE is High
To input address when BYTE is Low
CE Chip Enable To activate the device when CE is low.
OE Output Enable To gate the data output buffers.
WE Write Enable To control the Write operations.
RESET Reset Hardware Reset Pin/Sector Protect Unprotect
BYTE Word/Byte selection input To select word mode or byte mode
RY/ BY Ready/Busy To check device operation status
VCC Power Supply To provide power
GND Ground
NC No connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
F49L800U/BA
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
GND
CE
A0
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 3/47
5. SECTOR STRUCTURE
Table 1: F49L800UA Sector Address Table
Sector Size Address range Sector Address
Sector Byte Mode Word Mode Byte Mode(x8) Word Mode(x16) A18 A17 A16 A15 A14 A13 A12
SA0 64Kbytes 32Kwords 00000H-0FFFFH 00000H-07FFFH 0 0 0 0 X X X
SA1 64Kbytes 32Kwords 10000H-1FFFFH 08000H-0FFFFH 0 0 0 1 X X X
SA2 64Kbytes 32Kwords 20000H-2FFFFH 10000H-17FFFH 0 0 1 0 X X X
SA3 64Kbytes 32Kwords 30000H-3FFFFH 18000H-1FFFFH 0 0 1 1 X X X
SA4 64Kbytes 32Kwords 40000H-4FFFFH 20000H-27FFFH 0 1 0 0 X X X
SA5 64Kbytes 32Kwords 50000H-5FFFFH 28000H-2FFFFH 0 1 0 1 X X X
SA6 64Kbytes 32Kwords 60000H-6FFFFH 30000H-37FFFH 0 1 1 0 X X X
SA7 64Kbytes 32Kwords 70000H-7FFFFH 38000H-3FFFFH 0 1 1 1 X X X
SA8 64Kbytes 32Kwords 80000H-8FFFFH 40000H-47FFFH 1 0 0 0 X X X
SA9 64Kbytes 32Kwords 90000H-9FFFFH 48000H-4FFFFH 1 0 0 1 X X X
SA10 64Kbytes 32Kwords A0000H-AFFFFH 50000H-57FFFH 1 0 1 0 X X X
SA11 64Kbytes 32Kwords B0000H-BFFFFH 58000H-5FFFFH 1 0 1 1 X X X
SA12 64Kbytes 32Kwords C0000H-CFFFFH 60000H-67FFFH 1 1 0 0 X X X
SA13 64Kbytes 32Kwords D0000H-DFFFFH 68000H-6FFFFH 1 1 0 1 X X X
SA14 64Kbytes 32Kwords E0000H-EFFFFH 70000H-77FFFH 1 1 1 0 X X X
SA15 32Kbytes 16Kwords F0000H-F7FFFH 78000H-7BFFFH 1 1 1 1 0 X X
SA16 8Kbytes 4Kwords F8000H-F9FFFH 7C000H-7CFFFH 1 1 1 1 1 0 0
SA17 8Kbytes 4Kwords FA000H-FBFFFH 7D000H-7DFFFH 1 1 1 1 1 0 1
SA18 16Kbytes 8Kwords FC000H-FFFFFH 7E000H-7FFFFH 1 1 1 1 1 1 X
Note: Byte Mode: address range A18:A-1, Word mode : address range A18:A0
Table 2: F49L800BA Sector Address Table
Sector Size Address range Sector Address
Sector Byte Mode Word Mode Byte Mode(x8) Word Mode(x16) A18 A17 A16 A15 A14 A13 A12
SA0 16Kbytes 8Kwords 00000H-03FFFH 00000H-01FFFH 0 0 0 0 0 0 X
SA1 8Kbytes 4Kwords 04000H-05FFFH 02000H-02FFFH 0 0 0 0 0 1 0
SA2 8Kbytes 4Kwords 06000H-07FFFH 03000H-03FFFH 0 0 0 0 0 1 1
SA3 32Kbytes 16Kwords 08000H-0FFFFH 04000H-07FFFH 0 0 0 0 1 X X
SA4 64Kbytes 32Kwords 10000H-1FFFFH 08000H-0FFFFH 0 0 0 1 X X X
SA5 64Kbytes 32Kwords 20000H-2FFFFH 10000H-17FFFH 0 0 1 0 X X X
SA6 64Kbytes 32Kwords 30000H-3FFFFH 18000H-1FFFFH 0 0 1 1 X X X
SA7 64Kbytes 32Kwords 40000H-4FFFFH 20000H-27FFFH 0 1 0 0 X X X
SA8 64Kbytes 32Kwords 50000H-5FFFFH 28000H-2FFFFH 0 1 0 1 X X X
SA9 64Kbytes 32Kwords 60000H-6FFFFH 30000H-37FFFH 0 1 1 0 X X X
SA10 64Kbytes 32Kwords 70000H-7FFFFH 38000H-3FFFFH 0 1 1 1 X X X
SA11 64Kbytes 32Kwords 80000H-8FFFFH 40000H-47FFFH 1 0 0 0 X X X
SA12 64Kbytes 32Kwords 90000H-9FFFFH 48000H-4FFFFH 1 0 0 1 X X X
SA13 64Kbytes 32Kwords A0000H-AFFFFH 50000H-57FFFH 1 0 1 0 X X X
SA14 64Kbytes 32Kwords B0000H-BFFFFH 58000H-5FFFFH 1 0 1 1 X X X
SA15 64Kbytes 32Kwords C0000H-CFFFFH 60000H-67FFFH 1 1 0 0 X X X
SA16 64Kbytes 32Kwords D0000H-DFFFFH 68000H-6FFFFH 1 1 0 1 X X X
SA17 64Kbytes 32Kwords E0000H-EFFFFH 70000H-77FFFH 1 1 1 0 X X X
SA18 64Kbytes 32Kwords F0000H-FFFFFH 78000H-7FFFFH 1 1 1 1 X X X
Note: Byte Mode: address range A18:A-1, Word mode : address range A18:A0
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 4/47
6. FUNCTIONAL BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
SENSE
AMPLIFIER
PGM
DATA
HV
PROGRAM
DATA LATCH
WRITE
STATE
MACHING
(WSM)
STATE
REGISTER
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
ADDRESS
LATCH
AND
BUFFER
A0~A18
CE
BYTE
OE
WE
RESET
PROGRAM / ERASE
HIGH VOLTAGE
F49L800U/BA
FLASH
ARRAY
Y-DECODER
X-DECODER
Y-PASS GATE
I/OBUFFER
DQ0~DQ15(A-1)
ARRAY
SOURCE
HV
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 5/47
7. FUNCTIONAL DESCRIPTION
7.1 Device operation
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
register serve as inputs to the internal state
machine. The state machine outputs dictate the
function of the device. The F49L800UA
/F49L800BA features various bus operations as
Table 3.
Table 3. F49L800UA/F49L800BA Operation Modes Selection
ADDRESS DQ8~DQ15
DESCRIPTION CE OE WE RESET A18
|
A12
A11
|
A10
A9
A8
|
A7
A6
A5
|
A2
A1 A0
DQ0~DQ7 BYTE
=VIH BYTE
=VIL
Reset(3) X X X
L, Vss±
0.3V(3) X High Z High Z High Z
Read L L H H AIN Dout Dout
Write L H L H AIN DIN DIN
DQ8~DQ14=
High Z
DQ15=A-1
Output Disable L H H H X High Z High Z High Z
Standby VCC±
0.3V X X VCC±
0.3V X High Z High Z High Z
Sector Protect(2) L H L VID SA X X X L X H L DIN X X
Sector Unprotect(2) L H L VID SA X X X H X H L DIN X X
Temporary sector unprotect X X X VID AIN DIN DIN High Z
Auto-select See Table 4
Notes:
1. L= Logic Low = VIL, H= Logic High = VIH, X= Don't Care, SA= Sector Address, VID=10V to 10.5V.
AIN= Address In, DIN = Data In, Dout = Data Out.
2. The sector protect and unprotect functions may also be implemented via programming equipment.
3. See “Reset Mode” section.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 6/47
Table 4. F49L800UA/F49L800BA Auto-Select Mode (High Voltage Method)
Description Mode CE OE WE
A18
to
A12
A11
to
A10
A9
A8
to
A7
A6
A5
to
A4
A3 A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
L L 8CH
LH 7FH
HL 7FH
Manufacturer ID:
ESMT L L H X X VID XLX
HH
L L X
7FH
Word L L H 22H DAH
Device ID:
F49L800UA
(Upper Boot
Block) Byte L L H
X X VID XLXXXL H
X DAH
Word L L H 22H 5BH
Device ID:
F49L800BA
(Bottom
Boot Block) Byte L L H
X X VID XLXXXL H
X 5BH
X 01H
(protected)
Sector Protection
Verification L L H SA X VID XLXXXH L
X 00H
(unprotected)
L= Logic Low=VIL, H= Logic High=VIH, SA= Sector Address, X= Don’t care.
Notes :
1.Manufacturer and device codes may also be accessed via the software command sequence in Table 5.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 7/47
Reset Mode :
Hardware Reset
When the ESETR pin is driven low for at least a
period of tRP, the device immediately terminates any
operation in progress, tri-states all output pins, and
ignores all read/write commands for the duration of the
ESETR pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated later once the device is
ready to accept another command sequence, to ensure
the data integrity.
The current is reduced for the duration of the ESETR
pulse. When ESETR is held at VSS±0.3V, the device
draws CMOS standby current (ICC4). If ESETR is held
at VIL but not within VSS±0.3V, the standby current will
be greater.
The ESETR pin may be tied to system reset circuitry.
A system reset would thus reset the Flash memory,
enabling the system to read the boot-up firm-ware from
the Flash memory.
If ESETR is asserted during a program or erase
embedded algorithm operation, the RY/B
Y
pin remains
a "0" (busy) until the internal reset operation is
complete, which requires a time of tREADY (during
Embedded Algorithms). The system can thus monitor
RY/ B
Y
to determine whether the reset operation is
complete.
If ESETR is asserted when a program or erase
operation is not executing , i.e. the RY/B
Y
is “1”, the
reset operation is completed within a time of tREADY (not
during Embedded Algorithms). The system can read
data after tRH when the ESETR pin returns to VIH.
Refer to the AC Characteristics tables 13 for Hardware
Reset section & Figure 23 for the timing diagram.
Read Mode
To read array data from the outputs, the system must
drive the CE and OE pins to VIL. CE is the power
control and selects the device. OE is the output
control and gates array data to the output pins. WE
should remain at VIH. The internal state machine is set
for reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious
alteration of the memory content occurs during the
power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor’s read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered. section for more information. Refer
to the AC Read Operations table 10 for timing
specifications and to Figure 5 for the timing diagram. ICC1
in the DC Characteristics table represents the active
current specification for reading array data.
Write Mode
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE and
CE to VIL, and OE to VIH. The “Program Command”
section has details on programming data to the device
using standard command sequences.
An erase operation can erase one sector, multiple
sectors, or the entire device. Tables 1 and 2 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to uniquely
select a sector. The “Software Command Definitions”
section has details on erasing a sector or the entire chip,
or suspending/resuming the erase operation.
When the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Auto-select Mode and Auto-select
Command sections for more information. ICC2 in the DC
Characteristics table represents the active current
specification for the write mode. The “AC Characteristics”
section contains timing specification tables and timing
diagrams for write operations.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain unchanged for over
250ns. The automatic sleep mode is independent of the
CE , WE , and OE control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and
always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
Word / Byte Mode
This pin control the I/O configuration of device. When
BYTE = VIH or Vcc ± 0.3V. The I/O configuration is x16
and the pin of D15/A-1 is bi-direction Data I/O. However,
BYTE = VIL or VSS ± 0.3V. The I/O configuration would
be x8 and The pin of DQ15/A-1 only address input pin.
You must define the function of this pin before enable this
device.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 8/47
Temporary Sector Unprotect Mode
This feature allows temporary unprotection of previously
protected sector to change data in-system. This mode is
activated by setting the ESETR pin to VID(10V-10.5V).
During this mode, all formerly protected sectors are
un-protected and can be programmed or erased by
selecting the sector addresses. Once VID is removed from
the ESETR pin, all the previously protected sectors are
protected again.
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Start
RESET = VID (Note 1)
Perform Erase or
Program Operation
RESET = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Operation Completed
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 9/47
Output Disable Mode
With the OE is at a logic high level (VIH), outputs from
the devices are disabled. This will cause the output pins
in a high impedance state
Standby Mode
When CE and ESETR are both held at VCC ± 0.3V,
the device enter CMOS Standby mode. If CE and
ESETR are held at VIH, but not within the range of
VCC ± 0.3V, the device will still be in the standby mode,
but the standby current will be larger.
If the device is deselected during auto algorithm of
erasure or programming, the device draws active
current ICC2 until the operation is completed. ICC3 in
the DC Characteristics table represents the standby
current specification.
The device requires standard access time (tCE) for
read access from either of these standby modes,
before it is ready to read data.
Sector Protect / Un-protect Mode
The hardware sector protect feature disables both
program and erase operations in any sector. The
hardware sector unprotect feature re-enables both the
program and erase operations in previously protected
sectors. Sector protect/unprotect can be implemented
via two methods.
The primary method requires VID on the ESETR pin
only, and can be implemented either in-system or via
programming equipment.
Figure 16 shows the algorithms and Figure 15 shows
the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect,
all unprotected sectors must first be protected prior to
the first sector unprotect write cycle.
The alternate method intended only for programming
equipment requires VID on address pin A9, OE , and
ESETR .
Auto-select Mode
The auto-select mode provides manufacturer and
device identification and sector protection verification,
through outputs on DQ7–DQ0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its
corresponding programming algorithm. However, the
auto-select codes can also be accessed in-system
through the command register.
When using programming equipment, this mode
requires VID (10 V to 10.5 V) on address pin A9. While
address pins A3, A2, A1, and A0 must be as shown in
Table 4.
To verify sector protection, all necessary pins have to
be set as required in Table 4, the programming
equipment may then read the corresponding identifier
code on DQ7-DQ0.
To access the auto-select codes in-system, the host
system can issue the auto-select command via the
command register, as shown in Table 5. This method
does not require VID. See “ Software Command
Definitions” for details on using the auto-select mode.
7.2 Software Command Definitions
Writing specific address and data commands or
sequences into the command register initiates the
device operations. Table 5 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE
or CE, whichever happens later. All data is latched on
the rising edge of WE or CE , whichever happens
first. Refer to the corresponding timing diagrams in
the AC Characteristics section.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 10/47
Table 5. F49L800UA/F49L800BA Software Command Definitions
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle 4th Bus
Cycle 5th Bus
Cycle 6th Bus
Cycle
Command Bus
Cycles
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset (5) 1 XXXH F0H - - - - - - - - - -
Read (4) 1 RA RD - - - - - - - - - -
Word 4 555H AAH 2AAH 55H 555H A0H PA PD
Program
Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD
Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Chip Erase
Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H
Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Sector Erase
Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H
Sector Erase
Suspend (6) 1 XXXH B0H - - - - - - - - - -
Sector Erase Resume
(7) 1 XXXH 30H - - - - - - - - - -
Auto-select See Table 6.
X = don’t care
RA = Address of memory location to be read.
RD = Data to be read at location RA.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector.
Notes:
1. Except Read command and Auto-select command, all command bus cycles are write operations.
2. The system should generate the following address patterns: 555H or 2AAH to address A10~A0 in word mode
/ AAAH or 555H to address A10~A-1 in byte mode.
3. Address bits A19–A11 are don’t cares, unless SA or PA required.
4. The Reset command is required to return to reading array data when device is in the auto-select mode, or if
DQ5 goes high (while the device is providing status data).
5. No command cycles required when reading array data.
6. The system may read and program in non-erasing sectors, or enter the auto-select mode, when in the Erase
Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
7. The Erase Resume command is valid only during the Erase Suspend mode.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 11/47
Table 6. F49L800UA/F49L800BA Auto-Select Command
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle 4th Bus
Cycle 5th Bus
Cycle 6th Bus
Cycle
Command Cycles
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
4 555H AAH 2AAH 55H 555H 90H X00H XX8CH - - - -
4 555H AAH 2AAH 55H 555H 90H X04H XX7FH - - - -
4 555H AAH 2AAH 55H 555H 90H X08H XX7FH - - - -
Word
4 555H AAH 2AAH 55H 555H 90H X0CH XX7FH - - - -
4 AAAH AAH 555H 55H AAAH 90H X00H 8CH - - - -
4 AAAH AAH 555H 55H AAAH 90H X04H 7FH - - - -
4 AAAH AAH 555H 55H AAAH 90H X08H 7FH - - - -
Manufacturer ID
Byte
4 AAAH AAH 555H 55H AAAH 90H X0CH 7FH - - - -
Word 4 555H AAH 2AAH 55H 555H 90H X01H 22DAH - - - -
Device ID, Upper boot Byte 4 AAAH AAH 555H 55H AAAH 90H X02H DAH - - - -
Word 4 555H AAH 2AAH 55H 555H 90H X01H 225BH - - - -
Device ID, Bottom boot
Byte 4 AAAH AAH 555H 55H AAAH 90H X02H 5BH - - - -
XX00H
Word 4 555H AAH 2AAH 55H 555H 90H (SA)
X02H XX01H - - - -
00H
Sector Protect Verify
Byte 4 AAAH AAH 555H 55H AAAH 90H (SA)
X04H 01H - - - -
Notes :
1. The fourth cycle of the auto-select command sequence is a read cycle.
2. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read
out data is 00H, it means the sector is still not being protected.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 12/47
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are all don’t
cares for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an auto-select command sequence.
Once in the auto-select mode, the reset command must
be written to return to reading array data (also applies
to auto-select during Erase Suspend).
If DQ5 goes high(see “DQ5: Exceeded Timing Limits”
section) during a program or erase operation, writing
the reset command returns the device to reading array
data (also applies during Erase Suspend).
Read Command
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
When the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again read
array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more
information on this mode.
The system must issue the reset command to
re-enable the device for reading array data if DQ5 goes
high, or while in the auto-select mode. See the “Reset
Command” section. See also the “Read Mode” in the
“Device Operations” section for more information. Refer
to Figure 5 for the timing diagram.
Program Command
The program command sequence programs one byte
into the device. Programming is a four-bus-cycle
operation. The program command sequence is initiated
by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verifies the programmed cell
margin.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/B
Y
. See “Write Operation Status”
section for more information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the
programming operation. The Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
“0” back to a “1”. Attempting to do so may halt the
operation and set DQ5 to “1”, or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still “0”. Only erase operations can convert a “0” to a
“1”.
Chip Erase Command
Chip erase is a six-bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation
immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure the
data integrity.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 13/47
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/B
Y
. See
“Write Operation Status” section for more information
on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. See the Erase/Program Operations
tables in “AC Characteristics” for parameters.
Sector Erase Command
Sector erase is a six-bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the
sector for an all zero data pattern prior to electrical
erase. The system is not required to provide any
controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase
commands may be written. Loading the sector erase
buffer may be done in any sequence, and the number
of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than
50 μs, otherwise the last address and command might
not be accepted, and erasure may begin.
It is recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between
additional sector erase commands can be assumed to
be less than 50 µs, the system need not monitor DQ3.
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device
to reading array data. The system must rewrite the
command sequence and any additional sector
addresses and commands.
The system can monitor DQ3 to determine if the
sector erase timer has timed out. (See the “DQ3:
Sector Erase Timer” section.) The time-out begins
from the rising edge of the final WE pulse in the
command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure the data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/B
Y
. (Refer to “Write Operation Status”
section for more information on these status bits.)
Refer to the Erase/Program Operations tables in the
“AC Characteristics” section for parameters.
Sector Erase Suspend/Resume Command
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure (The device “erase suspends” all sectors
selected for erasure.). This command is valid only
during the sector erase operation, including the 50 µs
time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded
Program algorithm. Addresses are “don’t-cares” when
writing the Erase Suspend command as shown in
Table 5.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately
terminates the time-out period and suspends the erase
operation.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is
erase-suspended. See “Write Operation Status”
section for more information on these status bits.
After an erase-suspended program operation is
complete, the system can once again read array data
within non-suspended sectors. The system can
determine the status of the program operation using
the DQ7 or DQ6 status bits, just as in the standard
program operation. See “Write Operation Status” for
more information.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 14/47
The system may also write the auto-select command
sequence when the device is in the Erase Suspend
mode. The device allows reading auto-select codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the auto-select mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation.
The system must write the Erase Resume command
(address bits are “don’t care” as shown in Table 5) to
exit the erase suspend mode and continue the sector
erase operation. Further writes of the Resume
command are ignored. Another Erase Suspend
command can be written after the device has resumed
erasing.
Auto-select Command
The auto-select command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 6 shows the address and data requirements.
This method is an alternative to that shown in Table 4,
which is intended for PROM programmers and
requires VID on address bit A9.
The auto-select command sequence is initiated by
writing two unlock cycles, followed by the auto-select
command. The device then enters the auto-select
mode, and the system may read at any address any
number of times, without initiating another command
sequence. The read cycles at address 04H, 08H, 0CH,
and 00H retrieves the ESMT manufacturer ID. A read
cycle at address 01H retrieves the device ID. A read
cycle containing a sector address (SA) and the
address 02H returns 01H if that sector is protected, or
00H if it is unprotected. Refer to Tables 1 and 2 for
valid sector addresses.
The system must write the reset command to exit the
auto-select mode and return to reading array data.
7.3 Write Operation Status
The device provides several bits to determine the
status of a write operation: RY/B
Y
, DQ7, DQ6, DQ5,
DQ3, DQ2, and. Table 7 and the following subsections
describe the functions of these bits. RY/B
Y
, DQ7, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
Table 7. Write Operation Status
Status DQ7
(Note1) DQ6 DQ5
(Note2) DQ3 DQ2 RY/ B
Y
Embedded Program Algorithm 7DQ Toggle 0 N/A No
Toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading Erase Suspended
Sector 1 No
Toggle 0 N/A Toggle 1
Reading Non-Erase
Suspended Sector Data Data Data Data Data 1
In Progress
Erase Suspended Mode
Erase Suspend Program 7DQ Toggle 0 N/A N/A 0
Embedded Program Algorithm 7DQ Toggle 1 N/A No
Toggle 0
Embedded Erase Algorithm 0 Toggle 1 1 Toggle 0
Exceeded
Time Limits
Erase Suspend Program 7DQ Toggle 1 N/A N/A 0
Notes:1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum
timing limits. See “DQ5: Exceeded Timing Limits” for more information.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 15/47
RY/ BY :
Ready/Busy
The RY/B
Y
is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/B
Y
status is valid after
the rising edge of the final WE pulse in the command
sequence. Since RY/ B
Y
is an open-drain output,
several RY/B
Y
pins can be tied together in parallel
with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 7 shows the outputs for RY/B
Y
.
DQ7: Data Polling
The DQ7 indicates to the host system whether an
Embedded Algorithm is in progress or completed, or
whether the device is in Erase Suspend mode. The
Data Polling is valid after the rising edge of the final
WE pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the true data on DQ7. The system must provide
the program address to read valid status information on
DQ7. If a program address falls within a protected
sector, Data Polling on DQ7 is active for approximately
1 µs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data Polling
on DQ7 is active for approximately 100 µs, then the
device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7~
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE ) is asserted low. Refer to Figure
21, Data Polling Timings (During Embedded
Algorithms), Figure 19 shows the Data Polling
algorithm.
DQ6:Toggle BIT I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either OE
or CE to control the read cycles. When the operation
is complete, DQ6 stops toggling.
When an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to
reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
The system can use DQ6 and DQ2 together to
determine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(i.e. the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors
are erasing or erase-suspended. Alternatively, the
system can use DQ7.
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete. Table 7 shows the
outputs for Toggle Bit I on DQ6. Figure 20 shows the
toggle bit algorithm. Figure 22 shows the toggle bit
timing diagrams. Figure 25 shows the differences
between DQ2 and DQ6 in graphical form. Refer to the
subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6,
indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II
is valid after the rising edge of the final WE or CE ,
whichever happens first, in the command sequence.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 16/47
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for
erasure. (The system may use either OE or CE to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is
erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or whether is in erase-suspended, but
cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sector
and mode information. Refer to Table 7 to compare
outputs for DQ2 and DQ6.
Figure 20 shows the toggle bit algorithm in flowchart
form. See also the DQ6: Toggle Bit I subsection. Figure
22 shows the toggle bit timing diagram. Figure 25
shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/ DQ2
Refer to Figure 20 for the following discussion.
Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described earlier.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded the specified limits(internal pulse count).
Under these conditions DQ5 will produce a "1". This
time-out condition indicates that the program or erase
cycle was not successfully completed. Data Polling and
Toggle Bit are the only operating functions of the
device under this condition.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use
the other active sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the
programming operation, it specifies that the sector
containing that byte is bad and this sector may not be
reused, however other sectors are still functional and
can be reused.
The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.
DQ3:Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire
timeout also applies after each additional sector erase
command.
When the time-out is complete, DQ3 switches from “0”
to “1.” If the time between additional sector erase
commands from the system can be assumed to be less
than 50 µs, the system need not monitor DQ3.
When the sector erase command sequence is written,
the system should read the status on DQ7 (Data
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (except Erase Suspend)
are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 7 shows the outputs for DQ3.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 17/47
7.4 More Device Operations
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware
data protection measures prevent accidental erasure or
programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device
resets. Subsequent writes are ignored until VCC is
greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on CE or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE =
VIL, CE = VIH or WE = VIH. To initiate a write cycle,
CE and WE must be a logical zero while OE is a
logical one.
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND.
Power-Up Sequence
The device powers up in the Read Mode. In addition, the
memory contents may only be altered after successful
completion of the predefined command sequences.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the
device does not accept commands on the rising edge of
WE . The internal state machine is automatically reset to
reading array data on power-up.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 18/47
8. ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . .. . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE ,
and ESETR (Note 2) …. . . .. . . . . –0.5 V to +10.5 V
All other pins (Note 1). . . . . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) .. . .. 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins
is –0.5 V. During voltage transitions, input or
I/O pins may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 1. Maximum
DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to
20 ns. See Figure 2.
2. Minimum DC input voltage on pins A9, OE , and
ESETR is -0.5 V. During voltage transitions, A9, OE ,
and ESETR may overshoot VSS to –2.0 V for periods
of up to 20 ns. See Figure 1. Maximum DC input
voltage on pin A9 is +10.5 V which may overshoot to
14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 1. Maximum Negative Overshoot Waveform
Figure 2. Maximum Positive Overshoot Waveform
+0.8V
-0.5V
-2.0V
20ns
20ns
20ns
Vcc
+2.0V
Vcc
+0.5V
2.0V
20ns
20ns
20ns
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 19/47
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . -40°C to +85°C
VCC Supply Voltages VCC for all devices . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Table 8. Capacitance TA = 25°C , f = 1.0 MHz
Symbol Description Conditions Min. Typ. Max. Unit
CIN1 Input Capacitance VIN = 0V
8 pF
CIN2 Control Pin Capacitance VIN = 0V
12 pF
COUT Output Capacitance VOUT = 0V
12 pF
9. DC CHARACTERISTICS
Table 9. DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 3.6V
Symbol Description Conditions Min. Typ. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC, VCC = VCC max. ±1 uA
ILIT A9 Input Leakage Current VCC = VCC max; A9=10.5V 35 uA
ILO Output Leakage Current VOUT = VSS or VCC, VCC = VCC max ±1 uA
@5MHz 9 25 mA
CE= VIL, OE = VIH
( Byte Mode ) @1MHz 2 5 mA
@5MHz 9 40 mA
ICC1 V
CC Active Read Current
CE= VIL, OE = VIH
( Word Mode ) @1MHz 2 5 mA
ICC2 V
CC Active write Current CE= VIL, OE = VIH 20 50 mA
ICC3 V
CC Standby Current CE; ESETR = VCC ± 0.3V 25 100 uA
ICC4 VCC Standby Current
During Reset ESETR = VSS ± 0.3V 25 100 uA
ICC5 Automatic sleep mode VIH = VCC ± 0.3V; VIL = VSS ± 0.3V 25 100 uA
VIL Input Low Voltage(Note 1) -0.5 0.8 V
VIH Input High Voltage 0.7x VCC V
CC + 0.3 V
VID
Voltage for Auto-Select
and Temporary Sector
Unprotect
VCC =3.3V 10 10.5 V
VOL Output Low Voltage IOL = 4.0mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage(TTL) IOH = -2mA, VCC = VCC min 0.7x VCC
VOH2 Output High Voltage IOH = -100uA, VCC min VCC -0.4
VLKO Low VCC Lock-out Voltage 2.3 2.5 V
Notes :
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
V
IL min. = -2.0V for pulse width is equal to or less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If V
IH is over the specified maximum value, read operation cannot be guaranteed.
3. Automatic sleep mode enable the low power mode when addresses remain stable for 250 ns
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 20/47
10. AC CHARACTERISTICS
TEST CONDITIONS
Figure 3. Test Setup
Figure 4. Input Waveforms and Measurement Levels
Input
3.0V
0V
1.5V
Output
1.5V
Test Points
AC TESTING : Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0"
Input pulse rise and fall times are < 5ns.
6.2K DIODES = IN3064
OR EQUIVALENT
+3.3V
2.7K
CL = 100pF Including jig capacitance
CL = 30pF for F49L800U/BA
CL
DEVICE UNDER
TEST
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 21/47
10.1 Read Operation
TA = -40°C to 85°C, VCC = 2.7V~3.6V
Table 10. Read Operations
-70 -90
Symbol Description Conditions Min. Max. Min. Max.
Unit
tRC Read Cycle Time (Note 1) 70 90 ns
tACC Address to Output Delay CE=OE = VIL 70 90 ns
tCE CE to Output Delay OE = VIL 70 90 ns
tOE OE to Output Delay CE= VIL 30 35 ns
tDF OE High to Output Float
(Note1) CE= VIL 25 30 ns
Output Enable Read 0 0 ns
tOEH
Hold Time Toggle and
Data Polling 10 10 ns
tOH Address to Output hold CE =OE = VIL 0 0 ns
Notes :
1. Not 100% tested.
2. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer
driven.
Figure 5. Read Timing Waveform
tRC
Addresses Stable
Output Valid
Address
High-Z
CE
WE
0V
RY/BY
RESET
OE
Outputs
High-Z
tACC
tOEH
tOE
tOH
tDF
tCE
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 22/47
10.2 Program/Erase Operation
Table 11. WE Controlled Program/Erase Operations(TA = -40°C to 85°C, VCC = 2.7V~3.6V)
-70 -90
Symbol Description
Min. Max. Min. Max.
Unit
tWC Write Cycle Time (Note 1) 70 90
ns
tAS Address Setup Time 0 0 ns
tAH Address Hold Time 45 45 ns
tDS Data Setup Time 35 35 ns
tDH Data Hold Time 0 0 ns
tOES Output Enable Setup Time 0 0 ns
tGHWL Read Recovery Time Before
Write ( OE High to WE low) 0 0 ns
tCS CE Setup Time 0 0 ns
tCH CE Hold Time 0 0 ns
tWP Write Pulse Width 35 35 ns
tWPH Write Pulse Width High 30 30 ns
tWHWH1 Programming Operation (Note 2)
(Byte program time) 9(typ.) 9(typ.) us
tWHWH2 Sector Erase Operation (Note 2) 0.7(typ.) 0.7(typ.) sec
tVCS V
CC Setup Time (Note 1) 50 50 us
tRB Recovery Time from RY/B
Y
0 0 ns
tbusy Program/Erase Valid to RY/B
Y
Delay 90 90 ns
Notes :
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 23/47
Table 12. CE Controlled Program/Erase Operations(TA = -40°C to 85°C, VCC =2.7V~3.6V)
-70 -90
Symbol Description
Min. Max. Min. Max. Unit
tWC Write Cycle Time (Note 1) 70 90 ns
tAS Address Setup Time 0 0 ns
tAH Address Hold Time 45 45 ns
tDS Data Setup Time 35 35 ns
tDH Data Hold Time 0 0 ns
tOES Output Enable Setup Time 0 0 ns
tGHEL Read Recovery Time Before Write 0 0 ns
tWS WE Setup Time 0 0 ns
tWH WE Hold Time 0 0 ns
tCP CE Pulse Width 35 35 ns
tCPH CE Pulse Width High 30 30 ns
tWHWH1 Programming Operation(note2) 9(typ.) 9(typ.) us
tWHWH2 Sector Erase Operation (note2) 0.7(typ.) 0.7(typ.) sec
Notes :
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 24/47
Figure 6. Write Command Timing Waveform
OE
Data
VIH
VIL
ADD Valid
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tAH
tAS
tWP tWPH
VCC 3V
Address
WE
CE
tCWC
tCS tCH
tDH
tDS
DIN
tOES
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 25/47
Figure 7. Embedded Programming Timing Waveform
Notes :
1. PA = Program Address, PD = Program Data, DOUT is the true data the program address.
CE
WE
Address
OE
555h PA PA PA
tWC tAS
Read Status Data (last two cycle)
tAH
tCH
tGHWL
tWP
tCS tWPH
A0h
tDS tDH
PD Status DOUT
tWHWH1
Data
tVCS
VCC
Program Command Sequence (last two cycle)
RY/BY
tRB
tBUSY
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 26/47
Figure 8. Embedded Programming Algorithm Flowchart
Start
Write Data AAH Address 555H
Verify Work OK?
Embedded Program Completed
Data Poll
from system
Yes
Last address?
Yes
No
Write Data 55H Address 2AAH
Write Data A0H Address 555H
No
Increment
address
Write Program Data/Address
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 27/47
Figure 9. CE Controlled Program Timing Waveform
Notes :
1. PA = Program Address, PD = Program Data, DOUT = Data Out , DQ7 = complement of data written to device
2. Figure indicates the last two bus cycles of the command sequence..
Address
WE
CE
OE
555 for program
2AA for erase
Data Polling
tAStWC
PA
Data
RESET
RY/BY
PA for program
SA for sector erase
555 for chip erase
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
tWH tAH
tDS
tDH
tGHEL
tCP
tCPH tBUSY
tWS
DOUT
DQ7
tWHWH1 or 2
tRH
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 28/47
Figure 10. Embedded Chip Erase Timing Waveform
Notes :
SA = Sector Address (for Sector Erase, VA = Valid Address for reading status data
(see "Write Operation Status")
Address
CE
WE
OE
2AAh 555h VA VA
tWC tAS
Erase Command Sequence(last two cycle) Read Status Data
tAH
tCH
tGHWL
tWP
tCS tWPH
55h
tDS tDH
10h In
Progress Complete
tWHWH2
Data
tRB
tBUSY
RY/BY
tVCS
VCC
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 29/47
Figure 11. Embedded Chip Erase Algorithm Flowchart
Start
Write Data AAH Address 555H
Embedded Chip Erease Completed
Data = FFh?
Yes
No
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data Poll from System
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 30/47
Figure 12. Embedded Sector Erase Timing Waveform
Notes :
SA = Sector Address (for Sector Erase, VA = Valid Address for reading status data
(see "Write Operation Status")
Address
CE
WE
OE
2AAh SA VA VA
tWC tAS
Erase Command Sequence(last two cycle) Read Status Data
tAH
tCH
tGHWL
tWP
tCS tWPH
55h
tDS tDH
30h In
Progress Complete
tWHWH2
Data
tRB
tBUSY
RY/BY
tVCS
VCC
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 31/47
Figure 13. Embedded Sector Erase Algorithm Flowchart
Start
Write Data AAH Address 555H
Embedded Sector Erease Completed
Last Sector
to Erase
Yes
No
WriteData55HAddress2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Address SA
Data Poll from System
Data = FFH?
No
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 32/47
Figure 14. Erase Suspend/Erase Resume Flowchart
Start
Write Data B0H
Toggle Bit checking Q6
not toggled
Yes
ERASE RESUME
No ERASE SUSPEND
Read Array or
Program
Another
Erase Suspend?
No
No
Yes
Reading or
Programming End
Yes
Write Data 30H
Continue Erase
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 33/47
Figure 15. In-System Sector Protect/Unprotect Timing Waveform (RESE
T
Control)
Notes :
When sector protect, A6=0, A1=1, A0=0.
When sector unprotect, A6=1, A1=1, A0=0.
CE
RESET
SA,A6
A1,A0
Data
1us
Sector Protect Sector Unprotect
Valid* Valid* Valid*
60h 60h 40h Status
Verify
WE
Sector Protect = 150us
Sector Unprotect = 15ms
OE
VID
VIH
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 34/47
Figure 16. In-System Sector Protect/Unprotect Algorithm (RESE
T
= VID)
Start Start
PLSCNT = 1 PLSCNT = 1
Set up first
sector address
Sector Unprotect :
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 15 ms?
First Write
Cycle = 60h?
All sectors
protected?
Data = 00h?
Last sector
verified?
No
RESET = VID
No
No
Yes
Yes
No
No
No
Yes
Yes
First Write
Cycle = 60h? Temporary Sector
Unprotect Mode
Set up
next sector
address
Device failed
Device failed
Yes
Wait 1 s?
Temporary Sector
Unprotect Mode
μ
Data = 01h?
Yes
RESET = VID
PLSCNT
= 1000?
Wait 1 s?
Increment
PLSCNT
μ
Set up sector
address
Sector Protect :
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Verify Sector
Protect : Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Wait 150 s?
μ
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
PLSCNT = 25?
Increment
PLSCNT
Protect another
sector?
No
No
No
Remove VID
from RESET
Remove VID
from RESET
Write reset
command
Write reset
command
Sector Protect
complete
Sector Protect
complete
Sector Protect
Algorithm Sector Unprotect
Algorithm
Yes
Reset
PLSCNT = 1
Protect all sector :
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Yes
Yes
Read from
sector address
with A6 = 1,
A1 = 1, A0 =0
Verify Sector
Unprotect : Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 =0
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 35/47
Figure 17. Sector Protect Timing Waveform (A9, OE Control)
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 36/47
Figure 18. Sector Protection Algorithm (A9, OE Control)
Start
Set up sector address
Data = 01H?
Sector Protection
Complete
Activate WE Pluse
Remove VID from A9
Write reset command
Device Failed Protect Another
Sector?
Yes
Yes
No
No
PLSCNT = 1
OE = VID, A9 = VID, CE = VIL
A6 = VIL
Time out 150us
Set WE = VIH , CE = OE = VIL
A9 should remain VID
Read from Sector
Address = SA, A0=1, A1 = 1
PLSCNT = 32?
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 37/47
WRITE OPERATION STATUS
Figure 19. Data Polling Algorithm
Notes :
1. VA =Valid address for programming.
2. DQ7 should be re-checked even DQ5 = "1" because
DQ7 may change simultaneously with DQ5.
Start
Read DQ7~DQ0
Add. = VA(1)
DQ7 = Data?
FAIL Pass
DQ5 = 1?
No
Read DQ7~DQ0
Add. = VA
Yes
Yes
No
DQ7 = Data? Yes
No
(2)
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 38/47
Figure 20. Toggle Bit Algorithm
Note :
1. Read toggle bit twice to determine whether or not it is toggle.
2. Recheck toggle bit because it may stop toggling as DQ5 change to "1".
Start
Read DQ7 ~ DQ0
Toggle Bit = DQ6
Toggle?
Program / Erase operation
Not complete, write
reset command
Program / Erase
operation complete
DQ5 = 1?
No
Read DQ7~DQ0 Twice
Yes
No
Toggle bit DQ6
= Toggle?
No
Yes
Yes
Read DQ7 ~ DQ0 (Note 1)
(Note 1,2)
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 39/47
Figure 21. Data Polling Timings (During Embedded Algorithms)
Notes :
VA = Valid Address. Figure shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
WE
Address
CE
OE
tACC
DQ7
RY/BY
tCE
VA VA
tRC
tOE
tOEH
tCH
tDF
tOH
Complement Complement True Vaild Dat a
High-Z
Status Data Status Data True Vaild Data
High-Z
DQ0~DQ6
tBUSY
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 40/47
Figure 22. Toggle Bit Timing Waveforms (During Embedded Algorithms)
Notes :
VA = Valid Address; not required for DQ6. Figure shows first status cycle after command sequence, last status
read cycle, and array data read cycle.
Address
CE
OE
WE
tACC
DQ6/DQ2
RY/BY
tCE
VA VA
tRC
tOE
tOEH
tCH
tDF
tOH
Vaild Status
tBUSY
VA
Vaild Status
VA
High-Z
(first read) (second read)
Vaild Data
(stops tog gling )
Vaild Data
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 41/47
10.3 Hardware Reset Operation
Table 13. AC CHARACTERISTICS
Symbol Description All Speed Options Unit
TREADY1 ESETR Pin Low (During Embedded Algorithms)
to Read or Write (See Note) Max 20 us
TREADY2 ESETR Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
TRP ESETR Pulse Width (During Embedded
Algorithms) Min 500 ns
TRH ESETR High Time Before Read(See Note) Min 50 ns
TRB RY/B
Y
Recovery Time(to CE, OE go low) Min 0 ns
Notes :
Not 100% tested
Figure 23. RESET Timing Waveform
RY/BY
CE, OE
RESET
RY/BY
CE, OE
RESET
tRP
tReady2
tRH
tRP
tRB
tReady1
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 42/47
10.4 TEMPORARY SECTOR UNPROTECT Operation
Table 14. Temporary Sector Unprotect
Symbol Description All Speed Options Unit
TVIDR V
ID Rise and Fall Time (See Note) Min 500 ns
TRSP ESETR Setup Time for Temporary Sector
Unprotect Min 4 us
Notes:
Not 100% tested
Figure 24. Temporary Sector Unprotect Timing Diagram
Figure 25. DQ6 vs DQ2 for Erase and Erase Suspend Operations
Notes :
The system can use OE or CE to toggle DQ2 / DQ6, DQ2 toggles only when read at an address within an
erase-suspended.
WE
RY/BY
CE
RE SE T
tVIDR
tRS P
0orVCC
Pr ogr am or Er ase C om ma nd Se quen ce
tVIDR
0orVCC
10V
WE
DQ6
DQ2
Enter Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase
Suspend
Read
Erase
Resume
Erase Erase
Complete
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 43/47
Figure 26. Temporary Sector Unprotect Algorithm
Notes :
1. All protected status are temporary unprotect.
V
ID = 10V~10.5V
2. All previously protected sectors are protected again.
Start
RESET = VID (Note 1)
RESET = VIH
Program Erase or Program Operation
Temporary Sector Unprotect Completed (Note 2)
Operation Completed
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 44/47
Figure 27. ID Code Read Timing Waveform
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 45/47
11. ERASE AND PROGRAMMING PERFORMANCE
Table 15. Erase And Programming Performance (Note.1)
Limits
Parameter
Typ.(2) Max.(3) Unit
Sector Erase Time 0.7 15 Sec
Chip Erase Time 14 Sec
Byte Programming Time 9 300 Us
Word Programming Time 11 360 Us
Byte Mode 9 27
Sec
Chip Programming Time
Word Mode 5.8 17
Sec
Erase/Program Cycles (1) 100,000 - Cycles
Data Retention 20 -
Years
Notes:
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C, 3.3V.
3.Maximum values measured at 85°C, 2.7V.
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 46/47
12. PACKAGE DIMENSION
48-LEAD TSOP(I) ( 12x20 mm )
Dimension in mm Dimension in inch Dimension in mm Dimension in inch
Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max
A ------- ------- 1.20 ------- ------- 0.047 D 20.00 BSC 0.787 BSC
A 1 0.05 ------- 0.15 0.006 ------- 0.002 D 1 18.40 BSC 0.724 BSC
A 2 0.95 1.00 1.05 0.037 0.039 0.041 E 12.00 BSC 0.472 BSC
b 0.17 0.22 0.27 0.007 0.009 0.011 e 0.50 BSC 0.020 BSC
b1 0.17 0.20 0.23 0.007 0.008 0.009 L 0.50 0.60 0.70 0.020 0.024 0.028
c 0.10 ------- 0.21 0.004 ------- 0.008 θ 0
O ------- 8O 0
O ------- 8O
c1 0.10 ------- 0.16 0.004 ------- 0.006
ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008
Revision: 1.2 47/47
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form
or by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of
failure. To minimize risks associated with customer's application,
adequate design and operating safeguards against injury, damage, or
loss from such failure, should be provided by the customer when
making application designs.
ESMT 's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
