FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
April 2011
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6
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FIN224AC
22-Bit Bi-Directional Serializer/Deserializer
Features
• Industry smallest 22-bit Serializer/Deserializer pair
• Low power for minimum impact on battery life
– Multiple power-down modes
• 100nA in standby mode, 5mA typical operating
conditions
• Highly rolled LVCMOS edge rate option to meet
regulatory requirements
• Cable reduction: 25:4 or greater
• Differential signaling:
––90dBm EMI when using CTL in lab conditions
–Minimized shielding
–Minimized EMI filter
–Minimum susceptibility to external interference
• Up to 22 bits in either direction
• Voltage translation from 1.65V to 3.6V
• High ESD protection: > 15kV HBM
• Parallel I/O power supply (V
DDP
) range, 1.65V - 3.6V
• Can support Microcontroller or RGB pixel interface
Applications
• Image sensors
• Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
Description
The FIN224AC µSerDes™ is a low-power serializer/
deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bidirectional operation, using half duplex for multiple
sources, it is possible to reach signal reduction close to
10:1. Through the use of differential signaling, shielding
and EMI filters can also be minimized, further reducing
the cost of serialization. The differential signaling is also
important for providing a noise-insensitive signal that can
withstand radio and electrical noise sources. Major
reduction in power consumption allows minimal impact
on battery life in ultra-portable applications. It is possible
to use a single PLL for most applications including bi-
directional operation.
FIN224AC to FIN24AC Comparison
• Up to 20% power reduction
• Double wide CKP pulse on FIN224AC, Mode 3
• Rolled edge rate for deserializer outputs on
FIN224AC, for single display applications
• Same voltage range
• Same pinout and package
Ordering Information
µSerDes
TM
is a trademark of Fairchild Semiconductor Corporation.
Order
Number
Operating
Temperature
Range
Package Description Packing
Method
FIN224ACGFX -30 to +70°C 42-Ball, Ultra-Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide (Slow LVCMOS Edge Rate) Tape and Reel
FIN224ACMLX -30 to +70°C 40-Terminal, Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 6mm Square (Slow LVCMOS Edge Rate) Tape and Reel
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 2
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Basic Concept
Figure 1. Conceptual Diagram
Functional Block Diagram
Figure 2. Block Diagram
FIN224AC
Serializer
FIN224AC
Deserializer
CTL
4
LVCMOS
22
LVCMOS
22
CKREF CKS0+
CKSI+
+
-
+
-
+
-
+
-
CKSI-
cksint
cksint
oe
oe
DSO+/DSI-
Serializer
Control
WORD CK
Generator
Freq
Control
Direction
Control
Power Down
Control
Control Logic
0
I
Serializer
Deserializer
Deserializer
Control
PLL
Register
Register
Register
DSO-/DSI+
DIRO
CKS0-
CKP
S1
S2
DIRI
STROBE
DP[21:22]
DP[23:24]
DP[1:20]
100
Termination
100 Gated
Termination
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 3
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Terminal Description
Note
:
1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the
other device, the serial connections properly align without the need for any traces or cable signals to cross. Other
layout orientation may require that traces or cables cross.
Terminal
Name I/O Type Number of
Terminals Description of Signals
DP[1:20] I/O 20 LVCMOS parallel I/O, Direction controlled by DIRI pin
DP[21:22] I 2 LVCMOS parallel unidirectional inputs
DP[23:24] O 2 LVCMOS unidirectional parallel outputs
CKREF IN 1 LVCMOS clock input and PLL reference
STROBE IN 1 LVCMOS strobe signal for latching data into the serializer
CKP OUT 1 LVCMOS word clock output
DSO+ / DSI-
DSO- / DSI+ DIFF-I/O 2
CTL differential serial I/O data signals
(1.)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)-: Negative signal of DSO(I) pair
CKSI+
CKSI- DIFF-IN 2
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI-: Negative signal of CKSI pair
CKSO+
CKSO- DIFF-OUT 2
CTL differential serializer output bit clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO-: Negative signal of CKSO pair
S1 IN 1 LVCMOS mode selection terminals used to select frequency range for
the reflect, CKREF
S2 IN 1
DIRI IN 1
LVCMOS control input used to control direction of data flow:
DIRI = “1” Serializer
DIRI = “0” Deserializer
DIRO OUT 1 LVCMOS control output inversion of DIRI
V
DDP
Supply 1 Power supply for parallel I/O and translation circuitry
V
DDS
Supply 1 Power supply for core and serial I/O
V
DDA
Supply 1 Power supply for analog PLL circuitry
GND Supply 2 For ground signals (2 for µBGA, 1 for MLP)
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 4
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Connection Diagrams
Figure 3. Terminal Assignments for MLP (Top View)
Figure 4. Terminal Assignments for µBGA (Top View)
1
2
3
4
5
6
7
8
9
10
DP[9]
DP[10]
DP[11]
DP[12]
VDDP
CKP
DP[13]
DP[14]
DP[15]
DP[16]
30
29
28
27
26
25
24
23
22
21
DIRO
CKSO+
CKSO-
DSO+
DSO-
CKSI-
CKSI+
DIRI
S2
VDDS
11
12
13
14
15
16
17
18
19
20
DP[17]
DP[18]
DP[19]
DP[20]
DP[21]
DP[22]
DP[23]
DP[24]
S1
VDDA
40
39
38
37
36
35
34
33
32
31
DP[8]
DP[7]
DP[6]
DP[5]
DP[4]
DP[3]
DP[2]
DP[1]
STROBE
CKREF
42 MBGA Package
3.5mm x 4.5mm
(.5mm Pitcth)
(Top View)
1 2 3 4 5 6
A
B
C
D
E
F
G
Pin Assignments
1 2 3 4 5 6
A DP[9] DP[7] DP[5] DP[3] DP[1] CKREF
B DP[11] DP[10] DP[6] DP[2] STROBE DIRO
C CKP DP[12] DP[8] DP[4] CKSO+ CKSO-
D DP[13] DP[14] VDDP GND DSO-/DSI+ DSO+/DSI-
E DP[15] DP[16] GND VDDS CKSI+ CKSI-
F DP[17] DP[18] DP[21] VDDA S2 DIRI
G DP[19] DP[20] DP[22] DP[23] DP[24] S1
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 5
Control Logic Circuitry
The FIN224AC has the ability to be used as a 22-bit seri-
alizer or a 22-bit deserializer. Pins S1 and S2 must be
set to accommodate the clock reference input frequency
range of the serializer. Table 1 shows the pin program-
ming of these options based on the S1 and S2 control
pins. The DIRI pin controls whether the device is a serial-
izer or a deserializer. When DIRI is asserted LOW, the
device is configured as a deserializer. When the DIRI pin
is asserted HIGH, the device is configured as a serial-
izer. Changing the state on the DIRI signal reverses the
direction of the I/O signals and generate the opposite
state signal on DIRO. For unidirectional operation the
DIRI pin should be hardwired to the HIGH or LOW state
and the DIRO pin should be left floating. For bi-direc-
tional operation, the DIRI of the master device is driven
by the system and the DIRO signal of the master is used
to drive the DIRI of the slave device.
Serializer/Deserializer with Dedicated I/O Variation
The serialization and deserialization circuitry is set up for
24 bits. Because of the dedicated inputs and outputs,
only 22 bits of data are serialized or deserialized.
DP[21:22] inputs to the serializer are transmitted to
DP[23:24] outputs on the deserializer.
Turn-Around Functionality
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken by the system designer to ensure that no
contention occurs between the deserializer outputs and
the other devices on this port. Optimally the peripheral
device driving the serializer should be put into a HIGH-
impedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned around into a
deserializer and the values are overwritten.
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differ-
ential input buffers are shut off, differential output buffers
are placed into a HIGH-impedance state, LVCMOS out-
puts are placed into a HIGH-impedance state, and LVC-
MOS inputs are driven to a valid level internally.
Additionally all internal circuitry is reset. The loss of
CKREF state is also enabled to ensure that the PLL only
powers-up if there is a valid CKREF signal.
In a typical application mode, signals of the device do not
change states other than between the desired frequency
range and the power-down mode. This allows for sys-
tem-level power-down functionality to be implemented
via a single wire for a SerDes pair. The S1 and S2 selec-
tion signals that have their operating mode driven to a
“logic 0” should be hardwired to GND. The S1 and S2
signals that have their operating mode driven to a “logic
1” should be connected to a system-level power-down or
reset signal.
Table 1. Control Logic Circuitry
Mode
Number S2 S1 DIRI Description
0 0 0 x Power-Down Mode
1
0 1 1 22-Bit Serializer 2MHz to 5MHz CKREF
0 1 0 22-Bit Deserializer
2
1 0 1 22-Bit Serializer 5MHz to 15MHz CKREF
1 0 0 22-Bit Deserializer
3
1 1 1 22-Bit Serializer 10MHz to 26MHz CKREF (Divide by 2 Serial Data)
1 1 0 22-Bit Deserializer
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 6
Serializer Operation Mode
The serializer configurations are described in the follow-
ing sections. The basic serialization circuitry works
essentially identically in these modes, but the actual data
and clock streams differ depending on if CKREF is the
same as the STROBE signal or not. When it is stated
that CKREF does not equal STROBE, each signal is dis-
tinct and CKREF must be running at a frequency high
enough to avoid any loss of data condition. CKREF must
never be a lower frequency than STROBE.
Serializer Operation: MODE 1 or MODE 2,
DIRI = 1, CKREF = STROBE
The PLL must receive a stable CKREF signal to achieve
lock prior to any valid data being sent. The CKREF sig-
nal can be used as the data STROBE signal provided
that data can be ignored during the PLL lock phase.
Once the PLL is stable and locked, the device can begin
to capture and serialize data. Data is captured on the ris-
ing edge of the STROBE signal and serialized. When
operating in serializer mode, the internal deserializer cir-
cuitry is disabled; including the serial clock, serial data
input buffers, bi-directional parallel outputs, and CKP
word clock. The CKP word clock is driven HIGH.
Serializer Operation: DIRI = 1, CKREF Does Not
= STROBE
If the same signal is not used for CKREF and STROBE,
the CKREF signal must be run at a higher frequency
than the STROBE rate to serialize the data correctly. The
actual serial transfer rate remains at 13 times the
CKREF frequency. A data bit value of zero is sent when
no valid data is present in the serial bit stream. The oper-
ation of the serializer otherwise remains the same.
The exact frequency that the reference clock needs to
run at depends upon the stability of the CKREF and
STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the minimun
frequency of the spread spectrum clock should be used
in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly, if the STROBE signal has
significant cycle-to-cycle variation, the maximum cycle-
to-cycle time needs to be factored into the selection of
the CKREF frequency.
Serializer Operation: MODE 3 (S1 = S2 =1),
DIRI =1. CKREF Divide by 2 Mode.
When operating in mode 3, the effective serial speed is
divided by two. This mode has been implemented to
accommodate cases where the reference clock fre-
quency is high compared to the actual strobe frequency.
The actual strobe frequency must be less than or equal
to 50% of the CKREF frequency for this mode to work
properly. This mode, in all other ways, operates the
same as described in the section where CKREF does
not equal STROBE.
Serializer Operation: DIRI = 1, No CKREF
A third method of serialization can be acheived by pro-
viding a free-running bit clock on the CKSI signal. This
mode is enabled by grounding the CKREF signal and
driving the DIRI signal HIGH. At power-up, the device is
configured to accept a serialization clock from CKSI. If a
CKREF is received, this device enables the CKREF seri-
alization mode. The device remains in this mode even if
CKREF is stopped. To re-enable this mode, the device
must be powered down and then powered back up with a
“logic 0” on CKREF.
Deserializer Operation Mode
The operation of the deserializer is dependent on the
data received on the DSI data signal pair and the CKSI
clock signal pair. The following sections describe the
operation of the deserializer under distinct serializer
source conditions. References to the CKREF and
STROBE signals refer to the signals associated with the
serializer device generating the serial data and clock sig-
nals that are inputs to the deserializer. When operating in
deserializer mode, the internal serializer circuitry is dis-
abled, including the parallel data input buffers. If there is
a CKREF signal provided, the CKSO serial clock contin-
ues to transmit bit clocks. Upon power-up (S1 or S2 = 1),
deserializer output data pins are driven LOW until valid
data is passed through the deserializer.
Deserializer Operation: DIRI = 0 (Serializer
Source: CKREF = STROBE)
When the DIRI signal is asserted LOW, the device is
configured as a deserializer. Data is captured on the
serial port and deserialized through use of the bit clock
sent with the data.
Deserializer Operation: DIRI = 0 (Serializer
Source: CKREF Does Not = STROBE)
The logical operation of the deserializer remains the
same if the CKREF is equal in frequency to the STROBE
or at a higher frequency than the STROBE. The actual
serial data stream presented to the deserializer is differ-
ent because it has non-valid data bits sent between
words. The duty cycle of CKP varies based on the ratio
of the frequency of the CKREF signal to the STROBE
signal. The frequency of the CKP signal is equal to the
STROBE frequency. In modes 1 and 2, the CKP LOW
time equals half of the CKREF period of the serializer. In
mode 3, the CKP LOW is equal to the CKREF period.
The CKP HIGH time is approximately equal to the
STROBE period, minus the CKP LOW time.
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 7
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half V
DD
. The input buffers are only oper-
ational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source / sink current of approximately 0.5mA at 1.8V.
The outputs are active when the DIRI signal and either
S1 or S2 is asserted HIGH. When the DIRI signal and
either S1 or S2 is asserted LOW, the bi-directional LVC-
MOS I/Os is in a HIGH-Z state. Under purely capacitive
load conditions, the output swings between GND and
V
DDP
. When S1 or S2 initially transitions HIGH, the initial
state of the deserializer LVCMOS outputs is zero.
Unused LVCMOS input buffers must be either tied off to
a valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused LVC-
MOS output should be left floating. Unused bi-directional
pins should be connected to GND through a high-value
resistor. If a FIN224AC device is configured as an unidi-
rectional serializer, unused data I/O can be treated as
unused inputs. If the FIN224AC is hardwired as a deseri-
alizer,
unused data I/O can be treated as unused outputs.
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 8
Application Mode Diagrams
Figure 5. FIN224AC RGB
Figure 6. FIN224AC Microcontroller
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex
cable. The following best practices should be used when developing the flex cabling or Flex PCB:
Keep all four differential wires the same length.
Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.
Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
Do not place test points on differential serial wires.
Use differential serial wires a minimum of 2cm away from the antenna.
2.8V
2.8V
VDDP
2.8V
1.8V
LCD_VSYNC_S
LCD14_M
LCD10_M
LCD2_M
LCD6_M
LCD8_M
LCD12_M
LCD4_M
LCD1_M
LCD15_M
LCD5_M
LCD11_M
LCD3_M
LCD9_M
LCD7_M
LCD13_M
PIXCLK_M
LCD_HSYNC_M
LCD_VSYNC_M
LCD17_M
LCD0_S
LCD1_S
LCD0_M
LCD2_S
LCD3_S
LCD4_S
LCD5_S
PIXCLK_S
GPIO_MODE
LCD6_S
LCD7_S
LCD8_S
LCD9_S
LCD10_S
LCD11_S
LCD12_S
LCD13_S
LCD14_S
LCD15_S
LCD_HSYNC_S
LCD16_S
LCD17_S
LCD16_M
LCD_ENABLE_ M
LCD_ENABLE_ S
SerDes Deserializer
LCD
Controller
Out
Assumptions:
1) 18-bit Uni directional RGB Applicat ion
2) Mode 3 Operation (10 Mhz to 20Mhz CKREF)
LCD
Display
In
3) VDDP = (1.65V to 3.6V)
Se r Des Serializer
C11
2.2uF
C11
2.2µF 1nF
C10
1nF
C10
TP5TP5
.01uF
C3
.01µF
C3
1nF
C6
1nF
C6
U22 FIN224ACU22 FIN224AC
DP9 A1
DP7 A2
DP5 A3
DP3 A4
DP1 A5
CKREF
A6
DP11B1
DP10B2
DP6 B3
DP2 B4
STROBE
B5
DIRO
B6
CKP C1
DP12C2
DP8 C3
DP4 C4
CKSO+
C5 CKSO-
C6
DP13D1
DP14D2
VDDP
D3
GN D
D4
DSO-/DSI +
D5
DSO+/DSI -
D6
CKSI-
E6
CKSI+
E5
VDDS
E4
GN D
E3
DP16E2
DP15E1
DIRI
F6 S2
F5
VDDA
F4
DP21F3
DP18F2
DP17F1
S1
J6
DP24J5
DP23J4
DP22J3
DP20J2
DP19J1
TP6TP6 U20 FIN224ACU20 FIN224AC
DP9
A1
DP7
A2
DP5
A3
DP3
A4
DP1
A5
CKREF
A6
DP11
B1
DP10
B2
DP6
B3
DP2
B4
STROBE
B5
DIROB6
CKP C1
DP12
C2
DP8
C3
DP4
C4
CKSO+ C5
CKSO- C6
DP13
D1 DP14
D2
VDDP D3
GN D
D4
DSO-/DSI + D5
DSO+/DSI - D6
CKSI- E6
CKSI+ E5
VDDS E4
GN D
E3
DP16
E2
DP15
E1
DIRI
F6
S2
F5
VDDA F4
DP21
F3
DP18
F2
DP17
F1
S1
J6
DP24
J5
DP23
J4
DP22
J3
DP20
J2
DP19
J1
.01uF
C12
.01µF
C12
2.8V
1.8V
VDDP
2.8V
2.8V
LCD14_M
LCD10_M
LCD2_M
LCD6_M
LCD8_M
LCD12_M
LCD4_M
LCD1_M
LCD15_M
LCD5_M
LCD11_M
LCD9_M
LCD7_M
LCD13_M
REFCLK
LCD3_M
GPIO_MODE
LCD_/WRITE_ENABLE_M
LCD16_M
LCD17_M
LCD0_SLCD0_M
LCD_ADDRESS_M
LCD_/CS_M
LCD1_S
LCD2_S
LCD3_S
LCD4_S
LCD5_S
LCD6_S
LCD7_S
LCD8_S
LCD9_S
LCD10_S
LCD11_S
LCD12_S
LCD13_S
LCD14_S
LCD15_S
LCD16_S
LCD17_S
LCD_ADDRESS_S
LCD_/CS_S
LCD_/WRITE_ENABLE_S
SerDes Serializer
LCD
Controller
Out LCD
Display
In
Assumptions:
1) 18-bit Unidirectional Controller Application
2) Mode 3 Operation (10 Mhz to 20Mhz CKREF)
SerDes Deserializer
3) VDDP= (1.65V to 3.6V)
4) REFCLK is a continously running clock with a frequency
greater than /WRITE_ENABLE.
U23 FIN224ACU23 FIN224AC
DP9 A1
DP7 A2
DP5 A3
DP3 A4
DP1 A5
CKREF
A6
DP11 B1
DP10 B2
DP6 B3
DP2 B4
STROBE
B5
DIRO
B6
CKP C1
DP12 C2
DP8 C3
DP4 C4
CKSO+
C5 CKSO-
C6
DP13 D1
DP14 D2
VDDP
D3
GN D
D4
DSO-/DSI+
D5
DSO+/DSI-
D6
CKSI-
E6
CKSI+
E5
VDDS
E4
GN D
E3
DP16 E2
DP15 E1
DIRI
F6 S2
F5
VDDA
F4
DP21 F3
DP18 F2
DP17 F1
S1
J6
DP24 J5
DP23 J4
DP22 J3
DP20 J2
DP19 J1
TP2TP2
1nF
C7
1nF
C7
1nF
C5
1nF
C5
.01uF
C9
.01F
C9
TP1TP1
U21 FIN224ACU21 FIN224AC
DP9
A1
DP7
A2
DP5
A3
DP3
A4
DP1
A5
CKREF
A6
DP11
B1
DP10
B2
DP6
B3
DP2
B4
STROBE
B5
DIRO B6
CKP C1
DP12
C2
DP8
C3
DP4
C4
CKSO+ C5
CKSO- C6
DP13
D1 DP14
D2
VDDP D3
GN D
D4
DSO-/DSI+ D5
DSO+/DSI- D6
CKSI- E6
CKSI+ E5
VDDS E4
GN D
E3
DP16
E2
DP15
E1
DIRI
F6
S2
F5
VDDA F4
DP21
F3
DP18
F2
DP17
F1
S1
J6
DP24
J5
DP23
J4
DP22
J3
DP20
J2
DP19
J1
TP3TP3
.01uF
C2
.01F
C2 C8
2.2uF
C8
2.2F
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 9
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Note
:
2. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired.
The datasheet specification should be met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside
datasheet specifications.
Symbol Parameter Min. Max. Unit
V
DD
Supply Voltage -0.5 +4.6 V
ALL Input/Output Voltage -0.5 +4.6 V
I
OS
CTL Output Short-Circuit Duration Continuous
T
STG
Storage Temperature Range -65 +150 °C
T
J
Maximum JunctionTemperature +150 °C
T
L
Lead Temperature (Soldering 4 Seconds) +260 °C
ESD
IEC61000-4-2 15.0
kV
Human Body Model, JESD22-A114, Serial I/O Pin 8.0
Human Body Model, JESD22-A114, All Pins 2.5
Charged Device Model, JESD22-C101 2.0
Symbol Parameter Min. Max. Unit
V
DDA
, V
DDS
Supply Voltage 2.5 3.3 V
V
DDP
Supply Voltage 1.65 3.60 V
T
A
Operating Temperature
(2.)
-30 +70 °C
V
DDA-PP
Supply Noise Voltage 100 mV
PP
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 10
DC Electrical Characteristics
Values are for over-supply voltage and operating temperature ranges, unless otherwise specified.
Typical values are
given for V
DD
= 2.775V and T
A
= 25°C. Positive current values refer to the current flowing into the device and negative
values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless otherwise specified
(except
∆
V
OD
and V
OD
).
Symbol Parameter Test Conditions Min. Typ. Max. Unit
LVCMOS I/O
V
IH
Input High Voltage 0.65 x V
DDP
V
DDP
V
IL
Input Low Voltage GND 0.35 x V
DDP
V
V
OH
Output High Voltage I
OH
= 2.0mA
V
DDP
= 3.3±0.30
0.75 x V
DDP
V V
DDP
= 2.5±-0.20
V
DDP
= 1.8±0.18
V
OL
Output Low Voltage I
OL
= 2.0mA
V
DDP
= 3.3±0.30
0.25 x V
DDP
V V
DDP
= 2.5±0.20
V
DDP
= 1.8±0.18
I
IN
Input Current V
IN
= 0V to 3.6V -5.0 5.0 µA
DIFFERENTIAL I/O
I
ODH
Output HIGH source current V
OS
= 1.0V -1.75 mA
I
ODL
Output LOW sink current V
OS
= 1.0V 0.950 mA
I
OS
Short-Circuit Output
Current
V
OUT
= 0V
Driver Enabled mA
Driver Disabled ±5 µA
I
OZ
Disabled Output
Leakage Current
CKSO, DSO = 0V to V
DDS
S2 = S1 = 0V ±1 ±5 µA
I
TH
Differential Input Threshold
High Current 50 µA
I
TL
Differential Input Threshold
Low Current -50 µA
I
IZ
Disabled Input Leakage
Current
CKSI, DSI = 0V to V
DDS
S2 = S1 = 0V ±1 ±5 µA
I
IS
Short-Circuit Input Current V
OUT
= V
DDS
mA
V
ICM
Input Common Mode
Range V
DDS
= 2.775 ±5% 0.5 V
DDS-1
V
R
TRM
CKSI, DS Internal Receiver
Termination Resistor
V
ID
= 50mV, V
IC
= 925mV, DIRI = 0
| CKSI
+
– CKSI
–
| = V
ID
100
Ω
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 11
Power Supply Currents
Typical values are given for V
DD
= 2.775V and T
A
= 25°C. Positive current values refer to the current flowing into the
device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except
∆
V
OD
and V
OD
).
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IDDA1 VDDA Serializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1 450 µA
IDDA2 VDDA Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0 550 µA
IDDS1 VDDS Serializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1 4 mA
IDDS2 VDDS Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0 4.5 mA
IDD_PD VDD Power-Down Supply Current
IDD_PD = IDDA S1 = S2 = 0 All Inputs at GND or VDD 0.1 µA
IDD_SER1
26:1 Dynamic Serializer
Power Supply Current
IDD_SER1 = IDDA+IDDS+IDDP
CKREF = STROBE
DIRI = H
S2 = 0
S1 = 1
1.2MHz
9
mA
5MHz 14
S2 = 1
S1 = 0
5MHz 9
15MHz 17
S2 = 1
S1 = 1
10MHz 9
26MHz 16
IDD_DES1
26:1 Dynamic Deserializer
Power Supply Current
IDD_DES1 = IDDA+IDDS+IDDP
CKREF = STROBE
DIRI = L
S2 = 0
S1 = 1
2MHz 5
mA
5MHz 6
S2 = 1
S1 = 0
5MHz 4
15MHz 5
S2 = 1
S1 = 1
10MHz 7
26MHz 11
IDD_SER2
26:1 Dynamic Serializer
Power Supply Current
IDD_SES2 = IDDA+IDDS+IDDP
NO CKREF
STROBE Active
CKSI = 15x STROBE
DIRI = H
2MHz 8
mA
5MHz 8
10MHz 10
15MHz 12
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 12
AC Electrical Characteristics
Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified.
Typical values are given for V
DD
= 2.775V and T
A
= 25°C. Positive current values refer to the current flowing into
device and negative values means current flowing out of the pins. Voltages are referenced to GROUND unless other-
wise specified (except
∆
V
OD
and V
OD
).
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Serializer Input Operating Conditions
t
TCP
CKREF Clock Period
(2MHz – 26MHz)
CKREF = STROBE
Figure 7.
S2=0 S1=1 200 500
ns S2=1 S1=0 66 200
S2=1 S1=1 38.46 100.00
f
REF
CKREF Frequency Relative to
STROBE
CKREF does not =
STROBE S2=0 S1=1 2.25 x
f
STROBE
MHz
t
CPWH
CKREF Clock High Time 0.2 0.5 T
t
CPWL
CKREF Clock Low Time 0.2 0.5 T
t
CLKT
LVCMOS Input Transition Time Figure 9. 90.0 ns
t
SPWH
STROBE Pulse Width HIGH/LOW Figure 9. (Tx4)/26 (Tx22)/26 ns
f
MAX
Maximum Serial Data Rate CKREF x 26
S2=0 S1=1 52 130
Mb/s
S2=1 S1=0 130 390
S2=1 S1=1 260 676
t
STC
DP
(n)
Setup to STROBE DIRI = 1 2.5 ns
t
HTC
DP
(n)
Hold to STROBE 2.0 ns
Serializer AC Electrical Characteristics
t
TCCD
Transmitter Clock Input to Clock
Output Delay CKREF = STROBE 33a+1.5 35a+6.5 ns
t
SPOS
CKSO Position Relative to DS
(3.)
-50 250 ps
PLL AC Electrical Characteristics
t
TPLLS0
Serializer Phase Lock Loop
Stabilization Time Figure 11. 200 µs
t
TPLLD0
PLL Disable Time Loss of Clock Figure 12. 30 µs
t
TPLLD1
PLL Power-Down Time
(4.)
Figure 13. 20 ns
Deserializer Input Operating Conditions
t
S_DS
Serial Port Setup Time,
DS-to-CKSI
(5.)
1.4 ns
t
H_DS
Serial Port Hold Time,
DS-to-CKS
(5.)
-250 ps
Deserializer AC Electrical Characteristics
t
RCOP
Deserializer Clock Output
(CKP OUT) Period
(6.)
Figure 10. 50 500 ns
t
RCOL
CKP OUT Low Time
(6.)
(Rising Edge STROBE) Serializer
source STROBE = CKREF
Figure 10.
13a-3 13a+3 ns
t
RCOH
CKP OUT High Time 13a-3 13a+3 ns
t
PDV
Data Valid to CKP LOW (Rising Edge STROBE)
Figure 10. 8a-6 8a+1 ns
t
ROLH
Output Rise Time (20% to 80%) C
L
= 8pF
Figure 7. 18 ns
t
ROHL
Output Fall Time (20% to 80%) C
L
= 8pF
Figure 7. 18 ns
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 13
Notes
:
3. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
4. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
5. Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
6.
a = (1/f)/13)
Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling
edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge of
CKSO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the
data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal
to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13
bit times.
Control Logic Timing Controls
Note
:
7. Deserializer Enable Time includes the time required for internal voltage and current references to stabilize. This time
is significantly less than the PLL Lock Time and therefore does not limit overall system startup time.
Capacitance
Symbol Parameter Test Conditions Min. Typ. Max. Units
t
PHL_DIR
,
t
PLH_DIR
Propagation Delay
DIRI-to-DIRO DIRI LOW-to-HIGH or HIGH-to-LOW 17 ns
t
PLZ
, t
PHZ
Propagation Delay
DIRI-to-DP DIRI LOW-to-HIGH 25 ns
t
PZL
, t
PZH
Propagation Delay
DIRI-to-DP DIRI HIGH-to-LOW 25 ns
t
PLZ
, t
PHZ
Deserializer Disable Time:
S0 or S1 to DP
DIRI = 0,
S1(2) = 0 and S2(1) = LOW-to-HIGH,
Figure 14.
25 ns
t
PZL
, t
PZH
Deserializer Enable Time:
S0 or S1 to DP
DIRI = 0,
(7.)
S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 14.
2 µs
t
PLZ
, t
PHZ
Serializer Disable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) = 0 and S2(1) = HIGH-to-LOW,
Figure 13.
25 ns
t
PZL
, t
PZH
Serializer Enable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH,
Figure 13.
65 ns
Symbol Parameter Test Conditions Min. Typ. Max. Units
C
IN
Capacitance of Input Only Signals,
CKREF, STROBE, S1, S2, DIRI
DIRI = 1, S1 = S2 = 0,
V
DD
= 2.5V 2 pF
C
IO
Capacitance of Parallel Port Pins
DP
1:12
DIRI = 1, S1 = S2 = 0,
V
DD
= 2.5V 2 pF
C
IO-DIFF
Capacitance of Differential I/O
Signals
DIRI = 0, S1 = S2 = 0,
V
DD
= 2.775V 2 pF
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 14
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
AC Loading and Waveforms
Figure 7. LVCMOS Output Load and Transition
Times
Figure 8. Serial Setup and Hold Times
Figure 9. LVCMOS Clock Parameters Figure 10. Deserializser Data Valid Window Time and
Clock Output Parameters
Figure 11. Serializer PLL Lock Time
tROLH
20%
DPn
DPn
20%
80% 80%
8pF
tROHL
CKREF
tCLKT
90% 90%
10% 10%
50% 50%
tCLKT
VIH
VIL
tTCP
tCPWH tCPWL
CKP
DP[1:12]
tPDV
Data
Data Time
EN_DES = “1”, CKSI and DSI are valid signals
CKREF 50% 75% 50%
25%
tRCOP
tRCOH tRCOL
Setup:
CKS0
CKREF
S1 or S2
VDD/VDDA
tTPLLS0
Note: CKREF Signal is free running.
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 15
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
AC Loading and Waveforms
(Continued)
Figure 12. PLL Loss of Clock Disable Time
Figure 13. PLL Power-Down Time Figure 14. Serializer Enable and Disable Time
Figure 15. Deserializer Enable and Disable Times
CKS0
CKREF
tTPPLD0
Note: CKREF Signal can be stopped either High or LOW
CKS0
S1 or S2
tTPPLD1
DS+,CKS0+
HIGHZ
DS+,CKS0-
S1 or S2
tPLZ(HZ) tPZL(ZH)
Note: CKREF must be active and PLL must be stable
S1 or S2
DP
tPLZ(HZ) tPZL(ZH)
Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 16
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Tape and Reel Specification
MLP Embossed Tape Dimension
Dimensions are in millimeters.
Notes
:
Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C
).
Shipping Reel Dimension
Dimensions are in millimeters.
Package
A
0
±0.1
B
0
±0.1
D
±0.05
D
1
Min.
E
±0.1
F
±0.1
K
0
±0.1
P
1
Typ.
P
0
Typ.
P
2
±0/05
T
Typ.
T
C
±0.005
W
±0.3
W
C
Typ.
5 x 5 5.35 5.35 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0.07 12.00 9.30
6 x 6 6.30 6.30 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0.07 12.00 9.30
Tape
Width
Dia A
Max.
Dim B
Min.
Dia C
+0.5/–0.2
Dia D
Min.
Dim N
Min.
Dim W1
+2.0/–0
Dim W2
Max.
Dim W3
(LSL–USL)
8 330.0 1.5 13.0 20.2 178.0 8.4 14.4 7.9 ~ 10.4
12 330.0 1.5 13.0 20.2 178.0 12.4 18.4 11.9 ~ 15.4
16 330.0 1.5 13.0 20.2 178.0 16.4 22.4 15.9 ~ 19.4
P1
A0D1
P0P2
F
W
E
D
B0
Tc
Wc
K0
T
User Direction of Feed
10° maximum component rotation
Sketch C (Top View)
Component lateral movement
Typical component
cavity center line
1.0mm
maximum
W1 Measured at Hub
Dia A
max
Dia D
min
B Min
Dia C
Dia N
See detail AA
DETAIL AA
W3
W2 max Measured at Hub
1.0mm
maximum
Typical component
center line
10° maximum
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 17
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Physical Dimensions
Figure 16. 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO0220, 6mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION
WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION..
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994.
D. LAND PATTERN PER IPC SM-782.
E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.
F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR
TIE BAR PROTRUSIONS.
G. DRAWING FILENAME: MKT-MLP40Arev3.
6.00
6.00
0.80 MAX
0.10 C
SEATING
PLANE
0.08 C 0.05
0.00
(0.20)
C
0.15 C
0.15 C
PIN #1 IDENT
0.50
4.20
4.00 0.50
0.30
4.20
4.00
0.50 0.10 C A B
0.05 C
0.18-0.30
A
B
6.38MIN
0.20MIN
4.77MIN
4.37MAX
0.28 MAX 0.50TYP
(0.80)
X4
X40
E
(DATUM A)
(DATUM B)
PIN #1 ID
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 18
Physical Dimensions
(Continued)
Figure 17. 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
Note: Click here for tape and reel specifications, available at:
http://www.fairchildsemi.com/products/analog/packaging/bga42.html.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
BOTTOM VIEW
3.50
4.50
0.5
0.5
3.0
2.5
Ø0.3±0.05
SEATING PLANE
0.23±0.05
0.45±0.05
(0.75)
(0.5)(0.35)
(0.6)
0.08 C
0.10 C
0.10 C
0.89±0.082
1.00 MAX
0.21±0.04
(QA CONTROL VALUE)
0.10 C
C
0.15 C A B
0.05 C
X42
TERMINAL
A1 CORNER
INDEX AREA
2X
2X
0.2+0.1
-0.0
LAND PATTERN
RECOMMENDATION
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN224AC Rev.1.1.6 19