AS7C3256A-12PCN - Alliance Memory, Inc.

October 2003

AS7C3256A

10/22/03; v.1.1 Alliance Semiconductor P. 1 of 9

3.3V 32K X 8 CMOS SRAM (Common I/O)

Features

• Pin compatible with AS7C3256

• Industrial and commercial temperature options

• Organization: 32,768 words × 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5, 6, 7, 8 ns output enable access time

• Very low power consumption: ACTIVE

- 180mW max @ 10 ns

• Very low power consumption: STANDBY

- 7.2 mW max CMOS I/O

• Easy memory expansion with

and

inputs

• TTL-compatible, three-state I/O

• 28-pin JEDEC standard packages

- 300 mil PDIP

- 300 mil SOJ

-8 × 13.4 mm TSOP 1

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Logic block diagram

256 X 128 X 8

Array

(262,144)

Input buffer

I/O0

I/O7

VCC

GND

Column decoder

Row decoder

Control

circuit

Sense amp

Pin arrangement

VCC

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

A14

A12

A3 A2

I/O0

I/O1

I/O2

GND

AS7C3256A

VCC

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

A14

A12

I/O0

I/O1

I/O2

GND

AS7C3256A

28-pin TSOP 1 (8×13.4 mm) 28-pin DIP, SOJ (300 mil)

Selection guide

-10 -12 -15 -20 Unit

Maximum address access time 10 12 15 20 ns

Maximum output enable access time 5 6 7 8 ns

Maximum operating current 50 45 40 35 mA

Maximum CMOS standby current 2 2 2 2 mA

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Functional description

The AS7C3256A is a 3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device

organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage,

including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques

permit 3.3V operation without sacrificing performance or operating margins.

The device enters standby mode when

is high. CMOS standby mode consumes ≤3.6 mW. Normal operation offers 75%

power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns

are ideal for high-performance applications. The chip enable (

) input permits easy memory expansion with multiple-bank

memory organizations.

A write cycle is accomplished by asserting chip enable (

) and write enable (

) LOW. Data on the input pins I/O0-I/O7

is written on the rising edge of

(write cycle 1) or

(write cycle 2). To avoid bus contention, external devices should

drive I/O pins only after outputs have been disabled with output enable (

) or write enable (

A read cycle is accomplished by asserting chip enable (

) and output enable (

) LOW, with write enable (

) high. The

chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write

enable is low, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible. Operation is from a single 3.3 ±0.3V supply. The AS7C3256A is packaged

in high volume industry standard packages.

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Key: X = Don’t care, L = Low, H = High

Parameter Symbol Min Max Unit

Voltage on VCC relative to GND Vt1 –0.5 +5.0 V

Voltage on any pin relative to GND Vt2 –0.5 VCC + 0.5 V

Power dissipation PD–1.0W

Storage temperature (plastic) Tstg –65 +150 oC

Ambient temperature with VCC applied Tbias –55 +125 oC

DC current into outputs (low) IOUT –20mA

CE WE OE

Data Mode

H X X High Z Standby (ISB, ISB1)

L H H High Z Output disable (ICC)

LHLD

OUT Read (ICC)

LLXD

IN Write (ICC)

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10/22/03; v.1.1 Alliance Semiconductor P. 3 of 9

Recommended operating conditions

* VIL min = –2.0V for pulse width less than tRC/2.

DC operating characteristics (over the operating range)1

Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2

Parameter Symbol Min Typical Max Unit

Supply voltage VCC 3.0 3.3 3.6 V

Input voltage VIH 2.0 – VCC+0.5 V

VIL*-0.5*–0.8V

Ambient operating temperature commercial TA0–70

industrial TA–40 – 85 oC

Parameter Sym Test conditions

-10 -12 -15 -20

UnitMin Max Min Max Min Max Min Max

Input leakage

current |ILI|VCC = Max,

Vin = GND to VCC

–1–1–1–1µA

Output leakage

current |ILO|VCC = Max,

VOUT = GND to VCC

–1–1–1–1µA

Operating

power supply

current

ICC

VCC = Max, CE ≤ VIL

f = fMax, IOUT = 0mA –50–45–40–35mA

Standby power

supply current

ISB

VCC = Max, CE ≤ VIL

f = fMax, IOUT = 0mA –20–20–20–20mA

ISB1

VCC = Max, CE > VCC–0.2V

VIN < GND + 0.2V or

VIN > VCC–0.2V, f = 0

–2.0–2.0–2.0–2.0mA

Output voltage VOL IOL = 8 mA, VCC = Min –0.4–0.4–0.4–0.4V

VOH IOH = –4 mA, VCC = Min 2.4–2.4–2.4–2.4– V

Parameter Symbol Signals Test conditions Max Unit

Input capacitance CIN A,

Vin = 0V 5 pF

I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF

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Read cycle (over the operating range)3,9

Key to switching waveforms

Read waveform 1 (address controlled)3,6,7,9

Read waveform 2 (CE controlled)3,6,8,9

Parameter Symbol

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

Read cycle time tRC 10–12–15–20–ns

Address access time tAA – 10 – 12 – 15 – 20 ns 3

Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns 3

Output enable (OE) access time tOE –5–6–7–8ns

Output hold from address change tOH 3–3–3–3–ns5

CE LOW to output in low Z tCLZ 3–3–3–3–ns4, 5

CE HIGH to output in high Z tCHZ –3–3–4–5ns4, 5

OE LOW to output in low Z tOLZ 0–0–0–0–ns4, 5

OE HIGH to output in high Z tOHZ –3–3–4–5ns4, 5

Power up time tPU 0–0–0–0–ns4, 5

Power down time tPD – 10 – 12 – 15 – 20 ns 4, 5

Undefined output/don’t careFalling inputRising input

Address

out

Data valid

tAA

Supply

current

out

RC1

OLZ

ACE

CHZ

CLZ

50% 50%

OHZ

Data valid

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Write cycle (over the operating range)11

Write waveform 1 (WE controlled)10,11

Write waveform 2 (CE controlled)10,11

Parameter Symbol

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

Write cycle time tWC 10–12–15–20–ns

Chip enable to write end tCW 8 – 8 –10–12–ns

Address setup to write end tAW 8 – 8 –10–12–ns

Address setup time tAS 0–0–0–0–ns

Write pulse width tWP 7–8–9–12–ns

Write recovery time tWR 0–0–0–0–ns

Address hold from end of write tAH 0–0–0–0–ns

Data valid to write end tDW 5–6–8–10–ns

Data hold time tDH 0–0–0–0–ns4, 5

Write enable to output in high Z tWZ –5–6–7–8ns4, 5

Output active from write end tOW 3–3–3–3–ns4, 5

Address

out

Data valid

Address

out

Data valid

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AC test conditions

Notes

1During V

CC power-up, a pull-up resistor to VCC on

is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B.

4 These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±500mV from steady-state voltage.

5 This parameter is guaranteed, but not tested.

is High for read cycle.

and

are Low for read cycle.

8 Address valid prior to or coincident with

transition Low.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 All write cycle timings are referenced from the last valid address to the first transitioning address.

11 CE1 and CE2 have identical timing.

12 C=30pF, except on High Z and Low Z parameters, where C=5pF.

350

Ω

C(12)

320

Ω

out

GND

+3.3V

168

Ω

out

+1.72V

Figure B: Output load

Thevenin equivalent

- Output

: see F

gure B

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

10%

90%

10%

90%

GND

+3.0V

Figure A: Input pulse

2 ns

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Package diagrams

Seating

bA1

E1 E

Plane

Pin 1

28-pin PDIP

Min Max

in inches

A- 0.175

A1 0.010 -

B0.058 0.064

b0.016 0.022

c0.008 0.014

D- 1.400

E0.295 0.320

E1 0.278 0.298

e0.100 BSC

eA 0.330 0.370

L0.120 0.140

a0° 15°

S- 0.055

28-pin SOJ

Min Max

in inches

A0.128 0.148

A1 0.026 -

A2 0.095 0.105

B0.026 0.032

b0.016 0.020

c0.007 0.010

D0.720 0.730

E0.255 0.275

E1 0.295 0.305

E2 0.330 0.340

e0.050 BSC

28-pin TSOP1

8×13.4 mm

Min Max

A1.00 1.20

A1 0.05 0.15

A2 0.91 1.05

b0.17 0.27

c0.10 0.20

D11.70 11.90

e0.55 nominal

E7.90 8.10

Hd 13.20 13.60

L0.50 0.70

α0° 5°

Pin 1

Seating

Plane

LA1AA2

28-pin PDIP

28-pin SOJ

28-pin TSOP1

AS7C3256A

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Ordering information

Note: Add suffix ‘N’to the above part number for lead free parts. (Ex. AS7C3256A-10JIN)

Part numbering system

Package / Access time Volt/Temp 10 ns 12 ns 15 ns 20 ns

Plastic DIP, 300 mil 3.3V commercial AS7C3256A-10PC AS7C3256A-12PC AS7C3256A-15PC AS7C3256A-20PC

Plastic SOJ, 300 mil 3.3V commercial AS7C3256A-10JC AS7C3256A-12JC AS7C3256A-15JC AS7C3256A-20JC

3.3V industrial AS7C3256A-10JI AS7C3256A-12JI AS7C3256A-15JI AS7C3256A-20JI

TSOP 8x13.4mm 3.3V commercial AS7C3256A-10TC AS7C3256A-12TC AS7C3256A-15TC AS7C3256A-20TC

3.3V industrial AS7C3256A-10TI AS7C3256A-12TI AS7C3256A-15TI AS7C3256A-20TI

AS7C 3 256A –XX XC or I X

SRAM prefix

Voltage:

3 = 3.3V supply Device number Access time

Packages:

P = PDIP 300 mil

J = SOJ 300 mil

T = TSOP 8x13.4mm

Temperature range:

C = 0 oC to 70 0C

I = -40C to 85C

N= Lead Free Part

Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

Part Number: AS7C3256A

Document Version: v.1.1

trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make

changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.

The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at

any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in

this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any

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intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems

where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-

supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

AS7C3256A