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FEATURES
APPLICATIONS
DIVIDER
DIVIDER
SDA/SCL
VCO
PLL
Differential
LVDSInput
30MHz 319MHz-
1Bypass
CMLOutput
5Differential
CMLOutputs
15MHz 1.25GHz-
5Differential
CMLOutputs
15MHz 1.25GHz-
CDCL6010
SLLS780 – FEBRUARY 2007
1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer
•Meets ANSI TIA/EIA-644-A-2001 LVDSStandard Requirements•Single 1.8V Supply
•Integrated LC Oscillator Allows External•High-Performance Clock Multiplier,
Bandwidth AdjustmentDistributor, Jitter Cleaner, and Buffer With 11Outputs •PLL Lock Indication•Low Output Jitter: 400fs RMS •Power Consumption: 640mW Typical•Output Group Phase Adjustment •Output Enable Control for Each Output•Low-Voltage Differential Signaling (LVDS) •SDA/SCL Device Management InterfaceInput, 100 ΩDifferential On-Chip Termination,
•48-pin QFN (RGZ) Package30MHz to 319MHz Frequency Range
•Industrial Temperature Range: –40 °C to +85 °C•Differential Current Mode Logic (CML)Outputs, 50 ΩSingle-Ended On-ChipTermination, 15MHz to 1.25GHz Frequency
•Low Jitter Clocking for High-Speed SERDESRange
•Jitter Cleaning of SERDES Reference Clocks•One Dedicated Differential CML Output,
for 1G/10G Ethernet, 1X/2X/4X/10X FibreStraight PLL and Frequency Divider Bypass
Channel, PCI Express, Serial ATA, SONET,CPRI, OBSAI, etc.•Two Groups of Five Outputs Each with
•Up to 1-to-11 Clock Buffering and Fan-outIndependent Frequency Division Ratios;Optional PLL Bypass•Fully Integrated Voltage Controlled Oscillator(VCO); Supports Wide Output FrequencyRange
•Output Frequency Derived From VCOFrequency with Divide Ratios of 1, 2, 4, 5, 8,10, 16, 20, 32, 40, and 80•Meets OBSAI RP1 v1.0 Standard andCPRI v2.0 Requirements
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION
CDCL6010
SLLS780 – FEBRUARY 2007
The CDCL6010 is a high-performance, low phase The CDCL6010 supports one differential LVDS clocknoise clock multiplier, distributor, jitter cleaner, and input and a total of 11 differential CML outputs. Onelow skew buffer. It effectively cleans a noisy system output is a straight bypass with no support for jitterclock with a fully-integrated low noise Voltage cleaning or clock multiplication. The remaining 10Controlled Oscillator (VCO) that operates in the outputs are available in two groups of five outputs1.2GHz–1.275GHz range. (Note that the LC each with independent frequency division ratios.oscillator oscillates in the 2.4GHz–2.55GHz range. Those 10 outputs can be optionally setup to bypassThe frequency is predivided by 2 before the the PLL when no jitter cleaning is needed. The CMLpost-dividers P0 and P1.) outputs are compatible with LVDS receivers ifac-coupled.The output frequency (F
OUT
) is synchronized to thefrequency of the input clock (F
IN
). The programmable With careful observation of the input voltage swingpre-dividers, M and N, and the post-dividers, P0 and and common-mode voltage limits, the CDCL6010P1, give a high flexibility to the ratio of the output can support a single-ended clock input as outlined infrequency to the input frequency: the Pin Description Table .F
OUT
= F
IN
×N/(M ×P)
The CDCL6010 can operate as a multi-output clockbuffer in a PLL bypass mode.Where:
P (P0, P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80
All device settings are programmable through theSDA/SCL, serial two-wire interface.M = 1, 2, 4, 8N = 32, 40
The phase of one output group relative to the othercan be adjusted through the SDA/SCL interface. Forprovided that:
post-divide ratios (P0, P1) that are multiples of 5, the30MHz < (F
IN
/M) < 40MHz
total number of phase adjustment steps ( n) equals1200MHz < (F
OUT
×P) < 1275MHz
the divide-ratio divided by 5. For post-divide ratios(P0, P1) that are not multiples of 5, the total numberThe PLL loop bandwidth is user-selectable by
of steps ( n) is the same as the post-divide ratio. Theexternal filter components or by using the internal
phase adjustment step ( ∆ Φ ) in time units is given as:loop filter. The PLL loop bandwidth and damping
∆ Φ = 1/(n ×F
OUT
)factor can be adjusted to meet different systemrequirements.
where F
OUT
is the respective output frequency.
The device operates in a 1.8V supply environmentand is characterized for operation from –40 °C to+85 °C.
The CDCL6010 is available in a 48-pin QFN (RGZ)package.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
CDCL6010
SLLS780 – FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
AVAILABLE OPTIONS
(1)
T
A
PACKAGED DEVICES FEATURES
–40 °C to +85 °C CDCL6010RGZT 48-pin QFN (RGZ) Package, small tape and reel–40 °C to +85 °C CDCL6010RGZR 48-pin QFN (RGZ) Package, tape and reel
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet orrefer to our web site at www.ti.com .
over operating free-air temperature range (unless otherwise noted).
(1)
VALUE UNIT
V
DD
, AV
DD
Supply voltage
(2)
–0.3 to 2.5 VV
LVDS
Voltage range at LVDS input pins
(2)
–0.3 to 4.0 VV
I
Voltage range at all non-LVDS input pins
(2)
–0.3 to 3.0 VESD Electrostatic discharge (HBM) 2 kVT
J
Junction temperature +125 °CT
STG
Storage temperature range –65 to +150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingcondition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
Over operating free-air temperature range (unless otherwise noted).
MIN NOM MAX UNIT
V
DD
Digital supply voltage 1.7 1.8 1.9 VAV
DD
Analog supply voltage 1.7 1.8 1.9 VT
A
Ambient temperature (no airflow, no heatsink) –40 +85 °CT
J
Junction temperature +105 °Cθ
JA
Junction-to-ambient thermal resistance
(1)
:airflow = 0 lfm 28.3 °C/Wairflow = 50 lfm 22.4
(1) No heatsink; power uniformly distributed; 36 ground vias (6 x 6 array) tied to the thermal exposed pad; 4-layer high-K board.
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DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
CDCL6010
SLLS780 – FEBRUARY 2007
Over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
VDD
Total current from digital 1.8V supply All outputs enabled; V
DD
= V
DD,typ
270 mA30.72MHz input; 61.44MHz outputI
AVDD
Total current from analog 1.8V supply All outputs enabled; AV
DD
= V
DD,typ
85 mA30.72MHz input; 61.44MHz outputV
IL,CMOS
Low level CMOS input voltage V
DD
= 1.8V –0.2 0.6 VV
IH,CMOS
High level CMOS input voltage V
DD
= 1.8V V
DD
– 0.6 V
DD
VI
IL,CMOS
Low level CMOS input current V
DD
= V
DD,max
, V
IL
= 0.0V –120 µAI
IH,CMOS
High level CMOS input current V
DD
= V
DD,max
, V
IH
= 1.9V 65 µAV
OL,SDA
Low level CMOS output voltage for the
Sink current = 3mA 0 0.2V
DD
VSDA pinI
OL,CMOS
Low level CMOS output current 8 mA
Over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Differential input impedance for the LVDS inputZ
D,IN
90 132 Ωterminals
V
CM,IN
Common-mode voltage, LVDS input 1125 1200 1375 mV
V
S,IN
Single-ended LVDS input voltage swing 100 600 mV
PP
V
D,IN
Differential LVDS input voltage swing 200 1200 mV
PP
t
R,OUT
,
Output signal rise/fall time 20%–80% 100 pst
F,OUT
V
CM,OUT
Common-mode voltage, CML outputs V
DD
–0.31 V
DD
–0.23 V
DD
–0.19 V
V
S,OUT
Single-ended CML output voltage swing ac-coupled 180 230 280 mV
PP
V
D,OUT
Differential CML output voltage swing ac-coupled 360 460 560 mV
PP
F
IN
Clock input frequency 30 319 MHz
F
OUT
Clock output frequency 15 1250 MHz
L
OUT
Residual clock output phase noise F
IN
= 30.72MHz , F
OUT
= 61.44MHz400kHz PLL bandwidth
at 10Hz offset –103 dBc/Hz
at 100Hz offset –114 dBc/Hz
at 1kHz offset –123 dBc/Hz
at 10kHz offset –121 dBc/Hz
at 100kHz offset –119 dBc/Hz
at 1MHz offset –138 dBc/Hz
at 10MHz offset –152 dBc/Hz
at 20MHz offset –152 dBc/Hz
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AC ELECTRICAL CHARACTERISTICS FOR THE SDA/SCL INTERFACE
(1)
CDCL6010
SLLS780 – FEBRUARY 2007
AC ELECTRICAL CHARACTERISTICS (continued)Over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
J
OUT
Residual clock output jitter F
IN
= 30.72MHz, F
OUT
= 61.44MHz400kHz PLL bandwidth
10Hz–1MHz offset 2.01 ps RMS
1MHz–20MHz offset 0.45 ps RMS
12kHz–20MHz offset 2.11 ps RMS
T
P
Input-to-output delay F
IN
= 30.72MHz, F
OUT
= 30.72MHz
3 nsYP[9:0] outputs, PLL bypass mode
F
IN
= 30.72MHz, F
OUT
= 61.44MHz
150 psYP[9:0] outputs, PLL mode
F
IN
= 30.72MHz, F
OUT
= 61.44MHzTS
OUT
Clock output skew –64 64 psYP[9:0] outputs relative to YP[0]
DCycle
OUT
Clock output duty cycle
(1)
45 55 %
(1) Output duty cycle of the bypass output and for post-divide ratio = 1 is just as good as the input duty cycle.
PARAMETER MIN TYP MAX UNIT
f
SCL
SCL frequency 400 kHzt
h(START)
START hold time 0.6 µst
w(SCLL)
SCL low-pulse duration 1.3 µst
w(SCLH)
SCL high-pulse duration 0.6 µst
su(START)
START setup time 0.6 µst
h(SDATA)
SDA hold time 0 µst
su(DATA)
SDA setup time 0.6 µst
r(SDATA)
SCL / SDA input rise time 0.3 µst
f(SDATA)
SCL / SDA input fall time 0.3 µst
su(STOP)
STOP setup time 0.6 µst
BUS
Bus free time 1.3 µs
(1) See Figure 4 for the timing behavior.
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DEVICE INFORMATION
VCP
AVDD
CLKP
CLKN
AVDD
YP0
YN0
VDD
YP1
YN1
VDD
VSS
ADD0
VDD
YN7
YP7
VDD
YN6
YP6
VDD
YN5
YP5
VDD
SDA
1
2
3
4
5
6
7
8
9
10
13
16
19
22
11
14
17
20
23
12
15
18
21
24
36
35
34
33
32
31
30
29
28
27
26
25
CDCL6010
STATUS 48
45
42
39
47
44
41
38
46
43
40
37
VCN
YN9
YP10
YP8
AVDD
VDD
AVDD
VDD
YN10
YN8
YP9
ADD1
VDD
YP2
YN2
VDD
YP3
YN3
VDD
YP4
YN4
VDD
SCL
NOTE:Exposedthermalpadmustbesolderedto VSS.
CDCL6010
SLLS780 – FEBRUARY 2007
48-PIN QFN (RGZ)(TOP VIEW)
The CDCL6010 is available in a 48-pin QFN (RGZ) package with a pin pitch of 0,5mm. The exposed thermal padserves both thermal and electrical grounding purposes.
NOTE:
The device must be soldered to ground (V
SS
) using as many ground vias as possible.The device performance will be severely impacted if the exposed thermal pad is notgrounded appropriately.
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CDCL6010
SLLS780 – FEBRUARY 2007
DEVICE INFORMATION (continued)TERMINAL FUNCTIONS
TERMINAL
NAME PIN NO. TYPE DESCRIPTION
8, 11, 14,17,
20, 23, 26,V
DD
Power 1.8V digital power supply.29, 32, 35,38, 41AV
DD
2, 5, 44, 47 Power 1.8V analog power supply.ExposedV
SS
thermal pad Power Ground reference.and pin 12VCP, VCN 1, 48 I External loop filter terminals.Differential LVDS input. Single-ended 1.8V input can be dc-coupled to pin 3 with pin 4 eitherCLKP, CLKN 3, 4 I
tied to pin 3 (recommended) or left open.YP0, YN0 6, 7YP1, YN1 9, 10YP2, YN2 15, 16YP3, YN3 18, 19YP4, YN4 21, 22 10 differential CML outputs with support for jitter cleaning and clock multiplication. SupportOYP5, YN5 27, 28 optional PLL bypass mode when jitter cleaning is not needed.YP6, YN6 30, 31YP7, YN7 33, 34YP8, YN8 40, 39YP9, YN9 43, 42YP10, YN10 46, 45 O Differential CML output. Straight bypass with no jitter cleaning and no clock multiplication.SCL 24 I SDA/SCL serial clock pin. Open drain. Always connect to a pull-up resistor.SDA 25 I/O SDA/SCL bidirectional serial data pin. Open drain. Always connect to a pull-up resistor.STATUS 13 O LVCMOS status signaling. High status indicates PLL lock.Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixedADD1, ADD0 37, 36 I
most significant bits (ADD[6:2]) of the 7-bit device address are 11010.
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VDD
CLKN
CLKP
YN[4:0]
YP[4:0]
YN[9:5]
YP[9:5]
SDA/SCL
PLLBypass
Outputs orDisabletoLow 3-State
PostDividerSetting
PLLSetting
VCNVCP
STATUS
PLL_LOCK
Control
I
LPF
ExternalLow-PassFilter
AVDD
LVDS
CML
CML
YN10
YP10
R
C1
C2
SDA/SCL
DividerM
VSS
Control
CML
CML
CML
Divider N
PFD
CP
VCO
2¸
Internal
LPF
MUX
MUX
Divider
P1
Divider
P0
CDCL6010
SLLS780 – FEBRUARY 2007
FUNCTIONAL BLOCK DIAGRAM
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TYPICAL CHARACTERISTICS
-250
-200
-150
-100
-50
0
50
100
150
200
250
0 0.5 1 1.5 2
t-Time-ns
DifferentialOutputVoltage-mV
-300
-200
-100
0
100
200
300
0 10 20 30 40 50
t-Time-ns
DifferentialOutputVoltage-mV
-160
-150
-140
-130
-120
-110
-100
-90
-80
10 100 1k
OffsetFrequency-Hz
PhaseNoise-dBc/Hz
10k 100k 1M 10M 100M
CDCL6010
SLLS780 – FEBRUARY 2007
Typical operating conditions are at V
DD
= 1.8V and T
A
= +25 °C, V
D,IN
= 200mV
PP
(unless otherwise noted).
TRANSIENT PERFORMANCE: TRANSIENT PERFORMANCE:F
IN
= 30.72MHz, F
OUT
= 61.44MHz F
IN
= 250MHz, F
OUT
= 1.25GHz
Figure 1. Figure 2.
PHASE NOISE: F
IN
= 30.72MHz, F
OUT
= 61.44MHz
Figure 3.
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SDA/SCL INTERFACE
SDA/SCL Bus Slave Device Address
Command Code Definition
CDCL6010
SLLS780 – FEBRUARY 2007
This section describes the SDA/SCL interface of the The device address is made up of the fixed internalCDCL6010 device. The CDCL6010 operates as a address, 11010 (A6:A2), and configurable externalslave device of the industry standard 2-pin SDA/SCL pins ADD1 (A1) and ADD0 (A0). Four differentbus. It operates in the fast-mode at a bit-rate of up to devices with addresses 1101000, 1101001, 1101010400kbit/s and supports 7-bit addressing compatible and 1101011, can be addressed via the samewith the popular two-pin serial interface standard. SDA/SCL bus interface. The least significant bit ofthe address byte designates a write or readoperation.
A6 A5 A4 A3 A2 A1 A0 R/W
R/W Bit:1 1 0 1 0 ADD1 ADD0 0/1
0 = Write to CDCL6010 device1 = Read from CDCL6010 device
BIT DESCRIPTION
C7 1 = Byte Write / Read or Word Write / Read operation(C6:C0) Byte Offset for Byte Write / Read and Word Write / Read operation.
Command Code for Byte Write / Read HexOperation Code C7 C6 C5 C4 C3 C2 C1 C0
Byte 0 80h 1 0 0 0 0 0 0 0Byte 1 81h 1 0 0 0 0 0 0 1Byte 2 82h 1 0 0 0 0 0 1 0Byte 3 83h 1 0 0 0 0 0 1 1Byte 4 84h 1 0 0 0 0 1 0 0Byte 5 85h 1 0 0 0 0 1 0 1Byte 6 86h 1 0 0 0 0 1 1 0Byte 7 87h 1 0 0 0 0 1 1 1
Command Code for Word Write / Read HexOperation Code C7 C6 C5 C4 C3 C2 C1 C0
Word 0: Byte 0 and byte 1 80h 1 0 0 0 0 0 0 0Word 1: Byte 1 and byte 2 81h 1 0 0 0 0 0 0 1Word 2: Byte 2 and byte 3 82h 1 0 0 0 0 0 1 0Word 3: Byte 3 and byte 4 83h 1 0 0 0 0 0 1 1Word 4: Byte 4 and byte 5 84h 1 0 0 0 0 1 0 0Word 5: Byte 5 and byte 6 85h 1 0 0 0 0 1 0 1Word 6: Byte 6 and byte 7 86h 1 0 0 0 0 1 1 0Word 7: Byte 7 87h 1 0 0 0 0 1 1 1
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SDA/SCL Timing Characteristics
SDA/SCL Programming Sequence
1 7 1 1 81 1
S SlaveAddress DataByte
Wr A A P
S
Sr
Rd
Wr
A
N
P
Startcondition
Repeatedstartcondition
Read(bitvalue=1)
Write(bitvalue=0)
Acknowledge(bitvalue=0)
Notacknowledge(bitvalue=1)
Stopcondition
MastertoSlavetransmission
SlavetoMastertransmission
CDCL6010
SLLS780 – FEBRUARY 2007
Figure 4. Timing Diagram for the SDA/SCL Serial Control Interface
LEGEND FOR PROGRAMMING SEQUENCE
Byte Write Programming Sequence:171181811
S Slave Address Wr A Command Code A Data Byte A P
Byte Read Programming Sequence:1 7 1 1 8 1 1 7 1 1 8 1 1
Wr CommandS Slave Address A A S Slave Address Rd A Data Byte N PCode
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SDA/SCL Bus Configuration Command Bitmap
Byte 0:
Byte 1:
Byte 2:
CDCL6010
SLLS780 – FEBRUARY 2007
Word Write Programming Sequence:17118181811
S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A P
Word Read Programming Sequence:171181171181811
Slave Command SlaveS Wr A A S Rd A Data Byte A Data Byte N PAddress Code Address
Power UpBit Bit Name Description/Function Type Condition Reference To
7 PLL-LOCK 1 if PLL has achieved lock, otherwise 0 R 06 MANF[6] Manufacturer reserved R5 MANF[5] Manufacturer reserved R4 MANF[4] Manufacturer reserved R3 MANF[3] Manufacturer reserved R2 MANF[2] Manufacturer reserved R1 MANF[1] Manufacturer reserved R0 MANF[0] Manufacturer reserved R
Power UpBit Bit Name Description/Function Type Condition Reference To
7 RES Reserved R/W 06 RES Reserved R/W 05 ENPH Phase select enable R/W 14 PH1[4] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4 ,Table 53 PH1[3] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4 ,Table 52 PH1[2] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4 ,Table 51 PH1[1] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4 ,Table 50 PH1[0] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4 ,Table 5
Power UpBit Bit Name Description/Function Type Condition Reference To
7 RES Reserved R/W 06 RES Reserved R/W 05 ENP1 Post-divider P1 enable; if 0 output YP[9:5] and YN[9:5] are disabled R/W 14 ENBP1 Bypass PLL for post-divider P1: If 1 input is CLKP/CLKN, if 0 input is PLL R/W 0clock3 SELP1[3] Divide ratio select for post-divider P1 R/W 0 Table 12 SELP1[2] Divide ratio select for post-divider P1 R/W 1 Table 11 SELP1[1] Divide ratio select for post-divider P1 R/W 1 Table 10 SELP1[0] Divide ratio select for post-divider P1 R/W 1 Table 1
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Byte 3:
Byte 4:
Byte 5:
CDCL6010
SLLS780 – FEBRUARY 2007
Bit Power UpBit Name Description/Function Type Condition Reference To
7 RES Reserved R/W 06 RES Reserved R/W 05 PLLLOC PLL Lock Overwrite: If 1 output not gated by PLL Lock status. R/W 0K OW4 PH0[4] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4 ,Table 53 PH0[3] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4 ,Table 52 PH0[2] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4 ,Table 51 PH0[1] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4 ,Table 50 PH0[0] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4 ,Table 5
Power UpBit Bit Name Description/Function Type Condition Reference To
7 RES Reserved R/W 06 RES Reserved R/W 05 ENP0 Post-divider P0 enable. If 0, output YP[4:0] and YN[4:0] are disabled R/W 14 ENBP0 Bypass PLL for post-divider P0. If 1, input is CLKP/CLKN; if 0 input is PLL R/W 0clock3 SELP0[3] Divide ratio select for post-divider P0 R/W 0 Table 12 SELP0[2] Divide ratio select for post-divider P0 R/W 1 Table 11 SELP0[1] Divide ratio select for post-divider P0 R/W 1 Table 10 SELP0[0] Divide ratio select for post-divider P0 R/W 1 Table 1
Power UpBit Bit Name Description/Function Type Condition Reference To
7 EN Chip enable; if 0 chip is in Iddq mode R/W 16 ENDRV10 YP10, YN10 enable; if 0 output is disabled R/W 15 ENDRV9 YP[9], YN[9] enable; if 0 output is disabled R/W 14 ENDRV8 YP[8], YN[8] enable; if 0 output is disabled R/W 13 ENDRV7 YP[7], YN[7] enable; if 0 output is disabled R/W 12 ENDRV6 YP[6], YN[6] enable; if 0 output is disabled R/W 11 ENDRV5 YP[5], YN[5] enable; if 0 output is disabled R/W 10 ENDRV4 YP[4], YN[4] enable; if 0 output is disabled R/W 1
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Byte 6:
Byte 7:
CDCL6010
SLLS780 – FEBRUARY 2007
Power UpBit Bit Name Description/Function Type Condition Reference To
7 ENDRV3 YP[3], YN[3] enable; if 0 output is disabled R/W 16 ENDRV2 YP[2], YN[2] enable; if 0 output is disabled R/W 15 ENDRV1 YP[1], YN[1] enable; if 0 output is disabled R/W 14 ENDRV0 YP[0], YN[0] enable; if 0 output is disabled R/W 13 SELBW[3] PLL BW select; if 1 external loop filter is expected R/W 0 Table 62 SELBW[2] PLL BW select; if 1 external loop filter is expected R/W 0 Table 61 SELBW[1] PLL BW select; if 1 external loop filter is expected R/W 0 Table 60 SELBW[0] PLL BW select; if 1 external loop filter is expected R/W 0 Table 6
Bit Power UpBit Name Description/Function Type Condition Reference To
7 ENPLL PLL enable; if 0 PLL is switched off R/W 16 RES Reserved R/W 05 SELM[1] Divide ratio select for input clock CLKP and CLKN R/W 0 Table 34 SELM[0] Divide ratio select for input clock CLKP and CLKN R/W 0 Table 33 SELN[3] Divide ratio select for pre-divider N (PLL clock) R/W 1 Table 22 SELN[2] Divide ratio select for pre-divider N (PLL clock) R/W 0 Table 21 SELN[1] Divide ratio select for pre-divider N (PLL clock) R/W 0 Table 20 SELN[0] Divide ratio select for pre-divider N (PLL clock) R/W 1 Table 2
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CDCL6010
SLLS780 – FEBRUARY 2007
Table 1. Divide Ratio Settings for Post-Divider P0 or P1
Divide SELP1[3] or SELP1[2] or SELP1[1] or SELP1[0] orRatio SELP0[3] SELP0[2] SELP0[1] SELP0[0] Notes
1 0 0 0 02 0 0 0 14 0 0 1 05 0 0 1 18 0 1 0 010 0 1 0 116 0 1 1 020 0 1 1 1 Default32 1 0 0 040 1 0 0 180 1 0 1 0
Table 2. Divide Ratio Settings for Divider N
Divide
Ratio SELN[3] SELN[2] SELN[1] SELN[0] Notes
32 1 0 0 040 1 0 0 1 Default
Table 3. Divide Ratio Settings for Divider M
Divide
Ratio SELM[1] SELM[0] Notes
1 0 0 Default2 0 14 1 08 1 1
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CDCL6010
SLLS780 – FEBRUARY 2007
Table 4. Phase Settings for Divide Ratio = 5, 10, 20, 40, 80
With PH0[4:0] = 00000
PH1Divide Phase LeadRatio [4] [3] [2] [1] [0] (radian) Notes
5 X X X X X 0 Phase setting not available10 X X X 0 X 0X X X 1 X (2 π/2)20 X X 0 0 X 0 00000:DefaultX X 0 1 X (2 π/4)X X 1 0 X 2(2 π/4)X X 1 1 X 3(2 π/4)40 X 0 0 0 X 0X 0 0 1 X (2 π/8)X 0 1 0 X 2(2 π/8)X 0 1 1 X 3(2 π/8)X 1 0 0 X 4(2 π/8)X 1 0 1 X 5(2 π/8)X 1 1 0 X 6(2 π/8)X 1 1 1 X 7(2 π/8)80 0 0 0 0 X 00 0 0 1 X (2 π/16)0 0 1 0 X 2(2 π/16)0 0 1 1 X 3(2 π/16)0 1 0 0 X 4(2 π/16)0 1 0 1 X 5(2 π/16)0 1 1 0 X 6(2 π/16)0 1 1 1 X 7(2 π/16)1 0 0 0 X 8(2 π/16)1 0 0 1 X 9(2 π/16)1 0 1 0 X 10(2 π/16)1 0 1 1 X 11(2 π/16)1 1 0 0 X 12(2 π/16)1 1 0 1 X 13(2 π/16)1 1 1 0 X 14(2 π/16)1 1 1 1 X 15(2 π/16)
16
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CDCL6010
SLLS780 – FEBRUARY 2007
Table 5. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32
With PH0[4:0] = 00000
PH1Divide Phase LeadRatio [4] [3] [2] [1] [0] (radian) Notes
1 X X X X X 0 Phase setting not available2 X X X X 0 0X X X X 1 (2 π/2)4 X X X 0 0 0X X X 0 1 (2 π/4)X X X 1 0 2(2 π/4)X X X 1 1 3(2 π/4)8 X X 0 0 0 0X X 0 0 1 (2 π/8)X X 0 1 0 2(2 π/8)X X 0 1 1 3(2 π/8)X X 1 0 0 4(2 π/8)X X 1 0 1 5(2 π/8)X X 1 1 0 6(2 π/8)X X 1 1 1 7(2 π/8)16 X 0 0 0 0 0X 0 0 0 1 (2 π/16)X 0 0 1 0 2(2 π/16)X 0 0 1 1 3(2 π/16)X 0 1 0 0 4(2 π/16)X 0 1 0 1 5(2 π/16)X 0 1 1 0 6(2 π/16)X 0 1 1 1 7(2 π/16)X 1 0 0 0 8(2 π/16)X 1 0 0 1 9(2 π/16)X 1 0 1 0 10(2 π/16)X 1 0 1 1 11(2 π/16)X 1 1 0 0 12(2 π/16)X 1 1 0 1 13(2 π/16)X 1 1 1 0 14(2 π/16)X 1 1 1 1 15(2 π/16)
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CDCL6010
SLLS780 – FEBRUARY 2007
Table 5. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32 (continued)
With PH0[4:0] = 00000
PH1Divide Phase LeadRatio [4] [3] [2] [1] [0] (radian) Notes
32 0 0 0 0 0 00 0 0 0 1 (2 π/32)0 0 0 1 0 2(2 π/32)0 0 0 1 1 3(2 π/32)0 0 1 0 0 4(2 π/32)0 0 1 0 1 5(2 π/32)0 0 1 1 0 6(2 π/32)0 0 1 1 1 7(2 π/32)0 1 0 0 0 8(2 π/32)0 1 0 0 1 9(2 π/32)0 1 0 1 0 10(2 π/32)0 1 0 1 1 11(2 π/32)0 1 1 0 0 12(2 π/32)0 1 1 0 1 13(2 π/32)0 1 1 1 0 14(2 π/32)0 1 1 1 1 15(2 π/32)1 0 0 0 0 16(2 π/32)1 0 0 0 1 17(2 π/32)1 0 0 1 0 18(2 π/32)1 0 0 1 1 19(2 π/32)1 0 1 0 0 20(2 π/32)1 0 1 0 1 21(2 π/32)1 0 1 1 0 22(2 π/32)1 0 1 1 1 23(2 π/32)1 1 0 0 0 24(2 π/32)1 1 0 0 1 25(2 π/32)1 1 0 1 0 26(2 π/32)1 1 0 1 1 27(2 π/32)1 1 1 0 0 28(2 π/32)1 1 1 0 1 29(2 π/32)1 1 1 1 0 30(2 π/32)1 1 1 1 1 31(2 π/32)
18
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FREQUENCY SETTINGS FOR SOME APPLICATIONS
CDCL6010
SLLS780 – FEBRUARY 2007
Table 6. PLL Bandwidth Setting
PLL SELBWBandwidth
(1)
C
1
R C
2
On-Chip Loop(kHz) [3] [2] [1] [0] (nF) ( Ω) (nF) Filter ON/OFF Notes
400 0 0 0 0 N/A N/A N/A ON Default350 0 0 1 0 2.2 8660 0 OFF300 0 0 1 1 3.3 7500 0 OFF250 0 1 0 0 4.7 6200 0 OFF200 0 1 1 0 8.2 4990 0 OFF175 1 0 0 0 10 4300 0 OFF150 1 0 1 0 15 3740 0 OFF125 1 1 1 1 22 3090 0 OFF100 1 1 1 1 33 2490 0.24 OFF75 1 1 1 1 56 1870 0.82 OFF50 1 1 1 1 150 1210 2.70 OFF20 1 1 1 1 680 470 18 OFF10 1 1 1 1 3300 220 68 OFF
(1) Refer to Functional Block Diagram for the external low pass filter architecture.
APPLICATION
PROTOCOL Output Output VCO PLL Ref Clock Ref Clock PLL Ref Clock Ref ClockClock Divider Freq Divider Divider Max Freq Divider Divider Min FreqMHz P0, P1 GHz N (max f) M (max f) MHz N (min f) M (min f) MHz
10G Ethernet 312.5 4 1.250 32 8 312.5 40 1 31.25
(XAUI) 156.25 8 1.250 32 8 312.5 40 1 31.25
78.125 16 1.250 32 8 312.5 40 1 31.25
62.5 20 1.250 32 8 312.5 40 1 31.25
1G Ethernet 250 5 1.250 40 8 250 40 1 31.25
Serial ATA 125 10 1.250 40 8 250 40 1 31.25
62.5 20 1.250 40 8 250 40 1 31.25
10X FIBRE CHANNEL 159.375 8 1.275 32 8 318.75 40 1 31.875
63.75 20 1.275 32 8 318.75 40 1 31.875
CPRI 245.76 5 1.229 40 8 245.78 40 1 30.72
122.88 10 1.229 40 8 245.78 40 1 30.72
61.44 20 1.229 40 8 245.78 40 1 30.72
30.72 40 1.229 40 8 245.78 40 1 30.72
OBSAI 153.6 8 1.229 32 8 307.2 32 1 38.4
76.8 16 1.229 32 8 307.2 32 1 38.4
PCI Express 250 5 1.250 40 8 250 40 1 31.25
Serial ATA 150 8 1.200 32 8 300 32 1 37.5
75 16 1.200 32 8 300 32 1 37.5
SONET 622.08 2 1.244 32 8 311.04 40 1 31.104
311.04 4 1.244 32 8 311.04 40 1 31.104
155.52 8 1.244 32 8 311.04 40 1 31.104
62.208 20 1.244 32 8 311.04 40 1 31.104
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDCL6010RGZR ACTIVE QFN RGZ 48 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CDCL6010RGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CDCL6010RGZT ACTIVE QFN RGZ 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CDCL6010RGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Mar-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2007
Pack Materials-Page 1
Device Package Pins Site Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCL6010RGZR RGZ 48 TAI 330 16 7.3 7.3 1.5 12 16 PKGORN
T2TR-MS
P
CDCL6010RGZT RGZ 48 TAI 330 16 7.3 7.3 1.5 12 16 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
CDCL6010RGZR RGZ 48 TAI 342.9 336.6 28.58
CDCL6010RGZT RGZ 48 TAI 342.9 336.6 28.58
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2007
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2007
Pack Materials-Page 3
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